TW434823B - Method to form the structure of metal interconnections without cutting angle - Google Patents

Abstract

A method to form the structure of metal interconnections without cutting angle is provided, which comprises: first, providing a semiconductor substrate having a first silicon nitride layer, and a first inter-metal layer formed on the silicon nitride layer; then forming a first photoresist layer; etching the first inter-metal layer; next, forming a second silicon nitride layer followed by forming a dielectric layer; then forming a second inter-metal layer, and etching the second inter-metal layer, thereby forming the third silicon nitride layer; removing part of the third silicon nitride layer; then, removing the dielectric layer in the opening followed by etching the third silicon nitride layer, the second silicon nitride layer and the first silicon nitride layer; again, forming a barrier layer followed by filling the trench by metal; and finally, planarizing the metal surface to form the metal interconnection structure by this dual damascene method.

Description

V. Description of the invention (1) ~ '— 5 -1 Field of invention: The present invention relates to a method for forming a metal interconnect structure without chamfering ® 5-2 Background of the invention: The general integrated circuit The various electronic components and circuits required for the circuit are reduced and made into an electronic product with a size of only 2 square centimeters or less. Because integrated circuits are widely used in related industries, their demand has increased rapidly and in large quantities, especially in the information industry related to computer hardware. Moreover, as electronics, information, and communications products become thinner, shorter, and faster The trend of large scale integrated circuits (Ls I), very large scale integrated circuits (VLSI) and very large scale integrated circuits (ULSI) has also been gradually developed. In the ultra-large integrated circuit (ULSI) process, electronic components are often dense to tens of millions to billions or more, which is the result of the minimum line width used is getting smaller and smaller. Undoubtedly, even in the next century, ’integrated circuit will still play a key role, and its demand is undiminished. In the conventional art, damascene is a process for manufacturing interconnects, in which trenches are formed in an insulating layer and filled with metal to form wires. Double mosaic is a kind of multilayer interconnect (

^^ 48 2 3 V. Description of the invention (2) Multi-level interconnecti) process, in which one of the inlaid trenches simultaneously forms a conductive interlayer window, which opens into the gate. In the standard dual-damascene process, the insulation layer is coated with a photoresist material, where the photoresist is exposed as a mouth-shaped image (Uask), and anisotropic is used amsotropic) etch the upper half of the insulating layer to form this 'picture'. After removing the transferred photoresist layer, the insulating layer is coated with a photoresist material, wherein the photoresist is exposed as a second mask with a pattern of wires aligned with the openings of the interlayer window. The wire layer window in the upper half of the insulating layer is anisotropically etched. At this time, the via window in the upper half of the insulating layer is also etched with silver to the lower half of the insulating layer. After the etching step is completed, metal is then filled into the vias and trenches. Dual damascene can be improved in a single metal damascene, because dual damascene allows metal to be filled in both the trench and the via window, reducing the number of process steps. Self-Aligned Via Etching is an important step in the dual damascene process. In this step, two layers of intermetallic metal Etching Stop Layer are used to achieve simultaneous silver engraving to form two layers of intermetallic wide interconnects (IMD-Via) and trenches (IMD-Trench). However, because the etch stop layer must play the role of a money mask when the interconnect is etched, the etch stop layer has a higher selection ratio to the dioxide. If the etching is not controlled properly, the shoulder (V i a Shou 1 der) of the inner line will be chamfered. Severe even makes the contours in the double mosaic disappear

434823

Non-isotropic etching through the stop layer Jade, description of the invention (3) In addition, when etching IMD-Via and IMD-Trench, the upper stop layer must be eaten through. Therefore, the photoresist cannot be too thin, or the pattern of the trench will be distorted due to the loss of photoresist. However, for advanced processes, the photoresist needs to be reduced to a better depth of focus (Depth of Focus D 0 F). Therefore, the traditional Self-Aligned Dual Damascene has encountered great challenges in the process evolution. For a process of 0. 18mm or smaller, a dual damascene process is a key technology to reduce the design rule. However, it is quite difficult to control the process space, especially in the process of forming the vias and metal trenches. For the conventional techniques, please refer to the sections -A to _. The following description will explain a conventional method for forming a dual watch structure. As shown in FIG. 1A, in the manufacturing process of the conventional double-panel structure, # is first provided—the substrate m, and on the substrate 100, a layer of stOp 12 is sequentially deposited- Inner metal (-Er2, Γ30, and a stop ⑹ 叩) layer 140. The two layers of π are made of silicon nitride. They are used to stop trench etching. Θ ° ° Stop layer 140 is used to form a photoresist layer with an interlayer window pattern. 1 60 0 As shown in the first figure B, 140 ′ is used to move In addition to photoresist layer 160.

V. Description of the invention (4) Please refer to the first figure C, on the surface of the stop layer 140, to form another intermetal layer 丨 and another stop layer 170 on the opening of the interlayer window on the inner metal dielectric layer 130, And another layer of photoresist layer 16m having a trench line pattern. As shown in the first figure D, the trench pattern 161 is also transferred using the anisotropic etching method. The etching stop layer 170, the inner metal dielectric layer 15 passes through the stop layer 140, and the inner metal dielectric is continued for a while. The layer wo is stopped on the substrate 100. Then, the photoresist layer 161 is removed. Because the self-aligned interconnect is etched at the time of the interconnect #etching, it is necessary to rely on the stop layer 140 as a photomask. Therefore, the dielectric layer 130 has a higher selection ratio than the stop layer 140. If the thickness of the stop layer ho is insufficient 'or the conditions of silver engraving are changed, a chamfering situation is likely to occur. In severe cases, the connection pattern disappears. At this point, you can see 50 parts in the picture, the shoulder of the inner line (Via

Shoulder) has a pronounced Corner Faceted. Finally, as shown in the first E diagram, a barrier layer 180 is deposited and then a metal layer 190 is filled into the via window and the trench line, wherein the material of the metal layer 19 is tungsten or copper or aluminum. Subsequently, a chemical mechanical polishing method is used to remove the excessive metal layer 190 to form a dual damascene structure.

5-3 Purpose and Summary of the Invention: In the background of the above invention, there are many shortcomings caused by the traditional process.

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Larger points can be obtained, and the present invention provides a method for forming a dual-mosaic lithography and rhyme process space. In the present invention, a layer is filled in the outline of the interconnect to increase the interlayer etch / deer ratio of the etching stop layer and the interconnect. In this way, when the trench pattern is etched, the outline is completed and the integrity is maintained. X. An object of the present invention is to provide a manufacturing process combining the capacitance of a logic moving element, so as to accurately control the shape and position of the metal interconnect. Since the present invention controls the position and shape of the J-line in the metal by etching the oxide layer, the shape and position can be controlled more accurately than the traditional method of obtaining the metal inner-line by etching the aluminum metal layer. And because this series uses copper metal as the material of the metal interconnects, and the resistivity of copper is also the resistivity of the aluminum metal traditionally used as metal interconnects, the resistance value of the circuit can be reduced to speed up the logic circuit. Reaction rate. -^ In the embodiment of the present invention, a method for forming a metal interconnect structure without chamfering includes at least the following steps: First, a semiconductor substrate is provided, and the semiconductor substrate has a first silicon nitride layer. And a first dielectric metal layer is formed on the silicon nitride layer. Next, two first photoresist layers are formed on the first intermetallic layer, and the first photoresist layer has a metal interconnect pattern. Therefore, the first dielectric metal layer is etched to form an opening in the first dielectric metal layer 'by using the first photoresist layer as an etching mask. Again, forming — ^

5. Description of the invention (6) --- Panyu silicon layer is on the surface of the first intermetallic layer. Next, a dielectric fill is formed: G and the second silicon nitride layer Λ. The filled dielectric layer has a layer-to-layer characteristic, and the dielectric layer is the first layer of the nitrided nitride until the second nitrided layer is exposed. The second dielectric layer is engraved on the surface of the dielectric layer-the third nitride layer-the first layer of silicon and the dielectric layer, layer 0 until the surface of the dielectric layer is exposed. Then i Erqian 第 Γ followed, and the third gasification fragment was engraved to the ΐ inner layer. Shape again! The interconnect layer formed by the electrical layer and the second dielectric layer; :: = layer and second intermetallic layer = metal surface 'to expose the second intermetallic layer U. Finally, the method of forming a metal interconnect structure is performed. In order to make ν, A, and the present invention more obvious, the following features are described in detail below. With the preferred embodiment and the accompanying drawings,

434U3 V. Description of the invention (7) '------' 5 ~ 4 Detailed description of the invention: The following is a description of the invention. The description of the present invention will first be assigned = structure as a reference ... some changes and the advantages of the present invention will be in it; the better way to make it will be discussed later. Hug back. Furthermore, although the invention is taught in terms of several embodiments, it does not limit the scope or application of the invention. And, although these examples describe thin dielectric layers, it should be clear that the main part may be replaced by the relevant =. Therefore, the semiconductor element of the present invention is not limited to the description of the structure. These elements include proof of the utility of the present invention and the preferred embodiments presented. This is useful. And even though the present invention is described by way of example and a comparative example, the present invention is not limited to the listed implementation. = All other equivalent changes or modifications made without departing from the spirit disclosed in the present invention are included in the scope of patent application of the present invention. The scope of the present invention should be interpreted in terms of the most productive definitions, so as to encompass all of these similar structures. 'Λ As in the second A picture,' First ', a semiconductor substrate 11 is provided, the semiconductor substrate 110 has a first silicon nitride layer (first stop layer), and the first silicon nitride layer 111 has a First dielectric metal layer. The thickness of this first silicon nitride layer jn is about 400 angstroms to 600 angstroms, and the temperature controlled during the formation is about 400 ° c to 80 ° C, and the pressure is about a few. · R to 100 m τ 〇rr e,

Page 10 23 4348 V. Description of the invention (8) As shown in the second diagram B, and then formed by coating with a photoresist liquid-a first photoresist layer 60 is formed on the first dielectric metal layer, and the first photoresist layer 60 has a The metal interconnect pattern 'has a thickness between about 5 000 and 15,000 Angstroms. As shown in the second figure C, the first dielectric metal layer 112 is etched by a conventional plasma dry etching method to form an opening 550 in the first dielectric metal layer. The first photoresist layer 60 is used as an etching mask. . And the etching is stopped on the first stop layer. As shown in the second D diagram, a second nitrogen layer (first stop layer) 113 is formed on the surface of the first intermetallic layer 112 by the chemical vapor deposition method. The thickness of this silicon layer 1U is about 400 angstroms to 600 angstroms. The thickness of the silicon layer 1U is controlled between 400 ° C and 800 ° C, and the pressure is between several Torr and 100Torr. The layer 114 is formed by a spin-on-glass method (S0G) as shown in FIG. 1 to FIG. 5 to form a dielectric opening between 26 and 28, and the opening 55 of the line. The dielectric layer has a dielectric constant w in the range of 2. b to 2.8, and the dielectric waste rectification layer-λ to ⑻⑽Etch BacI) is about 4000 and 5 000 angstroms. Following the 1M to k) method, the dielectric layer on the second stop layer 113 is removed from the dielectric layer 14 as shown in the second E2 diagram. As shown in the second F diagram, a second dielectric layer 114 is formed on the surface of the second nitride layer 114 followed by the metal layer 115 to form a silicon layer (second stop) on the surface and a dielectric layer.

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As shown in the second figure G, a photoresist coating is applied to form a second photoresist layer η on the surface of the second dielectric layer 115. The second photoresist layer 61 has a trench opening pattern and a thickness of about 5000 and 15000 Angstroms. As shown in the second figure, the second dielectric metal layer 115 is etched by a conventional plasma dry etching method, and the second photoresist layer 6 is used as an etching mask. Etching is stopped on the second stop layer 113. As shown in Figure I, a third silicon nitride layer 117 is formed on the surfaces of the second dielectric metal layer 115, the second silicon nitride layer 113, and the dielectric layer 114 by chemical vapor deposition. The thickness of the fourth silicon nitride layer I)? Is about 400 angstroms to angstroms, and the temperature controlled during the formation is about 400 to 800 angstroms. 〇, the waste power is between several Torr to 100mTorr. As shown in the first figure J, the third stop layer 117, that is, the third silicon nitride layer, is returned by the conventional plasma dry money engraving method until the surface of the dielectric layer 114 is exposed. For example, as shown in the first K picture, a conventional wet button engraving method, such as Diluted HF, is used to remove the dielectric layer 114 in the opening. The wet etching method is used here because the thickness of the metal interconnect (IMD Via) is about 5,000 to 100,000 angstroms. If dry etching is used, even if the dielectric layer in the interconnect is etched quickly, chamfering will occur. Therefore, both the trench and the interconnecting line contour of the present invention are protected by the stop layer '. Therefore, it is possible to remove the dielectric layer 114 in the inner wiring of the wet etching by wet etching. The traditional method cannot use wet etching. As in the second example, the third stop layer (the third silicon nitride layer), the second stop layer (the second silicon nitride layer) 113, and the first stop layer (the first nitride layer) 111 are etched. Until the second dielectric layer 115, the first dielectric layer 112 and the substrate 1 1 0 are exposed as shown in the second M diagram, again, a 0-p resistive early layer 210 such as nitrogen is formed by sputtering or chemical vapor deposition. In the case of Ni, Ni or Ni in the interconnect trench formed by the first dielectric metal layer η? And the second dielectric metal layer 115, the thickness of the tantalum nitride is between about 200 and 500 angstroms. Then, the interconnecting trenches formed by filling the first intermetallic layer 112 and the second intermetallic layer 115 with physical or chemical vapor deposition are filled with a metal 211 such as a steel alloy or an aluminum-copper alloy. Full completion. For example, in the second N figure, the surface of the metal 211 is planarized by a conventional chemical mechanical polishing method (CMP) to expose the surface of the second intermetallic layer 115, and a double damascene method is used to form a metal interconnect structure. Gully 2 is used to improve the stop layer and the interconnect. The dielectric profile of the line profile is relatively small. Ϊ The best double mosaic structure. In addition, in the rest of the ditch, it is not far from the 隹 to produce, far: stop layer. Therefore, the thickness of the photoresist film can be reduced 'to increase…, and the ice degree can reach a better lithography process space. In addition, this embodiment can provide

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Five 'invention description (11) ί: ί The process of combining the logic circuit and the capacitor of the passive component, so as to be precise: 1. The shape and position of the internal wiring. Since the present invention uses an etching method to control the position and shape of the metal interconnects, it is more accurate to control the shape and position of the metal interconnects than the traditional way of obtaining the metal interconnects by decorating: the LJ layer. And because the present invention uses copper metal as the metal interconnect L and copper has a resistivity smaller than that of traditional gold: = system, the resistance value of the circuit can be reduced to achieve a 2 reaction rate. Based on the above-mentioned reasons, the present invention is a method for forming a gold structure without chamfering, which includes at least the following steps: 1. The interconnector first provides a semiconductorized sand layer, and the first photoresistor pattern metal layer. Inside it is a layer of iron! Following this dielectric surface, it is a layer that is second layer at. Then, it is etched back to form a second intermetallic substrate, a first intermetallic layer, a metal interlayer, and a metal barrier layer on the semiconductor substrate. The first photoresist layer and the nitride layer are at the first. Therefore, the layer is opened on the first full opening, and the surface of the layer is formed by a second light by a second gold on the silicon layer and a first light by a gold. The resist layer has a photoresist layer and a metal layer to form a trench. The 篦 -metal layer is engraved on the surface. The dielectric metal layer is on the second optical clear mask. Silicon nitride forms a mask. Again. Connect the next layer until the second nitrogen barrier layer is in the pattern. Therefore, the layer and the intermediary have one after another, have an opening next to the shape, and expose the siliconized silicon layer, the second intermediary etch, the first nitrogen layer that forms an electrical layer, the first nitrogen layer, the first intermediary layer, and the first intermediary layer— Λ: — — metal layer on lice surface — 34S2s on intermetallic surface

5. Description of the invention (12). The second silicon nitride layer is etched back until the dielectric layer in the opening is exposed. Then, the nitrided nitride layer and the first nitrided nitride layer, the straight metal layer and the substrate are etched. Once again, the interconnect formed by forming the second dielectric metal layer and the first dielectric metal layer and the second dielectric metal layer are taken out to 'planarize' the metal surface, so as to expose the double damascene method to form metal interconnecting the dielectric layer. surface. Next, the third silicon nitride layer is etched, and the second f is etched to expose the second dielectric metal layer and the first barrier layer in the first dielectric metal layer and the trench. Then, fill it with metal: the formation of the inner 'connection trenches. The surface of the second dielectric metal layer is routed to the line structure. The above is only the preferred scope of the present invention and the scope of the patent application for the present invention; all equivalent changes or modifications within the spirit of the invention are within the scope of the patent. The examples are not intended to limit it without departing from the disclosure of the present invention, and they should be included in the following application methods. Briefly, the first A to the first E diagrams are sectional views of conventional techniques; The second to N figures are cross-sectional views of the embodiments of the present invention;

50 chamfered 60 photoresist layer 61 photoresist layer 100 substrate no semiconductor substrate 111 silicon nitride layer 112 dielectric metal layer 113 silicon nitride layer 114 dielectric layer 115 dielectric metal layer 116 silicon nitride layer 117 silicon nitride layer . 120 stop layer 130 inter-metal dielectric layer 140 stop layer 150 metal dielectric layer 160 photoresist layer 161 photoresist layer page 16

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Claims (1)

434823 VI. Application for patent Fan Yuan 1. A method for forming a metal interconnect structure without chamfering, at least comprising: providing a semiconductor substrate, the semiconductor substrate having a first stop layer on the first stop layer There is a first intermetallic layer; the first intermetallic layer is etched to form an opening in the first intermetallic, and a first photoresist layer is used as an etched photomask; a second stop layer is formed on the first On the surface of the dielectric metal layer; forming a dielectric layer to fill the opening and the surface of the second stop layer; etch back the dielectric layer until the second stop layer is exposed; forming a second dielectric metal layer on the first The second stop layer and the surface of the dielectric layer; the second dielectric metal layer is engraved to form a third stop layer on the second metal layer by a second photoresist layer as a silver engraved mask; On the surface of the second stop layer and the dielectric layer; etch back the third stop layer until the surface of the dielectric layer is exposed; remove the dielectric layer in the opening; etch the third stop layer, the second A stop layer and the first stop layer until the second dielectric metal is exposed Layer, the first dielectric metal layer and the surface of the semiconductor substrate; forming a barrier layer in an interconnecting trench formed by the first dielectric metal layer and the second dielectric metal layer; filling with a metal Shaped by the first intermetallic layer and the second intermetallic layer Page 18 434823 VI. The scope of the patent application for the interconnecting trenches; flatten the metal surface to expose the surface of the second intermetallic layer, and use the dual damascene method to form a metallic interconnecting structure. 2. The method according to item 1 of the scope of patent application, wherein one of the first photoresist layers has a thickness between about 5000 and 15,000 angstroms. _ 3. The method as described in item 1 of the scope of patent application, wherein one of the second photoresist layers has a thickness between about 5000 and 15,000 angstroms. 4. The method according to item 1 of the patent application scope, wherein the first stop layer includes at least silicon nitride. 5. The method according to item 1 of the scope of patent application, wherein the first stop layer includes at least a carbonized dream. 6. The method according to item 1 of the scope of patent application, wherein the dielectric layer has a dielectric constant between 2.6 and 2.8, and a thickness of the dielectric layer is between about 4 000 and 5000 angstroms. 7. The method according to item 1 of the scope of patent application, wherein the method for forming a dielectric layer includes at least a spin-on glass method. 8. The method according to item 1 of the scope of patent application, wherein the barrier layer to Page 19 434823 6. Scope of patent application Less tantalum nitride. 9. The method according to item 1 of the scope of patent application, wherein the above barrier layer contains at least titanium nitride. 10. The method according to item 1 of the patent application scope, wherein the metal layer comprises at least a copper alloy. 11. The method as described in item 1 of the patent application scope, wherein the metal layer comprises at least an aluminum alloy. 12. The method according to item 1 of the scope of patent application, wherein the method of planarizing the metal surface includes at least a chemical mechanical polishing method. 13. A method for forming a metal interconnect structure without chamfering, at least comprising: providing a semiconductor substrate having a first nitride layer on the semiconductor substrate, and a first layer on the first nitride layer Forming a first photoresist layer on the first dielectric metal layer; the first photoresist layer having a metal interconnect pattern; etching the first dielectric metal layer to form an opening in the dielectric metal layer Using the first photoresist layer as an etching mask; forming a second silicon nitride layer on the surface of the first intermetallic layer; Page 20 U82 3 ^ 434823 VI, please patent Fan Yuan. A dielectric layer is formed to fill the opening and the surface of the second silicon hydride layer is reflected on the surface to form a first person out of the second On the surface of the electrical layer; on the surface of the second silicon nitride layer; and the dielectric resist = one-first; the open resistance ::; on the surface and surface of the second dielectric metal layer, the second The second dielectric metal layer is engraved because the second photoresist layer is an etched mask silicon layer. The dielectric layer is a first dielectric metal, and the second nitride etches back the second silicon. '(Remove the opening: the flesh silicon layer until the surface of the dielectric layer is exposed; the first dielectric layer is etched; the stone layer until the exposed layer = the second nitrogen-cut layer and the first-gasification Forming the -resistance-intermediate metal, the first-intermediate metal layer and the substrate; the formed-inner layer formed in the first-intermediate metal layer, the second intermetallic layer, and the inner trench. The first-second metal 'Xiao this first [intermediate connecting line formed by the intermetallic layer; flattening · 2' this double setting = metal surface 'to expose the second intermetallic metal to form a metal Interconnect structure. The layer—the method described in item 13 of Shengfen's patent scope, wherein the first photoresist—has a thickness between about 5000 and 1500 angstroms. The surface of the layer 434821 6. Scope of patent application 15. The method described in item 13 of the scope of patent application, wherein one of the second photoresist layers has a thickness between about 5000 and 15,000 angstroms. 16. The method according to item 13 of the scope of patent application, wherein the dielectric layer has a dielectric constant between 2.6 and 2, 8 and a thickness of the dielectric layer is between 4000 and 5000 angstroms. . 17. The method according to item 13 of the scope of patent application, wherein the method for forming a dielectric layer includes at least a spin-on glass method. 18. The method according to item 13 of the scope of patent application, wherein the above barrier layer includes at least nitride. 19. The method as described in item 13 of the scope of patent application, wherein the barrier layer includes at least Lan Huaqin. 20. The method according to item 13 of the scope of patent application, wherein the barrier layer includes at least a group. 21. The method according to item 13 of the patent application scope, wherein the metal comprises at least a copper alloy. 22. The method according to item 13 of the scope of patent application, wherein the metal is at least Page 434821 Page 23