CN1467859A - 薄膜半导体器件及其制造方法和图像显示装置 - Google Patents
薄膜半导体器件及其制造方法和图像显示装置 Download PDFInfo
- Publication number
- CN1467859A CN1467859A CNA031199097A CN03119909A CN1467859A CN 1467859 A CN1467859 A CN 1467859A CN A031199097 A CNA031199097 A CN A031199097A CN 03119909 A CN03119909 A CN 03119909A CN 1467859 A CN1467859 A CN 1467859A
- Authority
- CN
- China
- Prior art keywords
- film
- thin
- semiconductor device
- island
- zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 100
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000010408 film Substances 0.000 claims abstract description 126
- 239000013078 crystal Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims description 69
- 238000002425 crystallisation Methods 0.000 claims description 24
- 230000008025 crystallization Effects 0.000 claims description 23
- 239000000203 mixture Substances 0.000 claims description 18
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 claims description 2
- 238000005354 coacervation Methods 0.000 claims description 2
- 238000005070 sampling Methods 0.000 claims description 2
- 238000007493 shaping process Methods 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 36
- 229910021417 amorphous silicon Inorganic materials 0.000 description 25
- 239000012528 membrane Substances 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 6
- 239000007787 solid Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011835 investigation Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 240000001439 Opuntia Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002050 diffraction method Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004050 hot filament vapor deposition Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
薄膜半导体器件是利用熔化的半导体的表面张力的凝结现象,在绝缘性基板的整个面上,或在特定的区域形成孤立的单晶薄膜的岛区域,在该岛区域中形成薄膜晶体管的有源区域。
Description
技术领域
本发明涉及形成在绝缘性基板上的由半导体薄膜构成的薄膜晶体管(以下称作TFT)等的薄膜半导体器件及其制造方法和图像显示装置。
背景技术
近年,伴随着电子化信息量的增加,积极地进行了用于处理、显示图像信息的装置的开发。伴随着图像显示装置和图像传感器的大型化、象素的高密度化(高精细化)的进展,要求能对应于更高速驱动的TFT。为了满足这些要求,能在大型玻璃基板等的低成本的绝缘性基板上以低成本形成高质量的由Si薄膜构成的TFT的技术的开发是不可或缺的。
以往,作为高质量的Si薄膜形成技术,有使非晶硅薄膜结晶的方法,其中基于激光的结晶化技术被广泛应用。例如,使用受激准分子激光而结晶的Si薄膜是平均粒径0.1~1.0μm左右的多晶Si薄膜,当形成MOS型TFT时,因为在TFT的沟道区域内一定存在结晶粒界,所以载流子的迁移率下降,性能恶化。另外,另一个问题是在熔化结晶时,液体Si和固体Si之间的体积膨胀率的不同引起粒界上产生表面凹凸,使TFT的耐压恶化。由于这些问题点,所以强烈要求Si结晶的大粒径化和表面平坦化的技术。
作为提高TFT性能的例子,在特开平11-121753号公报中描述了使晶体生长在特定的方向进行,源极、漏极的配置方向(等于电流方向)与该结晶粒的长度方向几乎一致的装置。另外,例如在特开平2000-243970号公报的实施例中描述的液晶显示装置中,TFT的源极、漏极的配置方向与该结晶粒的长度方向几乎一致,从阵列基板表面一侧观察,各TFT在显示阵列的周边部配置为纵横块状(水平方向和垂直方向)。可是,在任一TFT中,沟道区域都未单晶化,所以由于粒界上存在的陷阱能级的影响,性能和可靠性恶化,存在特性变化增加的问题。最近,基于比受激准分子激光的光束稳定性高很多的固体激光(YAG激光)的结晶化技术十分盛行。可是,在激光扫描方向形成了矩形单晶,但是它的平均宽度为0.5~1.5μm左右,无法消除TFT有源区域内的粒界。即在此前的众所周知的例子中,无论是哪个,TFT的有源区域中都存在多个粒界,并且存在各TFT有源区域的粒界数的变化引起TFT的特性变化的问题。
从所述以往技术的问题点可知,在使用激光退火法的绝缘性基板上的高质量多晶体膜的形成技术中,结晶粒径和面方位等是无序的,且各晶粒的位置控制等是困难的,所以难以形成高性能的TFT。因此,为了以低成本的制造方法实现高性能、高可靠性、低变化的TFT,有必要以比较简便的方法至少使绝缘性基板上的TFT的有源区域单晶化。
发明内容
本发明的目的在于:提供在形成TFT等的薄膜半导体器件的区域中,一定能使半导体薄膜成为单晶膜的结晶化技术,通过使用这些方法,提供能同时实现TFT的场效应迁移率等的性能的提高和它的均匀性的提高的薄膜半导体器件及其制造方法。
本发明者通过各种研讨和实验,考虑到通过使用与以往不同的物理现象,能解决所述问题点的TFT等薄膜半导体器件及其制造方法、使用了该薄膜半导体器件的图像显示装置。
第一发明的特征在于:(1)一种具有绝缘性基板和设置在该绝缘性基板上的孤立的单晶薄膜的岛区域的薄膜半导体器件。
(2)所述单晶薄膜的岛区域的与基板垂直的截面上具有近圆形、近椭圆形或它们的一部分构成的截面。
(3)另外,所述单晶薄膜的岛区域是带状的,在该单晶薄膜的岛区域中能形成薄膜晶体管的有源区域。
(4)所述薄膜晶体管的源、漏方向能配置为与所述带状单晶薄膜的长度方向近平行或近垂直。须指出的是,作为所述薄膜晶体管的例子,有场效应晶体管。
(5)在所述薄膜晶体管的有源区域中,能至少包含一个以上的所述带状单晶薄膜。
(6)在所述带状单晶薄膜中能至少形成一个以上所述薄膜晶体管的有源区域。
(7)设置在所述绝缘性基板上的单晶薄膜的岛区域的与该基板垂直的方向的主结晶方位是<110>、<100>或<111>,而相对于该基板是水平方向且该单晶薄膜岛区域的长度方向的结晶方位是<110>、<100>或<111>。
第二发明的特征在于:(8)一种薄膜半导体器件的制造方法,具有:在绝缘性基板上形成半导体薄膜,进行该半导体薄膜的构图的第一步骤;对表面张力不同的多种材料进行构图,配置在该半导体薄膜的上部或下部的第二步骤;通过激光的扫描,使该半导体薄膜熔化,利用基于该表面张力的凝聚现象,进行位置控制,使其与进行构图的位置匹配,在所述绝缘性基板上形成孤立的单晶薄膜的岛区域的第三步骤;在该孤立的单晶薄膜的岛区域中形成薄膜晶体管的有源区域的第四步骤。
第三发明的特征在于:(9)一种图像显示装置,包含图像显示部和周边区域,至少配置在该图像显示部的周边区域上的具有绝缘性基板和设置在该绝缘性基板上的孤立的单晶薄膜的岛区域的薄膜半导体器件包含:至少一个用于驱动所述图像显示装置的电路,该电路是从缓冲电路、采样开关电路、预充电电路、移位寄存器电路、解码电路、时钟波形整形电路、数字模拟转换电路、电源变换电路、电平移动电路、定时控制电路、放大电路、存储器、处理器、门阵列、通讯电路中选择的。
附图说明
下面简要说明附图。
图1A、1B是本发明的代表图,是表示形成在绝缘性基板上的单晶半导体薄膜和形成在其上的TFT的形态的图。
图2A、2B、2C、2D是在绝缘性基板上形成单晶半导体薄膜的步骤图。
图3A、3B是表示形成在绝缘性基板上的单晶Si薄膜的形状和结晶性的图。
图4A、4B、4C、4D、4E、4F、4G是在绝缘性基板上形成单晶半导体薄膜的步骤图。
图5A、5B、5C、5D、5E是在绝缘性基板上形成单晶半导体薄膜的步骤图。
图6A、6B、6C、6D是形成在绝缘性基板上的单晶半导体薄膜的剖视图。
图7A、7B是表示形成在绝缘性基板上的单晶Si薄膜的结晶面方位的图。
图8A、8B、8C、8D、8E是表示使用了形成在绝缘性基板上的单晶半导体薄膜的薄膜半导体器件的图。
图9A、9B是表示使用了薄膜半导体器件的图像显示装置的结构的平面模式图。
图10A、10B、10C、10D是表示应用了本发明的图像显示装置的电子设备的图。
具体实施方式
下面,根据附图详细地就本发明加以描述。另外,为了简单,以下以Si为例,但是对于所有的IV族(C、Si、Ge、Sn、Pb中的任意一种或它们的混合晶体)的薄膜,也取得了同样的发明效果。
(实施例1)
下面,参照图2、图3来说明绝缘性基板上形成的半导体薄膜的结晶化步骤和结晶化后的单晶Si薄膜的形状。
图2A是本实施例的剖视图,在绝缘性基板201上通过CVD(化学汽相淀积)法,淀积例如膜厚约100nm左右的由氧化硅膜构成的底层膜202、膜厚约50nm~200nm左右的非晶硅薄膜203。这时,非晶硅薄膜和底层的氧化硅膜的膜厚并不局限于本实施例。另外,底层膜202的结构可以是氮化硅膜或氧化硅膜和氮化硅膜的层叠膜等。然后,如图2B和2C所示,通过激光扫描进行非晶硅膜203的结晶化,形成了单晶Si薄膜204。图2D表示了单晶Si薄膜204的与激光扫描垂直的面中的剖面形状。这时,通过激光照射,非晶硅膜203熔化,由于表面张力导致的凝结,形成了各结晶膜的剖面构造由椭圆形的一部分构成的多个带状单晶膜。在本实施例中,激光扫描是使用固体激光在一定方向扫描,但是并未特别限制激光的种类。另外,也可以通过波长不同的激光的组合,例如首先用受激准分子激光使Si薄膜203多晶化,然后通过进行基于固体激光的扫描,能形成单晶薄膜。
图3A、3B是表示通过本结晶化方法形成的单晶Si薄膜的特征图,图3A表示了扫描电子显微镜(SEM)的像,图3B表示了透射电子显微镜(TEM)的明视野像(左)和暗视野像(右)。如图3A所示,可知在绝缘性基板上形成了在与激光扫描方向相同的方向延伸的带状的单晶Si薄膜204。如图3A的小图所示,这些带状单晶Si膜的特征在于:与长度方向垂直的面中的截面构造是椭圆形。这是因为通过激光扫描而熔化的Si由于表面张力而凝结,由于再通过激光的扫描,在横向生长结晶,就生长了具有圆的截面形状的带状单晶Si膜。另外,根据图3B所示的TEM的明视野像(左),在结晶膜的内部,未发现以往的多晶Si薄膜中观察到的粒界,并且根据暗视野像(右),可知是在结晶膜中不包含粒界或缺陷等的单晶膜。即本实施例中形成的薄膜的特征在于:是形成在基板上的带状的单晶Si膜,并且与结晶膜的长度方向垂直的面中的截面构造具有圆形或椭圆形的一部分的形状。
(实施例2)
在实施例2中,说明了在所述实施例1中说明的基于激光扫描的结晶化步骤中,在绝缘性基板上的特定的地方形成单晶Si薄膜的实施例,即为了单晶Si薄膜的位置控制而在对结晶化前的初始薄膜进行构图的实施例,和一边利用对熔化Si的浸湿性不同的底层膜进行位置控制,一边形成单晶Si薄膜的实施例。
图4A~图4G是说明把非晶硅薄膜203形成各种形状后,通过激光照射形成单晶薄膜的实施例的图。首先,如图4A所示,在绝缘性基板201之上形成底层膜202、非晶硅膜203,如图4(B)所示,通过抗蚀剂的涂敷、光掩模的曝光、显影、蚀刻工艺,以10μm的间隔,在所述绝缘性基板的整个面上周期地形成了宽度约5μm左右的非晶硅膜203的带状区域后,通过激光扫描使该非晶硅膜203结晶。如果使用本方法,就能在基板的整个面上周期地形成具有相同宽度和长度的单晶Si膜。
作为激光扫描前的非晶硅膜203的构图的另外的实施例,如图4C所示,在单晶化的区域的两侧,通过非晶硅膜的局部除去,挖掘矩形的孔,或如图4D所示,使TFT的源漏间区域的矩形非晶硅膜的膜厚比沟道区域的膜厚还厚,再在该TFT的沟道区域两侧挖掘矩形的孔,或如图4E所示,进行具有TFT的源漏间区域的宽度比沟道区域宽的形状的构图,或如图4F、4G所示,进行圆形或正方形等形状的构图后,通过进行结晶化,就能控制单晶膜和岛区域的位置。须指出的是,所述4A~4G所示图案的宽度、间隔、长度等还能进行种种变更。另外,进行构图的区域可以是所述绝缘性基板的整个区域,或者可以只对形成高性能的TFT的特定地方进行构图。
图5A~5E是说明通过把对熔化的Si的浸湿性不同的膜作为Si膜的底层膜利用,进行单晶膜的岛区域的位置控制的别的实施例的图。如图5A所示,把浸湿性不同的两种膜207、208配置在非晶硅薄膜203之下后,通过进行激光扫描,如图5B所示,在对Si的浸湿性大的膜207上凝结了熔化的Si,单结晶化,就能控制单晶Si膜的岛区域204的位置。在本实施例中,在非晶硅薄膜203之下形成了浸湿性不同的膜,但是作为别的方法,也可以在非晶硅膜之下形成浸湿性强的膜207,在要形成图案的非晶硅膜的岛区域203的侧面形成浸湿性弱的膜208。另外,也可以在非晶硅薄膜203之上配置浸湿性不同的膜。另外,如图5C所示,在基板整个面上形成浸湿性强的膜207,在其上配置浸湿性弱的膜208的岛图案,在其上全面形成非晶硅膜203。然后,通过进行基于激光扫描的结晶化,如图5D所示,在浸湿性弱的图案208之间能形成单晶膜岛区域204。在该单晶膜的岛区域204上可以形成薄膜半导体器件,如图5E所示,也可以去掉膜208后,形成薄膜半导体器件。
图6A~图6D是表示绝缘性基板上形成的单晶Si薄膜岛区域的截面形状的特征的图。本实施例中形成的单晶薄膜岛区域的截面形状如图6A所示,能由结晶截面的宽度(W)、膜厚(H)、曲率半径(R)、与基板的接触角度(θ)定义。这些参数由绝缘性基板上的薄膜半导体的膜厚、构图方法、Si薄膜和底层膜的浸湿性、Si薄膜的表面张力、激光的种类和扫描方法决定。如果表示一个例子,则使用单晶Si膜的膜厚为50nm的样品,通过激光扫描进行单晶化,得到W约1.0μm左右,H约100nm左右,θ约30°左右,长度约100μm左右的带状单晶薄膜。须指出的是,本实施例不局限于这些值,通过改变非晶硅的膜厚、激光照射的能量等,能取得更大面积的单晶薄膜的岛区域。另外,通过在浸湿性不同的膜的材料、构图的形状等上下功夫,如图6B~6D所示,能在绝缘性基板上形成具有各种截面形状的单晶膜的岛区域。
图7A、7B是说明本实施例中形成的带状单晶Si薄膜中,基于电子射线衍射法的分析的结果、取得的结晶面方位的图7A(上方)、总结对各结晶面的垂直方向的结晶方位的图7B。当基于电子射线衍射法的结晶面方位的决定时,电子束的入射方向是对于基板垂直的方向。另外,为了取得最佳的结晶方位,有必要使样品对于电子束的入射方向倾斜±5°以内,但是该角度内的倾斜对结晶面方位的决定不产生影响。在实际的分析结果中,与基板垂直的方向(V-方向)的结晶面方位中,所有测定点的90%以上是<110>,此外<100>和<111>随机存在。即与本实施例中形成的单晶薄膜的基板垂直的方向中的主定向表示为<110>。另外,用电子射线衍射法调查带状单晶薄膜的截面的面方位的结果是激光扫描方向即带状的长度方向(L-方向)的面方位是<110>为主定向。在图7B中,相对于V-方向的结晶方位来表示L-方向的结晶方位(此处的L-方向表示激光的扫描方法)。例如,如果V-方向是<110>,与它垂直的L-方向是<100>,或<110>或<111>方向。
如上所述,通过使用基于激光扫描的对单晶化前的初始薄膜进行构图的方法,能在特定的地方形成单晶Si薄膜的岛区域,能更提高表面张力效果,能形成高质量的单晶Si薄膜。另外,在本实施例中,对非晶硅薄膜进行了构图,但是作为别的实施例,也可以用受激准分子激光对非晶硅薄膜进行多晶化,然后进行多晶Si薄膜的构图,然后使用固体激光器等,进行单晶化。另外,作为进行激光扫描前的初始Si薄膜,代替在绝缘性基板上形成非晶硅薄膜,可以例如被称作Cat-CVD(催化CVD)的利用了催化剂的低温CVD法、基板加热CVD法形成的多晶Si薄膜。再对用这些CVD法形成的多晶Si薄膜进行构图后,通过激光扫描进行单晶化。
(实施例3)
本实施例参照附图来说明在所述实施例1和2中说明的制造方法形成的单晶膜204中形成薄膜半导体器件的例子,即它的元件构造和制造方法。
图8A是绝缘性基板上形成的带状的单晶Si薄膜204,用虚线表示了长度方向为A,它的垂直方向为B。图8B是说明图8A所示的带状单晶Si薄膜上形成的MOS型TFT的截面构造的图,源漏间方向和长度方向(A方向)一致。左侧的图表示A部分的截面构造。在单晶Si膜204上形成栅绝缘膜,形成了单晶Si薄膜用接触孔302和303、电极304和305、栅电极306。另外,右侧表示了向栅极中心划的虚线C的部分的截面构造。其特征在于:在截面形状为椭圆形的单晶Si薄膜上形成了TFT的沟道区域。
图8C是表示在与所述图8A所示的带状单晶薄膜204的长度方向垂直的方向(B方向)上配置了源、漏极的TFT的截面构造的图。在本实施例中,因为配置为栅电极306在带状单晶Si薄膜204的长度方向(A方向)延伸,所以能使栅极宽度很宽,从而能提高TFT的电流驱动能力。
另外,图8D是使用多个所述带状单晶Si薄膜204,构成沟道的TFT的例子。在该TFT中,可以在各带状单晶Si薄膜上形成源漏间的接触孔,但是如图所示,可以把在与单晶Si薄膜204同一面中形成的Si膜或在单晶Si薄膜204的上下的别的层中形成的Si膜加工成矩形,在该矩形的Si膜320和321中设置接触孔302和303。通过这样,能抑制接触孔的开口时的过蚀刻导致的单晶Si薄膜204的底层膜的损伤。另外,这里表示了单栅极的情形,但是也能采用具有多个栅电极的TFT构造。另外,也可以通过在TFT的形成前,使用各向同性蚀刻法加工单晶膜204,改变圆形或椭圆形的截面形状,形成TFT。
图8E是说明在所述单晶Si膜204上形成了多个TFT310的实施例的图。在本实施例中,矩形单晶Si薄膜204的面积形成约5μm×20μm左右,使用最小加工尺寸约0.1μm左右的微细加工技术,形成了TFT。按照必要能对TFT的配置、源漏极的方向等做各种变更。这样,形成由单晶Si薄膜构成的多个TFT等的薄膜半导体器件,能实现集成电路。
作为其他实施例,通过激光扫描把形成例如图4D、图4E所示的形状的非晶硅的岛区域单晶化,在该单晶Si薄膜的岛区域中设置源漏极和栅极,能形成TFT。如上所述,在绝缘性基板上能用比较简单的方法实现由单晶Si薄膜构成的TFT。这些TFT是高性能的,具有可靠性,特性变化小,所以使用这些TFT,能在完全绝缘膜基板即石英基板上形成在以往的单晶Si基板上形成的大规模集成电路。在大面积并且廉价的玻璃基板上能形成内置了电路的图像显示装置。
须指出的是,本实施例是形成MOS型TFT的例子,但是,因为根据本发明而取得的膜是单晶Si薄膜,所以利用它的特长,除了MOS型TFT以外,当然能形成例如双极性晶体管等的其他构造的元件。
(实施例4)
下面,参照图9A、9B说明在图像显示装置中使用了由所述实施例1~3所示的单晶Si薄膜构成的薄膜半导体器件,例如MOS型TFT的实施例。本实施例是在同一基板上搭载了由液晶和有机EL构成的图像显示装置、用于驱动它的驱动电路、DAC电路、电源电路、逻辑电路、帧存储器等系统的面板上系统。这些电路是由实施了本发明的TFT构成,在同一玻璃基板上形成TFT,所以制造工艺温度为例如500℃以下。
如果说明TFT的制造工艺,则如下所述。首先,如图9A所示,在例如玻璃或塑料等廉价的大型绝缘性基板201上淀积非晶硅薄膜203,例如通过第一激光步骤即受激准分子激光扫描基板的整个面,形成了多晶Si薄膜。接着,按照必要对形成例如驱动电路、数字模拟转换电路、电源电路、逻辑电路、帧存储器等的显示象素阵列部周边的电路的区域401进行多晶Si薄膜的构图,通过第二激光步骤即例如固体激光,再度进行激光扫描,用本发明的方法在区域401中形成由单晶Si薄膜构成的TFT,构成了必要的电路。
所述的结晶化步骤是通过受激准分子激光使基板整个面结晶化,只使周边电路区域401再度通过激光扫描单晶化,但是也可以是别的方法。例如,淀积非晶硅薄膜后,通过全面激光扫描进行单晶化,不仅是周边电路区域,在显示象素阵列部也形成由周边电路区域构成的TFT,形成象素TFT和象素存储器等的象素内置电路。另外,为了尽力省略激光扫描步骤,在通过例如CVD法全面淀积了多晶Si薄膜后,只在形成周边电路区域的地方,有选择地通过激光扫描形成由单晶Si薄膜构成的TFT。
图9B是表示使用了由所述制造工艺形成的TFT的面板上系统的装置结构的平面模式图。在图像显示部410的周边设置由单晶Si薄膜构成的高性能TFT,构成帧存储器、图像信号驱动系统电路411、垂直扫描系统电路412、逻辑电路413、接口电路414、电源电路415、DAC电路416等的周边电路,通过布线417连接这些周边电路和象素电路,构成了面板上系统。根据本发明的实施,能得到高图像质量、低耗电、高可靠、薄型、质量轻的面板上的系统。
(实施例5)
本实施例是应用了所述实施例4中所示的面板上系统的电子仪器,图10表示了它的形态。例如能应用于薄型大屏幕TV、PC用的显示器、移动电话、便携式信息终端(PDA)等各种电子仪器,并且通过利用本发明的TFT,把以往由LSI的安装构成的周边电路内置在同一基板上,能合并高图像质量、低耗电、高可靠、薄型、质量轻的特长,能实现低成本化。
根据本发明,能在低温下,在绝缘性基板上形成由单晶Si薄膜构成的TFT等的薄膜半导体器件,能实现搭载了系统的图像显示装置(面板上系统)和完全绝缘性基板上的集成电路。
Claims (15)
1.一种薄膜半导体器件,具有:绝缘性基板和设置在该绝缘性基板上的孤立的单晶薄膜岛区域。
2.根据权利要求1所述的薄膜半导体器件,其中:所述单晶薄膜岛区域的与基板垂直的截面具有近圆形、近椭圆形或它们的一部分构成的截面。
3.根据权利要求1所述的薄膜半导体器件,其中:所述单晶薄膜岛区域是带状单晶薄膜,在该单晶薄膜岛区域中形成有薄膜晶体管的有源区域。
4.根据权利要求3所述的薄膜半导体器件,其中:所述薄膜晶体管的源、漏方向配置为与所述带状单晶薄膜的长度方向近平行或近垂直。
5.根据权利要求3所述的薄膜半导体器件,其中:在所述薄膜晶体管的有源区域中,至少包含一个以上的所述带状单晶薄膜。
6.根据权利要求3所述的薄膜半导体器件,其中:在所述带状单晶薄膜中至少形成有一个以上所述薄膜晶体管的有源区域。
7.根据权利要求1所述的薄膜半导体器件,其中:设置在所述绝缘性基板上的单晶薄膜岛区域的与该基板垂直的方向的主结晶方位是<110>、<100>或<111>,而相对于该基板是水平方向且该单晶薄膜岛区域的长度方向的结晶方位是<110>、<100>或<111>。
8.一种薄膜半导体器件的制造方法,具有:在绝缘性基板上形成半导体薄膜,进行该半导体薄膜的构图的第一步骤;对表面张力不同的多种材料进行构图,配置在该半导体薄膜的上部或下部的第二步骤;通过激光的扫描,使该半导体薄膜熔化,利用基于表面张力的凝聚现象,进行位置控制,使其与进行构图的位置匹配,在所述绝缘性基板上形成孤立的单晶薄膜岛区域的第三步骤;在该孤立的单晶薄膜岛区域中形成薄膜晶体管的有源区域的第四步骤。
9.根据权利要求8所述的薄膜半导体器件的制造方法,其中:所述单晶薄膜岛区域的与基板垂直的截面具有近圆形、近椭圆形或它们的一部分构成的截面。
10.根据权利要求8所述的薄膜半导体器件的制造方法,其中:所述单晶薄膜岛区域是带状单晶薄膜,在该单晶薄膜岛区域中形成有薄膜晶体管的有源区域。
11.根据权利要求10所述的薄膜半导体器件的制造方法,其中:所述薄膜晶体管的源、漏方向配置为与所述带状单晶薄膜的长度方向近平行或近垂直。
12.根据权利要求10所述的薄膜半导体器件的制造方法,其中:在所述薄膜晶体管的有源区域中,至少包含有一个以上的所述带状单晶薄膜。
13.根据权利要求10所述的薄膜半导体器件的制造方法,其中:在所述带状单晶薄膜中至少形成有一个以上所述薄膜晶体管的有源区域。
14.根据权利要求8所述的薄膜半导体器件的制造方法,其中:设置在所述绝缘性基板上的单晶薄膜岛区域的与该基板垂直的方向的主结晶方位是<110>、<100>或<111>,而相对于该基板是水平方向且该单晶薄膜岛区域的长度方向的结晶方位是<110>、<100>或<111>。
15.一种图像显示装置,包含图像显示部和周边区域,至少配置在该图像显示部的周边区域上的具有绝缘性基板和设置在该绝缘性基板上的孤立的单晶薄膜岛区域的薄膜半导体器件包含:至少一个用于驱动所述图像显示装置的电路,该电路是从缓冲电路、采样开关电路、预充电电路、移位寄存器电路、解码电路、时钟波形整形电路、数字模拟转换电路、电源变换电路、电平移动电路、定时控制电路、放大电路、存储器、处理器、门阵列、通讯电路中选择的。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002192852A JP4329312B2 (ja) | 2002-07-02 | 2002-07-02 | 薄膜半導体装置、その製造方法及び画像表示装置 |
JP192852/2002 | 2002-07-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1467859A true CN1467859A (zh) | 2004-01-14 |
CN100456497C CN100456497C (zh) | 2009-01-28 |
Family
ID=29996983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB031199097A Expired - Fee Related CN100456497C (zh) | 2002-07-02 | 2003-02-28 | 薄膜半导体器件 |
Country Status (5)
Country | Link |
---|---|
US (2) | US6847069B2 (zh) |
JP (1) | JP4329312B2 (zh) |
KR (1) | KR100998148B1 (zh) |
CN (1) | CN100456497C (zh) |
TW (1) | TWI266371B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1909188B (zh) * | 2004-08-23 | 2011-03-09 | 株式会社半导体能源研究所 | 半导体器件的制作方法 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7935958B2 (en) * | 2004-10-22 | 2011-05-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP2006128233A (ja) | 2004-10-27 | 2006-05-18 | Hitachi Ltd | 半導体材料および電界効果トランジスタとそれらの製造方法 |
KR100570219B1 (ko) * | 2004-12-23 | 2006-04-12 | 주식회사 하이닉스반도체 | 반도체 소자의 체인 게이트 라인 및 그 제조 방법 |
JP2006261188A (ja) * | 2005-03-15 | 2006-09-28 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
KR101127132B1 (ko) * | 2005-05-13 | 2012-03-21 | 삼성전자주식회사 | 실리콘 나노와이어 기판 및 그 제조방법, 그리고 이를이용한 박막 트랜지스터의 제조방법 |
US8022408B2 (en) * | 2005-05-13 | 2011-09-20 | Samsung Electronics Co., Ltd. | Crystalline nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same |
JP4850452B2 (ja) * | 2005-08-08 | 2012-01-11 | 株式会社 日立ディスプレイズ | 画像表示装置 |
US20090250791A1 (en) * | 2008-04-08 | 2009-10-08 | Themistokles Afentakis | Crystalline Semiconductor Stripes |
US20090250700A1 (en) * | 2008-04-08 | 2009-10-08 | Themistokles Afentakis | Crystalline Semiconductor Stripe Transistor |
JP5669439B2 (ja) * | 2010-05-21 | 2015-02-12 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
CN102280474B (zh) * | 2010-06-09 | 2014-02-19 | 尹海洲 | 一种igbt器件及其制造方法 |
GB201310854D0 (en) | 2013-06-18 | 2013-07-31 | Isis Innovation | Photoactive layer production process |
JP6857517B2 (ja) * | 2016-06-16 | 2021-04-14 | ディフテック レーザーズ インコーポレイテッド | 基板上に結晶アイランドを製造する方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3213338B2 (ja) * | 1991-05-15 | 2001-10-02 | 株式会社リコー | 薄膜半導体装置の製法 |
TW226478B (en) * | 1992-12-04 | 1994-07-11 | Semiconductor Energy Res Co Ltd | Semiconductor device and method for manufacturing the same |
JP3450376B2 (ja) * | 1993-06-12 | 2003-09-22 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JPH08316485A (ja) * | 1995-05-12 | 1996-11-29 | Fuji Xerox Co Ltd | 半導体結晶の形成方法及びこれを用いた半導体装置の製造方法 |
JP3550805B2 (ja) * | 1995-06-09 | 2004-08-04 | ソニー株式会社 | 薄膜半導体装置の製造方法 |
JPH10289876A (ja) * | 1997-04-16 | 1998-10-27 | Hitachi Ltd | レーザ結晶化方法及びそれを用いた半導体装置並びに応用機器 |
JPH11121753A (ja) | 1997-10-14 | 1999-04-30 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2000243970A (ja) | 1999-02-24 | 2000-09-08 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタとその製造方法及びそれを用いた液晶表示装置とその製造方法 |
US6271101B1 (en) * | 1998-07-29 | 2001-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Process for production of SOI substrate and process for production of semiconductor device |
TW517260B (en) * | 1999-05-15 | 2003-01-11 | Semiconductor Energy Lab | Semiconductor device and method for its fabrication |
JP2001345451A (ja) * | 2000-05-30 | 2001-12-14 | Hitachi Ltd | 薄膜半導体集積回路装置、それを用いた画像表示装置、及びその製造方法 |
US6580122B1 (en) * | 2001-03-20 | 2003-06-17 | Advanced Micro Devices, Inc. | Transistor device having an enhanced width dimension and a method of making same |
US6692999B2 (en) * | 2001-06-26 | 2004-02-17 | Fujitsu Limited | Polysilicon film forming method |
-
2002
- 2002-07-02 JP JP2002192852A patent/JP4329312B2/ja not_active Expired - Fee Related
-
2003
- 2003-02-25 TW TW092103932A patent/TWI266371B/zh not_active IP Right Cessation
- 2003-02-26 US US10/372,809 patent/US6847069B2/en not_active Expired - Fee Related
- 2003-02-27 KR KR1020030012276A patent/KR100998148B1/ko not_active IP Right Cessation
- 2003-02-28 CN CNB031199097A patent/CN100456497C/zh not_active Expired - Fee Related
-
2004
- 2004-12-07 US US11/004,858 patent/US7084020B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1909188B (zh) * | 2004-08-23 | 2011-03-09 | 株式会社半导体能源研究所 | 半导体器件的制作方法 |
Also Published As
Publication number | Publication date |
---|---|
US20040005747A1 (en) | 2004-01-08 |
JP2004039765A (ja) | 2004-02-05 |
US20050095822A1 (en) | 2005-05-05 |
TW200401366A (en) | 2004-01-16 |
KR20040004039A (ko) | 2004-01-13 |
CN100456497C (zh) | 2009-01-28 |
KR100998148B1 (ko) | 2010-12-02 |
JP4329312B2 (ja) | 2009-09-09 |
US7084020B2 (en) | 2006-08-01 |
TWI266371B (en) | 2006-11-11 |
US6847069B2 (en) | 2005-01-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100456497C (zh) | 薄膜半导体器件 | |
CN1309034C (zh) | 底栅控制型多晶硅薄膜晶体管的制造方法 | |
JP4358998B2 (ja) | 薄膜トランジスタ装置およびその製造方法 | |
CN1514469A (zh) | 结晶掩模、非晶硅结晶方法及利用其制造阵列基板的方法 | |
KR101243667B1 (ko) | 폴리실리콘 액정표시소자 및 그 제조방법 | |
CN1291452C (zh) | 多晶硅结晶方法、薄膜晶体管及其液晶显示器的制造方法 | |
CN101626034A (zh) | 薄膜晶体管及其制造方法 | |
CN101064256A (zh) | 低温直接沉积多晶硅薄膜晶体管及其制造方法 | |
CN1577022A (zh) | 液晶显示装置及其制造方法 | |
CN1536620A (zh) | 低温多晶硅薄膜晶体管及其多晶硅层的制造方法 | |
CN1815321A (zh) | 液晶显示装置用下基板的制造方法 | |
CN1710469A (zh) | 像素结构与其制造方法 | |
CN1300825C (zh) | 制造多晶硅层的方法 | |
CN1687838A (zh) | 有源阵列基板及其制造方法 | |
CN1324359C (zh) | 平面显示器及其制造方法 | |
CN100474627C (zh) | 具有轻掺杂漏区/偏移区(ldd/offset)结构的薄膜晶体管 | |
CN1581427A (zh) | 多晶硅薄膜的制造方法 | |
CN1497685A (zh) | 制造使用双重或多重栅极的薄膜晶体管的方法 | |
CN1645612A (zh) | 具复合多晶硅层的半导体结构及其应用的显示面板 | |
CN1581450A (zh) | 低温多晶硅薄膜晶体管的制造方法 | |
CN1187642C (zh) | 具有凸状结构的薄膜晶体管液晶显示器及其制造方法 | |
CN1991542A (zh) | 液晶显示装置及其制造方法 | |
CN1670622A (zh) | 激光退火的制程光罩以及利用激光退火形成多晶系膜层的方法 | |
KR20200009106A (ko) | 산화물 반도체 박막 트랜지스터 및 그 제조방법 | |
CN1725090A (zh) | 低温多晶硅薄膜晶体管全集成有源选址基板及制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090128 Termination date: 20130228 |