CN1444278A - 存储器系统和制造该存储器系统的方法 - Google Patents

存储器系统和制造该存储器系统的方法 Download PDF

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Publication number
CN1444278A
CN1444278A CN03119885A CN03119885A CN1444278A CN 1444278 A CN1444278 A CN 1444278A CN 03119885 A CN03119885 A CN 03119885A CN 03119885 A CN03119885 A CN 03119885A CN 1444278 A CN1444278 A CN 1444278A
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CN
China
Prior art keywords
memory
lines
custom
memory layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN03119885A
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English (en)
Chinese (zh)
Inventor
J·N·霍甘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of CN1444278A publication Critical patent/CN1444278A/zh
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
CN03119885A 2002-03-07 2003-03-07 存储器系统和制造该存储器系统的方法 Pending CN1444278A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/093020 2002-03-07
US10/093,020 US6594171B1 (en) 2002-03-07 2002-03-07 Memory systems and methods of making the same

Publications (1)

Publication Number Publication Date
CN1444278A true CN1444278A (zh) 2003-09-24

Family

ID=22236384

Family Applications (1)

Application Number Title Priority Date Filing Date
CN03119885A Pending CN1444278A (zh) 2002-03-07 2003-03-07 存储器系统和制造该存储器系统的方法

Country Status (6)

Country Link
US (1) US6594171B1 (enExample)
EP (1) EP1343169B1 (enExample)
JP (1) JP4303006B2 (enExample)
KR (1) KR100936148B1 (enExample)
CN (1) CN1444278A (enExample)
TW (1) TWI259557B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101164118B (zh) * 2005-03-31 2011-04-06 桑迪士克3D公司 集成电路及用于集成电路存储器阵列中的方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882553B2 (en) * 2002-08-08 2005-04-19 Micron Technology Inc. Stacked columnar resistive memory structure and its method of formation and operation
WO2004084228A1 (en) 2003-03-18 2004-09-30 Kabushiki Kaisha Toshiba Phase change memory device
US20050138012A1 (en) * 2003-12-23 2005-06-23 Royer Robert J.Jr. Meta-data storage and access techniques
KR100800486B1 (ko) 2006-11-24 2008-02-04 삼성전자주식회사 개선된 신호 전달 경로를 갖는 반도체 메모리 장치 및 그구동방법
US20080259676A1 (en) * 2007-04-17 2008-10-23 Bernhard Ruf Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Computer Program Product
KR100974174B1 (ko) * 2009-11-03 2010-08-05 주식회사 파이로 방탄복
TW202315050A (zh) * 2010-02-16 2023-04-01 凡 歐貝克 製造３ｄ半導體晶圓的方法
KR20110135298A (ko) * 2010-06-10 2011-12-16 삼성전자주식회사 반도체 메모리 장치
JP2022050059A (ja) 2020-09-17 2022-03-30 キオクシア株式会社 磁気記憶装置及びメモリシステム

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008729A (en) 1984-06-18 1991-04-16 Texas Instruments Incorporated Laser programming of semiconductor devices using diode make-link structure
AU4663293A (en) * 1992-07-07 1994-01-31 Rtb Technology, Inc. High density memory and method of forming the same
US5314840A (en) * 1992-12-18 1994-05-24 International Business Machines Corporation Method for forming an antifuse element with electrical or optical programming
FR2719967B1 (fr) 1994-05-10 1996-06-07 Thomson Csf Interconnexion en trois dimensions de boîtiers de composants électroniques utilisant des circuits imprimés.
US5807791A (en) * 1995-02-22 1998-09-15 International Business Machines Corporation Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes
US5914906A (en) * 1995-12-20 1999-06-22 International Business Machines Corporation Field programmable memory array
US5973396A (en) * 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
JPH1154693A (ja) 1997-07-29 1999-02-26 Sanyo Electric Co Ltd 半導体装置
KR100321169B1 (ko) 1998-06-30 2002-05-13 박종섭 앤티퓨즈의프로그래밍회로
JP2000091729A (ja) 1998-09-07 2000-03-31 Nec Eng Ltd スタックメモリモジュール
US6122187A (en) * 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101164118B (zh) * 2005-03-31 2011-04-06 桑迪士克3D公司 集成电路及用于集成电路存储器阵列中的方法

Also Published As

Publication number Publication date
TWI259557B (en) 2006-08-01
EP1343169A2 (en) 2003-09-10
KR100936148B1 (ko) 2010-01-12
US6594171B1 (en) 2003-07-15
JP4303006B2 (ja) 2009-07-29
EP1343169A3 (en) 2004-03-24
KR20030074205A (ko) 2003-09-19
TW200304206A (en) 2003-09-16
EP1343169B1 (en) 2012-04-11
JP2003331573A (ja) 2003-11-21

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Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SAMSUNG ELECTRONICS CO., LTD

Free format text: FORMER OWNER: HEWLETT-PACKARD DEVELOPMENT COMPANY

Effective date: 20070928

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20070928

Address after: Gyeonggi Do, South Korea

Applicant after: Samsung Electronics Co., Ltd.

Address before: California, USA

Applicant before: Hewlett-Packard Co.

C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20030924