CN1333441C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1333441C
CN1333441C CNB038118122A CN03811812A CN1333441C CN 1333441 C CN1333441 C CN 1333441C CN B038118122 A CNB038118122 A CN B038118122A CN 03811812 A CN03811812 A CN 03811812A CN 1333441 C CN1333441 C CN 1333441C
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CN
China
Prior art keywords
layer
nitrogen
gate electrode
silicide
nickel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB038118122A
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English (en)
Chinese (zh)
Other versions
CN1656605A (zh
Inventor
E·N·佩顿
P·R·贝瑟
S·S·常
F·N·豪思
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
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Publication of CN1656605A publication Critical patent/CN1656605A/zh
Application granted granted Critical
Publication of CN1333441C publication Critical patent/CN1333441C/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/50—Alloying conductive materials with semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
CNB038118122A 2002-05-31 2003-05-13 半导体器件及其制造方法 Expired - Lifetime CN1333441C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/157,807 US6873051B1 (en) 2002-05-31 2002-05-31 Nickel silicide with reduced interface roughness
US10/157,807 2002-05-31

Publications (2)

Publication Number Publication Date
CN1656605A CN1656605A (zh) 2005-08-17
CN1333441C true CN1333441C (zh) 2007-08-22

Family

ID=32228405

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038118122A Expired - Lifetime CN1333441C (zh) 2002-05-31 2003-05-13 半导体器件及其制造方法

Country Status (9)

Country Link
US (2) US6873051B1 (https=)
EP (1) EP1509947B1 (https=)
JP (1) JP4866549B2 (https=)
KR (1) KR101117320B1 (https=)
CN (1) CN1333441C (https=)
AU (1) AU2003299495A1 (https=)
DE (1) DE60304225T2 (https=)
TW (1) TWI289328B (https=)
WO (1) WO2004040622A2 (https=)

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US6440851B1 (en) * 1999-10-12 2002-08-27 International Business Machines Corporation Method and structure for controlling the interface roughness of cobalt disilicide
KR100870176B1 (ko) * 2003-06-27 2008-11-25 삼성전자주식회사 니켈 합금 샐리사이드 공정, 이를 사용하여 반도체소자를제조하는 방법, 그에 의해 형성된 니켈 합금 실리사이드막및 이를 사용하여 제조된 반도체소자
JP2005072264A (ja) * 2003-08-25 2005-03-17 Seiko Epson Corp トランジスタの製造方法、トランジスタ、回路基板、電気光学装置及び電子機器
US20050056881A1 (en) * 2003-09-15 2005-03-17 Yee-Chia Yeo Dummy pattern for silicide gate electrode
BE1015721A3 (nl) * 2003-10-17 2005-07-05 Imec Inter Uni Micro Electr Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting.
JP3879003B2 (ja) * 2004-02-26 2007-02-07 国立大学法人名古屋大学 シリサイド膜の作製方法
US7253125B1 (en) 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
US7132352B1 (en) * 2004-08-06 2006-11-07 Advanced Micro Devices, Inc. Method of eliminating source/drain junction spiking, and device produced thereby
JP2006060045A (ja) * 2004-08-20 2006-03-02 Toshiba Corp 半導体装置
US9659769B1 (en) * 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
JP2006261635A (ja) 2005-02-21 2006-09-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US8980769B1 (en) 2005-04-26 2015-03-17 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8454750B1 (en) 2005-04-26 2013-06-04 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8889233B1 (en) 2005-04-26 2014-11-18 Novellus Systems, Inc. Method for reducing stress in porous dielectric films
KR100679224B1 (ko) * 2005-11-04 2007-02-05 한국전자통신연구원 반도체 소자 및 그 제조방법
US7608515B2 (en) * 2006-02-14 2009-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion layer for stressed semiconductor devices
JP5042517B2 (ja) * 2006-04-10 2012-10-03 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4920310B2 (ja) * 2006-05-30 2012-04-18 株式会社東芝 半導体装置およびその製造方法
WO2008035490A1 (en) * 2006-09-20 2008-03-27 Nec Corporation Semiconductor device and method for manufacturing same
US10037905B2 (en) 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
US8465991B2 (en) * 2006-10-30 2013-06-18 Novellus Systems, Inc. Carbon containing low-k dielectric constant recovery using UV treatment
US20090004851A1 (en) * 2007-06-29 2009-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Salicidation process using electroless plating to deposit metal and introduce dopant impurities
US8211510B1 (en) 2007-08-31 2012-07-03 Novellus Systems, Inc. Cascaded cure approach to fabricate highly tensile silicon nitride films
DE102008035809B3 (de) * 2008-07-31 2010-03-25 Advanced Micro Devices, Inc., Sunnyvale Technik zum Verringern der Silizidungleichmäßigkeiten in Polysiliziumgateelektroden durch eine dazwischenliegende Diffusionsblockierschicht
US9050623B1 (en) 2008-09-12 2015-06-09 Novellus Systems, Inc. Progressive UV cure
US20110001169A1 (en) * 2009-07-01 2011-01-06 International Business Machines Corporation Forming uniform silicide on 3d structures
CN102593174B (zh) * 2011-01-18 2015-08-05 中国科学院微电子研究所 半导体器件及其制造方法
CN102593173B (zh) * 2011-01-18 2015-08-05 中国科学院微电子研究所 半导体器件及其制造方法
US9607842B1 (en) * 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
US9847221B1 (en) 2016-09-29 2017-12-19 Lam Research Corporation Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing
JP7583550B2 (ja) * 2020-08-13 2024-11-14 東京エレクトロン株式会社 半導体装置の電極部及びその製造方法
EP4199110A4 (en) 2021-01-14 2024-04-10 Changxin Memory Technologies, Inc. MANUFACTURING METHOD FOR ONE SEMICONDUCTOR STRUCTURE AND TWO SEMICONDUCTOR STRUCTURES
CN112864240B (zh) * 2021-01-14 2022-05-31 长鑫存储技术有限公司 半导体结构的制造方法及两种半导体结构

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US5545575A (en) * 1994-10-24 1996-08-13 Motorola, Inc. Method for manufacturing an insulated gate semiconductor device
US5950098A (en) * 1995-06-26 1999-09-07 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of a semiconductor device with a silicide layer

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JPS62183180A (ja) * 1986-02-07 1987-08-11 Hitachi Ltd 半導体集積回路装置の製造方法
US5170242A (en) * 1989-12-04 1992-12-08 Ramtron Corporation Reaction barrier for a multilayer structure in an integrated circuit
US5545574A (en) 1995-05-19 1996-08-13 Motorola, Inc. Process for forming a semiconductor device having a metal-semiconductor compound
US5648287A (en) * 1996-10-11 1997-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of salicidation for deep quarter micron LDD MOSFET devices
US6180469B1 (en) * 1998-11-06 2001-01-30 Advanced Micro Devices, Inc. Low resistance salicide technology with reduced silicon consumption
US5970370A (en) * 1998-12-08 1999-10-19 Advanced Micro Devices Manufacturing capping layer for the fabrication of cobalt salicide structures
JP2000307110A (ja) * 1999-04-23 2000-11-02 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
US6228730B1 (en) * 1999-04-28 2001-05-08 United Microelectronics Corp. Method of fabricating field effect transistor
US6281102B1 (en) * 2000-01-13 2001-08-28 Integrated Device Technology, Inc. Cobalt silicide structure for improving gate oxide integrity and method for fabricating same
US6465349B1 (en) * 2000-10-05 2002-10-15 Advanced Micro Devices, Ins. Nitrogen-plasma treatment for reduced nickel silicide bridging
US6483154B1 (en) * 2000-10-05 2002-11-19 Advanced Micro Devices, Inc. Nitrogen oxide plasma treatment for reduced nickel silicide bridging
US6602754B1 (en) * 2001-02-02 2003-08-05 Advanced Micro Devices, Inc. Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer
US6432805B1 (en) * 2001-02-15 2002-08-13 Advanced Micro Devices, Inc. Co-deposition of nitrogen and metal for metal silicide formation
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US6495460B1 (en) * 2001-07-11 2002-12-17 Advanced Micro Devices, Inc. Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface

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US5545575A (en) * 1994-10-24 1996-08-13 Motorola, Inc. Method for manufacturing an insulated gate semiconductor device
US5950098A (en) * 1995-06-26 1999-09-07 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of a semiconductor device with a silicide layer

Also Published As

Publication number Publication date
AU2003299495A1 (en) 2004-05-25
KR20050005524A (ko) 2005-01-13
EP1509947A2 (en) 2005-03-02
WO2004040622A2 (en) 2004-05-13
DE60304225T2 (de) 2006-12-14
US6967160B1 (en) 2005-11-22
EP1509947B1 (en) 2006-03-22
AU2003299495A8 (en) 2004-05-25
JP2005539402A (ja) 2005-12-22
TWI289328B (en) 2007-11-01
US6873051B1 (en) 2005-03-29
DE60304225D1 (de) 2006-05-11
KR101117320B1 (ko) 2012-03-22
WO2004040622A3 (en) 2004-07-22
TW200403731A (en) 2004-03-01
JP4866549B2 (ja) 2012-02-01
CN1656605A (zh) 2005-08-17

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Granted publication date: 20070822