CN1311519C - 晶圆/芯片上再分布层的保护方法 - Google Patents
晶圆/芯片上再分布层的保护方法 Download PDFInfo
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Abstract
本发明是关于一种保护晶圆/芯片上再分布层的方法，其较佳地包含一结构，其构成为一种子层，一铜层位于种子层上，一镍层配置其上，以及一金层覆盖后者。其目的是提供一种保护晶圆上之再分布层的方法，其处理不用额外的微影步骤且可实现成本效益。此藉由具有再分布层(1)之晶圆(4)以一有机保护层(12)例如由BTA(苯三唑)，Glicoat或Preventol制成，被覆盖其整个表面达成，其保护再分布层(1)免于侵蚀以及氧化，其中其经由化学键结制造一稠密的再分布层(1)之金属表面覆盖。
Description
技术领域
本发明是关于一种保护晶圆/芯片上再分布层的方法，其较佳地包含一种子层，一铜层位于该种子层上，一镍层配置于其上，以及一金层覆盖最后。
背景技术
此一再分布层之制造，其实现一电连接于有效构造以及一联合键结台之间在一晶圆或一3D结构上以一顺从组件的型式，是相关复杂且需要一复数的光微影处理步骤。因此，首先晶圆必须以光阻涂覆，随后必须被曝光且显影。此是随后以一金属层涂覆，在其之后，光阻是被剥除。这些处理步骤必须重复直到所需要层序列被达成。这些处理步骤是原则上以一下列大纲来表示。
因此，在目前实际上所使用的方法中，金层的必须图样化是藉由一习惯上的微影程序来实现。再分布层在此例中是被制造于其中，在一种子层之沉积以及Cu/Ni层配置其上之后，金层是被沉积在整个再分布层之上。实际的电导体在此例中是为Cu层而具有最低电阻。
此方法可以概要地表示如下：
a)沉积种子层
b)EPR1(环氧化物光阻1)：涂覆以及图样化(微影步骤1)
c)重新电镀，制造Cu/Ni层序列于种子层上
d)以Au涂覆重新进行的图形
e)EPR2(环氧化物光阻2)：涂覆以及图样化(微影步骤2)
f)(如所需)选择性蚀刻Au层(湿式蚀刻(CMP)，或者移除/剥除)。
在此例中，Ni层作为Cu层之一黏着层以及后者依次作为Au覆盖层之一黏着层。因为Au层本身不能氧化，其作为，一方面来说，一安全的焊接材料黏着层，为了作为连接一3D结构到一印刷电路板之连接台的例子，其是经常由Cu组成，且，另一方面来说，作为一Cu层之保护层位于其下。换句话说，Cu层是大大地保护Au层免于侵蚀，自上面在任何速度下。
一特别的缺点在此例中再分布层以此一结构构成是被看到再分布层之侧边缘是一点都不被保护免于侵蚀以及氧化。这表示侧面渗透侵蚀或前进的氧化的可能性可能最后局部地导致再分布层之破坏，因此，限制具有此一分布层之电子组件之服务寿命。
在朝向终点的IC制造期间，Cu金属化是被保护免于氧化在CMP(化学机械抛光)期间藉由BTA(苯三唑)，以及后来藉由一线型(TiN)以及一氧化物。
在印刷电路板(PCBs)之制造中，工业使用BTA或另外的有机层为了提供印刷电路板具有保护氧化优先于焊接。再者，传导图形在一印刷电路板上是相对的厚且宽，结果侵蚀问题在此例中是不特别明显。
然而，再分布层在晶圆或芯片上之例子中状况不同。在此例中，问题至今已经被解决藉由压缩再分布层经由直流电或电子涂覆。然而，此需要一额外的微影步骤，其增加程序复杂性以及成本。
另外的可能性对于保护Cu层包含使用焊接步骤以将Cu层封入藉由一UBM(在帮浦金属化之下)。在此例中，再分布层是完全地被压缩，虽然此是不适合于长传导图形且，再者，将导致一明显的成本增加。
发明内容
因此，本发明是基于提供一种用以保护再分布层于晶圆上的方法的目的，其处理不需额外的微影步骤且可被有效成本实现。
本发明以为基础的目的是被达成，在介绍中所述的类型之一方法的例子中，由于晶圆具有再分布层是被覆盖于其整个表面上以一有机保护层，其保护再分布层免于侵蚀以及氧化其中其制造一稠密的再分布层之金属表面覆盖经由化学键结。
具体而言，本发明提供一种用来保护晶圆上再分布层的方法，该晶圆上的再分布层包含一种子层，一铜层坐落于该种子层上，一镍层配置于其上，以及一金层覆盖于后者，其步骤包括：对该晶圆的再分布层进行蚀刻；于经蚀刻的再分布层上形成一有机保护层，其覆盖于整个再分布层的表面上，以保护经由化学键结制造的金属表面所覆盖的再分布层免于受侵蚀或氧化，其中该有机保护层是在温度为30度的条件下形成于经蚀刻的再分布层上。
藉由此方法，可以一特别简单的方式实现，再分布层之一有效保护以及，特别是，其Cu层是被达成而无任何额外的光微影步骤。
BTA(苯三唑)Glicoat(公司Shikoku Chemical Corp.注册商标)或者Preventol(Bayer Chemical之注册商标)是较佳地考虑为有机保护层。
在本发明延续中，保护层是藉由喷溅来提供，或者藉由晶圆/芯片浸入一液体储存槽。
在前者例子中，晶圆必须被预热到趋近30度，而再第二例子中液体储存槽的温度必须为趋近30度。
为了避免任何侵蚀与氧化开始，其是有利的如果晶圆在以有机保护层涂覆之前被直接蚀刻。
本发明之一再一改进提供晶圆之涂覆重新开始在后者已经被单一化且单一化的芯片已经被装置在一载体之上之后。
附图说明
本发明将被更详细地解释于下使用一实施粒。在随附的图标中：
图1显示一详细图标自一晶圆具有一顺从的组件在以一种子层涂覆之后；
图2显示根据图1的晶圆具有一EPR(电泳电阻)在一第一光微影以及一再分布层在一键结台以及顺从的组件之间；
图3显示根据图2之晶圆在部分移除Au层之后；
图4显示根据图3之晶圆在EPR之移除以及种子层之剥除之后；
图5显示以一有机物质例如BTA，Glicoat或者Preventol涂覆整个面积之晶圆；以及
图6显示晶圆在焊接操作之后。
具体实施方式
一再分布层1之制造自一键结台2到一3D结构3于一晶圆4上系图标且仅以基本步骤于图1至图4中说明。3D结构可能为一顺从组件用以制造一电子连接到一连接台于一载体组件上，如一印刷电路板。
为了实现再分布层，首先，一EPR1屏蔽5是被制造于晶圆上藉由一微影步骤，该屏蔽作为随后重新执行电镀的罩慕(制造再分布层)。为此目的，首先一种子层6被应用(图1)，其作为Cu层7之一黏着层，其是被提供至该种子层。对于此部份，Cu层7作为Ni层8之一黏着层，其是被应用于其上，该Ni层保护Cu层7免于侵蚀。最后，一Au层9被提供于Ni层(图第2)之上，且，对于此部份，作为一焊接材料之确保黏着层。
为了预防焊接材料从3D结构3耗损在一后来的焊接操作期间，必须对Au层9再次从再分布层1部分移除，Au层9必须被保存于3D结构3之上以可以实现一焊接连接。为此目的，从第3图中可见，一再一EPR2屏蔽10是被制造用以覆盖3D结构3之较上方区域藉由一另外的光微影以及Au层9是随后被剥除。
为了完成再分布层1，EPR1以及EPR2以及种子层是最后被剥除(图4)。
因此，其可被确定无困难性的是种子层7是自上被保护藉由Ni层8位于其上，但不在其终点面/侧边缘11。因此存在Cu层之侵蚀或氧化的风险，其最后导致电子特性之一损伤。
为了避免此情况，具有再分布层1之晶圆4是被一有机保护层12覆盖于其整个表面上(图5)，其保护再分布层免于侵蚀且氧化其中其制造伊稠密的再分布层金属表面经由化学键结。
BTA(苯三唑)Glicoat(公司Shikoku Chemical Corp.注册商标)或者Preventol)是较佳地考虑为有机保护层。
在本发明中，保护层是藉由喷溅来提供，或者藉由晶圆/芯片浸入一液体储存槽。
在前者例子中，晶圆必须被预热到趋近30度，而再第二例子中液体储存槽的温度必须为趋近30度。
为了避免任何侵蚀或氧化开始，晶圆4应该在以有机保护层涂覆之前一开始轻微地被直接蚀刻。
图6显示一详细图标自具有一有机保护层之晶圆4在一焊接操作之后。有机保护层12出现在3D结构之上蒸发在焊接操作期间。因此焊接材料13直接黏着在Au层9之上。
基于焊接操作以及加热再分布层1期间，有机保护层12可能亦蒸发在焊接连接14附近，因此再分布层1之终点面/侧边缘11是在此区中不被保护。
此处为了确认一可靠的保护，可能已有机材料重复对晶圆4或者芯片之涂覆。
参考符号列表
1 再分布层
2 键结台
3 3D结构
4 晶圆
5 EPR1屏蔽
6 种子层
7 Cu层
8 Ni层
9 Au层
10 EPR2屏蔽
11 终止面/侧边缘
12 有机保护层
13 焊接材料
14 焊接连接
Claims (7)
1.一种用来保护晶圆上再分布层的方法，该晶圆上的再分布层包含一种子层，一铜层坐落于该种子层上，一镍层配置于其上，以及一金层覆盖于后者，其步骤包括：
对该晶圆(4)的再分布层(1)进行蚀刻；
于经蚀刻的再分布层(1)上形成一有机保护层(12)，其覆盖于整个再分布层(1)的表面上，以保护经由化学键结制造的金属表面所覆盖的再分布层(1)免于受侵蚀或氧化，其中
该有机保护层(12)是在温度为30度的条件下形成于经蚀刻的再分布层(1)上。
2.根据权利要求1所述的方法，其中所述有机保护层(12)为苯三唑。
3.根据权利要求1所述的方法，其中所述有机保护层(12)为Glicoat。
4.根据权利要求1所述的方法，其中所述有机保护层(12)为Preventol。
5.根据权利要求1至4其中一项所述的方法，其中所述有机保护层(12)是通过喷溅来提供。
6.根据权利要求1至4其中一项所述的方法，其中所述有机保护层(12)是通过浸泡晶圆(4)到一液体储藏槽来提供。
7.根据权利要求1所述的方法，其中在一焊接操作之后，重复地在该晶圆上涂覆该有机保护层。
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| DE10318078A DE10318078B4 (de) | 2003-04-17 | 2003-04-17 | Verfahren zum Schutz einer Umverdrahtung auf Wafern/Chips |
| DE10318078.8 | 2003-04-17 |
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| DE10320561B4 (de) * | 2003-05-07 | 2007-12-06 | Qimonda Ag | Verfahren zur Herstellung einer leitfähigen Verbindung zwischen einem Halbleiterchip und einer äußeren Leiterstruktur |
| JP4130158B2 (ja) * | 2003-06-09 | 2008-08-06 | 三洋電機株式会社 | 半導体装置の製造方法、半導体装置 |
| JP2006093367A (ja) * | 2004-09-24 | 2006-04-06 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
| US20080079175A1 (en) * | 2006-10-02 | 2008-04-03 | Michael Bauer | Layer for chip contact element |
| DE102006046851B4 (de) * | 2006-10-02 | 2011-02-10 | Infineon Technologies Ag | Verfahren zum Schützen der Kontaktelemente eines Halbleiterwafers |
| KR101199716B1 (ko) * | 2006-12-15 | 2012-11-08 | 다우 글로벌 테크놀로지스 엘엘씨 | 알데히드 및 케톤의 환원성 아민화 방법 |
| US7928582B2 (en) * | 2007-03-09 | 2011-04-19 | Micron Technology, Inc. | Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces |
| US7923645B1 (en) * | 2007-06-20 | 2011-04-12 | Amkor Technology, Inc. | Metal etch stop fabrication method and structure |
| US20100101840A1 (en) * | 2008-10-29 | 2010-04-29 | Raytheon Company | Application of a self-assembled monolayer as an oxide inhibitor |
| CN103311223A (zh) * | 2013-06-14 | 2013-09-18 | 深圳市创智成功科技有限公司 | 晶圆电镀镍金产品及其制备方法 |
| DE102016106137B4 (de) | 2016-04-04 | 2023-12-28 | Infineon Technologies Ag | Elektronikvorrichtungsgehäuse umfassend eine dielektrische Schicht und ein Kapselungsmaterial |
| US9922922B1 (en) | 2016-09-16 | 2018-03-20 | Omnivision Technologies, Inc. | Microchip with cap layer for redistribution circuitry and method of manufacturing the same |
| US11682640B2 (en) | 2020-11-24 | 2023-06-20 | International Business Machines Corporation | Protective surface layer on under bump metallurgy for solder joining |
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| JPH0684917A (ja) * | 1992-08-31 | 1994-03-25 | Tanaka Kikinzoku Kogyo Kk | 高周波用バンプの形成方法 |
| JPH09232898A (ja) * | 1996-02-23 | 1997-09-05 | Oki Electric Ind Co Ltd | Ｓａｗフィルタチップ及びその製造方法 |
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| US6441500B1 (en) * | 1999-09-13 | 2002-08-27 | Sharp Kabushiki Kaisha | Semiconductor device having resin members provided separately corresponding to externally connecting electrodes |
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| CN1542908A (zh) | 2004-11-03 |
| US7115496B2 (en) | 2006-10-03 |
| DE10318078B4 (de) | 2007-03-08 |
| US20040248343A1 (en) | 2004-12-09 |
| DE10318078A1 (de) | 2004-11-25 |
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