CN1308773A - 半导体元件的封壳 - Google Patents

半导体元件的封壳 Download PDF

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CN1308773A
CN1308773A CN99808331A CN99808331A CN1308773A CN 1308773 A CN1308773 A CN 1308773A CN 99808331 A CN99808331 A CN 99808331A CN 99808331 A CN99808331 A CN 99808331A CN 1308773 A CN1308773 A CN 1308773A
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flange
electrically insulating
insulating substrate
capsule
copper
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CN1192428C (zh
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L-A·乌洛夫松
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Infineon Technologies AG
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Telefonaktiebolaget LM Ericsson AB
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Abstract

本发明涉及一种用于至少一个高频大功率晶体管芯片(17)的封壳(1),包括导电导热法兰(10)、至少两个电绝缘衬底(15)、至少两个电接点(16)和盖件,其中大功率晶体管芯片(17)设置在法兰(10)上。大功率晶体管芯片(17)和电绝缘衬底(15)放置在法兰(10)上。电接点(16)设置在电绝缘衬底(15)上,电绝缘衬底(15)与法兰(10)连接,并且是开口的,与大功率晶体管芯片(17)隔开。

Description

半导体元件的封壳
本发明涉及一种半导体元件的封壳,特别涉及例如LDMOS晶体管等需要最高热传导性且可以表面焊接的高频功率晶体管的封壳。
发明的背景
用于例如移动电话的基站发射器或如数字无线电和模拟TV的地面发射器等高频无线电发射器的功率级的高频功率晶体管主要有两种类型,即双极和LDMOS型。双极型晶体管必须安装在电绝缘体上,而LDMOS型晶体管可以安装在下层导电表面上。
一般可以利用包封晶体管的框架形式的陶瓷电绝缘体包封LDMOS晶体管。LDMOS晶体管安装到所谓的导电法兰上。在至少一个电路板和晶体管间用作导体的接点与电绝缘框架连接。陶瓷绝缘体可以由氧化铝构成,是由于热流无法穿过陶瓷材料。
已有技术的一个问题是法兰必须包括CuW(铜和钨的复合体),以便实现陶瓷和法兰间线性膨胀的有效匹配。CuW法兰较贵,而导电率仅是铜的一半。另一个问题是,由于框架和法兰间的热膨胀差,封壳制造期间,电绝缘框架会变脆,容易龟裂,所以造成了低成品率和非常昂贵的封壳。另外,不能表面焊接目前的功率晶体管封壳。
发明概述
高频晶体管已有封壳的一个问题是,它们包括在制造封壳期间容易龟裂的窄电绝缘陶瓷框架。
另一个问题是,所谓的法兰需要特殊材料,例如CuW,以实现法兰和陶瓷框架间线性膨胀的最佳匹配。
再一个问题是,CuW没有令人满意的导电性。
本发明通过用于至少一个高频、大功率晶体管芯片的封壳介质解决了上述问题,所说封壳介质包括导电导热法兰、至少两个电绝缘衬底、至少两个电接点、和盖件,其中大功率晶体管芯片和电绝缘衬底设置在法兰上,电接点设置在电绝缘衬底上。电绝缘衬底设置成局部封闭芯片。
法兰一般可以是铜制的。在优选实施例中,当本发明应表面焊接时,电绝缘衬底设置在法兰的至少两个侧缘上。所说衬底从其上侧绕一个边缘向下到下侧被金属化。
由于可以给出小尺寸衬底,所以法兰材料和衬底材料间的线性膨胀间的差异可以很大,但没有衬底龟裂的危险。
本发明的目的是提供一种具有较好的热传导性、比现有技术相关部件便宜且能够表面焊接的封壳。
本发明的一个优点是法兰可以采用铜。
另一个优点是电绝缘衬底硬焊到法兰上后,没有劈裂的危险。
下面结合例示实施例及附图,更具体介绍本发明。
附图简介
图1是去掉了其盖件的已知封壳的侧剖图。
图2示出了去掉了其盖件的已知封壳的俯视图。
图3是另一实施例的去掉了其盖件的封壳的侧剖图。
图4是本发明另一实施例的去掉了其盖件的封壳的侧剖图。
图5是去掉了其盖件的图?或图?的封壳的俯视图。
图6是去掉了其盖件的图?或图?的封壳的俯视图。
图7是本发明另一实施例的去掉了其盖件的封壳的侧剖图。
图8是本发明再一实施例的去掉了其盖件的封壳的侧剖图。
优选实施例的具体介绍
图1是去掉了其盖件的已知封壳的侧剖图。封壳1包括法兰10、电绝缘衬底15、两个电接点16、带有关接点导体18的高频晶体管芯片17。法兰10由其线性膨胀系数适应电绝缘衬底15的材料的导电材料制造。尽管未示出,但封壳还包括盖件。
图2是图1所示已知封壳的俯视图。从该透视图可以看出,电绝缘衬底15按框架形结构绕高频晶体管芯片17设置,还可以看出,法兰包括一对孔20,这些孔用于借助于一对螺钉或铆钉连接法兰10与冷却器。
图3是去掉了其盖件的本发明封壳的侧剖图。该实施例中,电绝缘衬底15容纳在法兰10的侧缘上的两个凹槽内。如图3所示,衬底15可以具有与与之连接的法兰10相同的高度。图3所示实施例的电绝缘衬底配有从一个上侧绕侧缘并在底侧上的金属化形式的电接点16,以实现封壳上侧与下侧的低感应电连接。
图4是图3所示实施例的侧视图。图5从上部示出了图3和4的实施例。从图4和5可以看出,金属化和法兰10间留有间隙,所以避免了两者间的接触。电绝缘衬底可以通过按所属领域技术人员已知的方式印刷?被金属化,所以这里不再介绍所说的金属化方式。
图6从上部示出了去掉了盖件的本发明封壳的另一实施例。该实施例中,电绝缘衬底沿法兰的侧缘的充分延伸部分设置,而不是设置于所说凹槽内。如图5所示,构成衬底上的电接点的金属化可以是不完全的,换言之,各表面不必被完全覆盖。然而,金属化可以不与法兰10接触。
图7是去掉了盖件的本发明封壳的另一实施例的侧剖图。该实施例中,为简化制造,改进了电绝缘衬底15和衬底将与之连接的法兰的边缘。在图7所示实施例中,法兰10与衬底15的连接面彼此间采用台阶状结构。法兰与衬底的这种简化结合允许底侧是平坦的。
根据图8,提高封壳性能的因素在于通过电绝缘衬底15设置所谓的通路25。这种通路将减小电接点中的串联感应。
法兰可以包括用于安装电路板或冷却器的大量螺钉孔20或小孔。然而,或者法兰可以焊接到电路板上,因此不需要螺钉孔。
每个电绝缘衬底可以包括一个或多个电接点16。
关于具有良好导热性并适于用作法兰材料的材料,例子有铜、铜-金刚石复合体、铜-钼-铜复合体、铜-钨-铜复合体。
应理解,本发明不限于这里所介绍和例示的各实施例,可以做出改进,而不脱离权利要求书的范围。

Claims (9)

1.一种用于至少一个高频大功率晶体管芯片(17)的封壳,包括导电导热法兰(10)、至少两个电绝缘衬底(15)、至少两个电接点(16)和盖件,其中大功率晶体管芯片(17)设置在法兰(10)上,电接点(16)设置在电绝缘衬底(15)上,其特征在于,电绝缘衬底(15)设置为与法兰(10)连接,并且是开口的,与大功率芯片(17)隔开。
2.根据权利要求1所述的封壳,其特征在于,法兰是铜制的。
3.根据权利要求1所述的封壳,其特征在于,法兰(10)由铜-钼-铜复合体或铜-钨-铜复合体或铜-金刚石复合体构成。
4.根据权利要求2或3所述的封壳,其特征在于,电绝缘衬底(15)沿所说法兰(10)的至少一个侧缘上的凹槽设置。
5.根据权利要求2或3所述的封壳,其特征在于,电绝缘衬底(15)沿所说法兰(10)的侧缘的充分延伸部设置。
6.根据权利要求1或2所述的封壳,其特征在于,电绝缘衬底(15)从上侧绕侧缘向下到下侧被金属化。
7.根据权利要求4或5所述的封壳,其特征在于,电绝缘衬底(15)包括从电绝缘体(15)的上侧延伸到下侧的导电通路。
8.根据权利要求6或7所述的封壳,其特征在于,将与法兰(10)连接的电绝缘衬底(15)的侧缘具有与法兰(10)侧缘的形状和大小相适应的几何形状,所以可以使法兰的上下侧和电绝缘衬底的上下侧彼此容易相互成同一平面。
9.根据权利要求8所述的封壳,其特征在于,所说几何结构是台阶状结构。
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Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6580159B1 (en) * 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
KR100369393B1 (ko) 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
US7309446B1 (en) 2004-02-25 2007-12-18 Metadigm Llc Methods of manufacturing diamond capsules
US9470485B1 (en) 2004-03-29 2016-10-18 Victor B. Kley Molded plastic cartridge with extended flash tube, sub-sonic cartridges, and user identification for firearms and site sensing fire control
JP2006316040A (ja) 2005-05-13 2006-11-24 Genentech Inc Herceptin(登録商標)補助療法
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US8208266B2 (en) * 2007-05-29 2012-06-26 Avx Corporation Shaped integrated passives
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8110915B2 (en) * 2009-10-16 2012-02-07 Infineon Technologies Ag Open cavity leadless surface mountable package for high power RF applications
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
TWI408837B (zh) * 2011-02-08 2013-09-11 Subtron Technology Co Ltd 封裝載板及其製作方法
US8698291B2 (en) 2011-12-15 2014-04-15 Freescale Semiconductor, Inc. Packaged leadless semiconductor device
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US8803302B2 (en) 2012-05-31 2014-08-12 Freescale Semiconductor, Inc. System, method and apparatus for leadless surface mounted semiconductor package
JP2014017318A (ja) * 2012-07-06 2014-01-30 Toyota Industries Corp 半導体装置
US8963305B2 (en) 2012-09-21 2015-02-24 Freescale Semiconductor, Inc. Method and apparatus for multi-chip structure semiconductor package
KR20150129673A (ko) 2013-01-16 2015-11-20 지멘스 리서치 센터 리미티드 라이어빌리티 컴퍼니 칩 패키지 어셈블리
US9921017B1 (en) 2013-03-15 2018-03-20 Victor B. Kley User identification for weapons and site sensing fire control
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097089A (en) * 1998-01-28 2000-08-01 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
US3946428A (en) * 1973-09-19 1976-03-23 Nippon Electric Company, Limited Encapsulation package for a semiconductor element
JPS5315763A (en) * 1976-07-28 1978-02-14 Hitachi Ltd Resin sealed type semiconductor device
US4376287A (en) * 1980-10-29 1983-03-08 Rca Corporation Microwave power circuit with an active device mounted on a heat dissipating substrate
US4819041A (en) * 1983-12-30 1989-04-04 Amp Incorporated Surface mounted integrated circuit chip package and method for making same
FR2563050B1 (fr) * 1984-04-13 1987-01-16 Thomson Csf Combineur compact de dispositifs semiconducteurs, fonctionnant en hyperfrequences
US4943470A (en) * 1985-01-11 1990-07-24 Ngk Spark Plug Co., Ltd. Ceramic substrate for electrical devices
US5012386A (en) * 1989-10-27 1991-04-30 Motorola, Inc. High performance overmolded electronic package
US5166097A (en) * 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
JP2857725B2 (ja) * 1991-08-05 1999-02-17 株式会社日立製作所 樹脂封止型半導体装置
US5438305A (en) * 1991-08-12 1995-08-01 Hitachi, Ltd. High frequency module including a flexible substrate
US5397912A (en) * 1991-12-02 1995-03-14 Motorola, Inc. Lateral bipolar transistor
JPH06120374A (ja) * 1992-03-31 1994-04-28 Amkor Electron Inc 半導体パッケージ構造、半導体パッケージ方法及び半導体パッケージ用放熱板
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5598034A (en) * 1992-07-22 1997-01-28 Vlsi Packaging Corporation Plastic packaging of microelectronic circuit devices
US5422615A (en) * 1992-09-14 1995-06-06 Hitachi, Ltd. High frequency circuit device
US5481136A (en) * 1992-10-28 1996-01-02 Sumitomo Electric Industries, Ltd. Semiconductor element-mounting composite heat-sink base
US5642261A (en) * 1993-12-20 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball-grid-array integrated circuit package with solder-connected thermal conductor
JPH07221218A (ja) * 1994-02-03 1995-08-18 Toshiba Corp 半導体装置
EP0704092A1 (fr) * 1994-04-18 1996-04-03 Gay Frères Vente et Exportation S.A. Dispositif a memoire electronique
US5458716A (en) * 1994-05-25 1995-10-17 Texas Instruments Incorporated Methods for manufacturing a thermally enhanced molded cavity package having a parallel lid
US5969414A (en) * 1994-05-25 1999-10-19 Advanced Technology Interconnect Incorporated Semiconductor package with molded plastic body
JP3367299B2 (ja) * 1994-11-11 2003-01-14 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
EP0742682B1 (en) * 1995-05-12 2005-02-23 STMicroelectronics, Inc. Low-profile socketed integrated circuit packaging system
JP3206717B2 (ja) * 1996-04-02 2001-09-10 富士電機株式会社 電力用半導体モジュール
TW332334B (en) * 1996-05-31 1998-05-21 Toshiba Co Ltd The semiconductor substrate and its producing method and semiconductor apparatus
JP2904141B2 (ja) * 1996-08-20 1999-06-14 日本電気株式会社 半導体装置
US5856911A (en) * 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
JP4030028B2 (ja) * 1996-12-26 2008-01-09 シチズン電子株式会社 Smd型回路装置及びその製造方法
US5920458A (en) * 1997-05-28 1999-07-06 Lucent Technologies Inc. Enhanced cooling of a heat dissipating circuit element
US6011691A (en) * 1998-04-23 2000-01-04 Lockheed Martin Corporation Electronic component assembly and method for low cost EMI and capacitive coupling elimination

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SE512710C2 (sv) 2000-05-02
CN1192428C (zh) 2005-03-09
EP1116271A2 (en) 2001-07-18
SE9802453D0 (sv) 1998-07-08
US6465883B2 (en) 2002-10-15
US20020014694A1 (en) 2002-02-07
SE9802453L (sv) 2000-01-09
AU4948199A (en) 2000-02-01
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TW441057B (en) 2001-06-16
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JP2002520855A (ja) 2002-07-09

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