CN1288755C - 半导体装置和形成半导体装置的方法 - Google Patents

半导体装置和形成半导体装置的方法 Download PDF

Info

Publication number
CN1288755C
CN1288755C CNB028091264A CN02809126A CN1288755C CN 1288755 C CN1288755 C CN 1288755C CN B028091264 A CNB028091264 A CN B028091264A CN 02809126 A CN02809126 A CN 02809126A CN 1288755 C CN1288755 C CN 1288755C
Authority
CN
China
Prior art keywords
doped region
gate
metal
dielectric
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB028091264A
Other languages
English (en)
Other versions
CN1520613A (zh
Inventor
塔特·恩盖
比施－银·恩古银
维德亚·S·考什克
詹姆斯·K·Iii·谢弗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1520613A publication Critical patent/CN1520613A/zh
Application granted granted Critical
Publication of CN1288755C publication Critical patent/CN1288755C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本文公开一种具有双栅电极(60，50)的半导体装置以及形成这种半导体装置的方法。第一金属/硅栅堆和第一栅电介质(40)在第一掺杂区形成。金属/栅堆(60，50)包括第一栅电介质(40)上面的金属部分(50)和金属部分(50)上面的第一栅部分(60)。硅栅(60)和第二栅电介质(40)在第二掺杂区形成。在一种实施例中，第一和第二栅部分是P+掺杂硅锗，而金属部分是TaSiN。在另一实施例中，第一和第二栅部分是N+掺杂的多晶硅，而金属部分是TaSiN。

Description

半导体装置和形成半导体装置的方法
技术领域
本发明一般涉及半导体装置和形成半导体装置的方法，特别涉及具有双栅极的半导体装置和形成这种半导体装置的方法。
背景技术
传统上使用多晶硅作MOS晶体管的栅电极。多晶硅电极一般掺杂P+或N+以匹配CMOS技术的源区和漏区的掺杂。然而，随着装置尺寸缩小，使用多晶硅作为栅电极就产生了问题。例如，随着P+掺杂的多晶硅栅电极尺寸的减小，硼可以通过栅电介质从多晶硅栅电极渗入并降低装置的可靠性。另外，随着P+和N+掺杂的多晶硅尺寸的缩小，掺杂浓度会增加。为了将掺杂物打入栅电极，需要执行高温处理。由于尺寸缩小，源极和漏极会变薄。不利之处在于，高温处理可能使源极和漏极变得更深。然而，如果不使用高温，掺杂物很可能存在于远离栅极电介质的位置。因此，需要一个没有掺杂的栅电极区域。这个多耗尽效应(polydepletion effect)将作为附加的电容与栅电介质电容串联。换句话说，不希望增加晶体管的有效氧化物厚度。多耗尽效应在原有技术中不是重要的效应，因为多耗尽区域的厚度比栅极介质的有效厚度要小。
一个解决方案是使用逸出功与P掺杂硅或N掺杂硅的逸出功近似相等的材料。P掺杂硅具有的逸出功大约为4.1eV，而N掺杂硅具有的逸出功大约为5.2eV。难点是选择均适合于这两个数值的材料。另一个选择方案是使用两个不同的材料，其中一个材料的逸出功近似等于N掺杂硅的逸出功，而另一个材料的逸出功近似等于P掺杂硅的逸出功。但是很难找到两种具有并入CMOS工艺流程所需的化学和热稳定性、具有不同逸出功的材料。因此，需要找寻适用于缩小器件的栅材料。
附图说明
本发明通过附图举例说明但不限于附图，其中类似的参考指示相似的组件，其中：
图1包括在形成栅极介质和金属栅电极层后半导体器件衬底的一部分的剖视图图示。
图2包括在使金属栅层形成图案(pattern)后半导体器件衬底的一部分的剖视图图示。
图3包括在形成多晶硅层后图2衬底的剖视图图示。
图4包括在使多晶硅金属栅和栅极介质层形成图案后图3衬底的剖视图图示。
图5包括在形成基本完整的器件后图4衬底的剖视图图示。
本领域的普通技术人员可以理解，附图中的组件是为了简单和清楚起见而示出的，没有必要按比例制图。例如，图形中某些组件的尺寸可能相对于其它组件放大，以帮助增进对本发明实施例的理解。
具体实施方式
硅的导带低于真空能级4.1eV。价电子带低于硅的导带1.1eV左右或者说低于真空能级5.2eV。硅的价电子带和导带之间的1.1eV左右的差异称为带隙。中隙大约是带隙的一半，并且大约在材料的导带和价电子带之间的中间部分。N沟道晶体管栅电极所需的逸出功在半导体衬底的导带和中隙之间。N沟道晶体管所更需要的逸出功与中隙还至少相差0.2eV。换句话说，N沟道晶体管所更需要的逸出功是低于真空能级大约4.1eV到4.5eV之间。P沟道晶体管栅电极所需的逸出功在半导体衬底的价电子带和中隙之间。P沟道晶体管所更需要的逸出功与中隙还至少相差0.2eV或者说低于真空能级4.9eV到5.2eV之间。
图1示出了半导体衬底10内用来隔离后来形成的晶体管的沟道20。在优选实施例中，沟道20是浅沟道隔离区。本领域的普通技术人员知道，为了形成沟道20，使用了传统的蚀刻和淀积工艺。半导体衬底10可以是单晶硅、硅锗、镓砷、绝缘体上的外延硅(SO1)等等。在第一实施例中，半导体衬底10是P掺杂硅。硅可以是用硼掺杂硅的P型掺杂。在该实施例中，势阱30是N掺杂势阱。势阱30可以通过注入砷、磷等来进行N型掺杂。栅极介质40在半导体衬底10上面形成。在一实施例中，栅极介质40是SiO2。在该实施例中，对栅极介质40进行热生长处理，厚度生长到大约15到50埃。本领域的普通技术人员可以理解，随着器件缩小，SiO2的厚度可能减小到15埃以下。在另一实施例中，栅极介质40可以是氧化物，特别是金属氧化物，例如HfO2、ZrO2、Al2O3、La2O3或者这些金属氧化物的组合等等。如果栅极介质40是金属氧化物，它通常的厚度在大约5-100埃，或者最好为小于25埃。如果栅极介质40是金属氧化物，就可以使用微粒层淀积(ALD)、化学气相淀积(CVD)、物理气相淀积(PVD)或者这些淀积法的组合来淀积。
然后，可以使用ALD、CVD、PVD或其中的组合等来淀积金属栅层50。金属栅层50可以是氮化硅钽(TaSiN)、铂、氧化钉、氮化钼、氮化硅钨、氮化钽、氮化硅钼、氮化硅钛和氮化钨。已经证明，氮化硅钽是NMOS器件的适用材料，而铂和氮化钨适用于PMOS器件。在优选实施例中，金属栅层50是氮化硅钽(TaSiN)，硅或氮浓度可以被调整以改变该材料的逸出功。例如，增加硅的浓度将使该材料的逸出功降低到大约4.4eV。增加氮的浓度是与逸出功成正比的。因此，增加氮浓度可以产生大约4.8eV的逸出功。
参看图2，半导体衬底10形成图案(pattern)，金属栅层50被蚀刻。金属栅层50保留在包含势阱30的部分半导体衬底的上面。金属栅层50也可以保留在沟道20的有效部分上面。类似于用来蚀刻多晶硅的蚀刻化学过程能够被用于形成金属栅层50。基于卤化物的化学物质，例如四氟化碳(CF4)、六氟乙烷(C2F6)、溴化氢(HBr)、六氟化硫(SF6)、氯化氢(HCl)、氯分子(Cl2)等等能够在等离子蚀刻、反应离子蚀刻、电子回旋共振蚀刻或者微波蚀刻过程中使用。在金属栅层50已经形成图案之后，使用传统方法，例如将光致抗蚀剂暴露于含氧的环境中，光致抗蚀层就会被去除。金属栅层50大致大于或等于50埃。一般地，使用终点检测来进行蚀刻。还可以进行定时的蚀刻。
参看图3所示，形成第二栅电极60。在第一实施例中，第二栅电极60是掺杂硅层。硅栅60包括淀积的非晶态硅或者多晶硅，并且在原位置掺杂或者在单独的掺杂步骤中掺杂。在这个特殊实施例中，第二栅电极60的厚度大约为1000-2000埃。可选地，可以在掺杂硅层60上面形成防反射涂层(ARC)。
光致抗蚀剂层沉积在掺杂硅层60的上面。可以使用与先前用于蚀刻金属栅层50的相同的蚀刻化学过程和工艺来蚀刻第二栅电极60和金属栅层50。如果栅极介质40是二氧化硅(SiO2)，就可以使用稀HF的湿蚀刻。一般地，水和HF的浓度为100∶1。如果栅极介质40是金属氧化物，就可以使用HF或者磷酸。如图4所示，产生的结构是形成金属/栅或栅堆的金属栅层和第二栅电极60。如果第二栅电极60是硅，那么堆就是金属/硅栅堆。在一实施例中，金属/硅栅堆是硅栅部分上面的氮化硅钽的栅部分。
处理工艺继续形成如图5所示的其余的半导体器件。在离子注入过程中，形成源极和漏极80。在第一实施例中，源极和漏极80为N掺杂，而源极和漏极81为P掺杂。在栅电极和栅极介质周围形成隔板70。一般地，隔板是由氮化物形成的。对于本领域普通技术人员来说，可以理解，CMOS工艺处理将从这个点继续进行。
虽然本发明的第一实施例已经根据具体的掺杂类型进行了描述，本领域技术人员可以理解，掺杂类型可以是相反的。例如，半导体衬底10可以是N掺杂的，而势阱30可以是P掺杂的。在这种情况下，硅电极将在P掺杂势阱的上面，而金属/硅堆电极将在N掺杂的区域的上面。
在第二实施例中，将在P型衬底或者P势阱上方形成由半导体材料和金属组成的堆，在N势阱上方形成半导体栅。这可以通过制造N掺杂的半导体衬底10和P掺杂的势阱30来实现。或者，如果半导体衬底10是P型的，将在半导体衬底10上方形成金属/硅堆，而在势阱30上方单独形成栅电极。在该实施例中，半导体电极是P掺杂硅锗。所讨论的有关第一个实施例的全部蚀刻和构成处理工艺均可以用于第二实施例。
使用金属电极用于N沟道晶体管或P沟道晶体管并使用硅电极用于另一个晶体管是很有益的。这样可以重复使用已经在半导体领域中建立起来的硅处理工艺和工具。另外，它不再需要寻找具有所需的N沟道和P沟道晶体管的逸出功、具有化学和热稳定性的两种不同的材料。而且，也不需要一种具有两种不同逸出功的材料。
在上述说明书中，已经参照具体实施例对本发明进行了描述。然而，本领域的普通技术人员可以理解，在不背离如所附权利要求所述的本发明的范围的前提下，可以对本发明进行各种修改和改变。因此，本说明书和附图可以认为是示例性的而不具有限制性意义，所有这样的修改都可认为包含在本发明的范围内。
上面已经描述了关于具体实施例的益处、其它优点和问题的解决方案。然而，这些益处、优点或提出的解决方案，或者可以带来这些益处、优点或解决方案或使之更显著的任何组件都不能被理解为任何或所有权利要求的关键的、必须的或者重要的特性或组件。在本文中所使用的术语“包含(comprises、comprising)”或者其另外的变化都意旨涵盖非排它性的包含，因此，包含一系列组件的工艺处理、方法、物品或者装置并不仅仅包括这些组件，还可能包括未明确示出的或者这样的工艺处理、方法、物品或者装置所固有的其它组件。

Claims (9)

1.一种形成半导体装置的方法，其包括：
提供具有第一掺杂区域和第二掺杂区域的半导体衬底；
在所述第一掺杂区和所述第二掺杂区上面提供电介质；
提供与所述电介质相接触的金属层；
将所述金属层形成图案，以将金属部分留在至少部分所述第一掺杂区之上；
在所述金属部分和所述第二掺杂区上形成硅层；以及
将所述硅层和金属部分形成图案，以将硅栅留在所述第二掺杂区之上，将金属/硅栅堆留在所述第一掺杂区之上。
2.如权利要求1所述的方法，其中所述的硅层在原位置掺杂了一种或多种砷和磷。
3.如权利要求1所述的方法，其中所述的硅层在原位置掺杂了锗。
4.如权利要求3所述的方法，其中所述的硅层掺杂了硼。
5.如权利要求1所述的方法，其中所述的半导体衬底具有价电子带和传导带，价电子带和传导带之间具有中间隙，所述金属层在所述价电子带和所述中间隙之间具有逸出功。
6.如权利要求1所述的方法，其中所述的半导体衬底具有价电子带和传导带，价电子带和传导带之间具有中间隙，所述金属层在所述价电子带和传导带之间具有与所述中间隙至少相差0.2eV的逸出功。
7.如权利要求1所示，其中所述的半导体衬底具有价电子带和传导带，价电子带和传导带之间具有中间隙，所述金属层在所述传导带和所述中间隙之间具有逸出功。
8.一种半导体装置，其包括：
半导体衬底，其包括第一掺杂区域和第二掺杂区域；
所述第一掺杂区域上的第一栅电介质；
所述第一栅电介质上的金属/硅栅堆，其中所述的金属/硅栅堆包括与所述第一栅电介质相接触的金属部分和所述金属部分上的多晶硅部分；
所述第二掺杂区域上的第二栅电介质；以及
所述第二栅电介质上的硅栅。
9.一种形成半导体装置的方法，其包括：
提供具有第一掺杂区和第二掺杂区的半导体衬底；
在所述第一掺杂区和所述第二掺杂区上提供介质层；
提供与所述介质层相接触的氮化硅钽层；
将所述氮化硅钽层形成图案，以将氮化硅钽部分留在至少部分所述第一掺杂区的上面；
在所述氮化硅钽部分和所述第二掺杂区上面形成原位上的掺杂硅层；以及
将所述原位掺杂硅层和所述氮化硅钽部分形成图案，以将硅栅留在所述第二掺杂区上面，将栅堆留在所述第一掺杂区上面，其中所述的栅堆包括硅栅部分上面的氮化硅钽栅部分。
CNB028091264A 2001-05-26 2002-04-24 半导体装置和形成半导体装置的方法 Expired - Fee Related CN1288755C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/865,855 US6518106B2 (en) 2001-05-26 2001-05-26 Semiconductor device and a method therefor
US09/865,855 2001-05-26

Publications (2)

Publication Number Publication Date
CN1520613A CN1520613A (zh) 2004-08-11
CN1288755C true CN1288755C (zh) 2006-12-06

Family

ID=25346391

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028091264A Expired - Fee Related CN1288755C (zh) 2001-05-26 2002-04-24 半导体装置和形成半导体装置的方法

Country Status (8)

Country Link
US (1) US6518106B2 (zh)
EP (1) EP1396024A2 (zh)
JP (1) JP2006523008A (zh)
KR (1) KR100867565B1 (zh)
CN (1) CN1288755C (zh)
AU (1) AU2002254726A1 (zh)
TW (1) TW557475B (zh)
WO (1) WO2002097889A2 (zh)

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001257344A (ja) * 2000-03-10 2001-09-21 Toshiba Corp 半導体装置及び半導体装置の製造方法
US9139906B2 (en) * 2001-03-06 2015-09-22 Asm America, Inc. Doping with ALD technology
US7563715B2 (en) * 2005-12-05 2009-07-21 Asm International N.V. Method of producing thin films
US6596597B2 (en) * 2001-06-12 2003-07-22 International Business Machines Corporation Method of manufacturing dual gate logic devices
US6700771B2 (en) * 2001-08-30 2004-03-02 Micron Technology, Inc. Decoupling capacitor for high frequency noise immunity
JP2003086798A (ja) * 2001-09-13 2003-03-20 Nec Corp 半導体装置およびその製造方法
US6794252B2 (en) * 2001-09-28 2004-09-21 Texas Instruments Incorporated Method and system for forming dual work function gate electrodes in a semiconductor device
US6873020B2 (en) * 2002-02-22 2005-03-29 North Carolina State University High/low work function metal alloys for integrated circuit electrodes
KR100487525B1 (ko) * 2002-04-25 2005-05-03 삼성전자주식회사 실리콘게르마늄 게이트를 이용한 반도체 소자 및 그 제조방법
US6794281B2 (en) * 2002-05-20 2004-09-21 Freescale Semiconductor, Inc. Dual metal gate transistors for CMOS process
US6894353B2 (en) * 2002-07-31 2005-05-17 Freescale Semiconductor, Inc. Capped dual metal gate transistors for CMOS process and method for making the same
US7030024B2 (en) * 2002-08-23 2006-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Dual-gate structure and method of fabricating integrated circuits having dual-gate structures
US20060060565A9 (en) * 2002-09-16 2006-03-23 Applied Materials, Inc. Method of etching metals with high selectivity to hafnium-based dielectric materials
US6858524B2 (en) * 2002-12-03 2005-02-22 Asm International, Nv Method of depositing barrier layer for metal gates
US7045406B2 (en) * 2002-12-03 2006-05-16 Asm International, N.V. Method of forming an electrode with adjusted work function
US7122414B2 (en) * 2002-12-03 2006-10-17 Asm International, Inc. Method to fabricate dual metal CMOS devices
US20040135218A1 (en) * 2003-01-13 2004-07-15 Zhizhang Chen MOS transistor with high k gate dielectric
US7071086B2 (en) * 2003-04-23 2006-07-04 Advanced Micro Devices, Inc. Method of forming a metal gate structure with tuning of work function by silicon incorporation
US20050070103A1 (en) * 2003-09-29 2005-03-31 Applied Materials, Inc. Method and apparatus for endpoint detection during an etch process
US7183221B2 (en) * 2003-11-06 2007-02-27 Texas Instruments Incorporated Method of fabricating a semiconductor having dual gate electrodes using a composition-altered metal layer
US20050104142A1 (en) * 2003-11-13 2005-05-19 Vijav Narayanan CVD tantalum compounds for FET get electrodes
KR100616499B1 (ko) * 2003-11-21 2006-08-28 주식회사 하이닉스반도체 반도체소자 제조 방법
US20050221513A1 (en) * 2004-03-31 2005-10-06 Tokyo Electron Limited Method of controlling trimming of a gate electrode structure
US7105889B2 (en) * 2004-06-04 2006-09-12 International Business Machines Corporation Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
TWI367560B (en) * 2004-07-05 2012-07-01 Samsung Electronics Co Ltd Integrated circuit devices including a dual gate stack structure and methods of forming the same
JP2006108602A (ja) * 2004-09-10 2006-04-20 Toshiba Corp 半導体装置及びその製造方法
KR100889362B1 (ko) * 2004-10-19 2009-03-18 삼성전자주식회사 다층 유전체막으로 이루어진 트랜지스터 및 그 제조 방법
WO2006072975A1 (ja) * 2005-01-05 2006-07-13 Fujitsu Limited 半導体装置とその製造方法
US7109079B2 (en) * 2005-01-26 2006-09-19 Freescale Semiconductor, Inc. Metal gate transistor CMOS process and method for making
US7282426B2 (en) * 2005-03-29 2007-10-16 Freescale Semiconductor, Inc. Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof
KR100706244B1 (ko) * 2005-04-07 2007-04-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR100596487B1 (ko) * 2005-04-12 2006-07-04 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP2007019396A (ja) * 2005-07-11 2007-01-25 Renesas Technology Corp Ｍｏｓ構造を有する半導体装置およびその製造方法
JP2007019395A (ja) * 2005-07-11 2007-01-25 Renesas Technology Corp Ｍｏｓ構造を有する半導体装置及びその製造方法
JP2007019400A (ja) * 2005-07-11 2007-01-25 Renesas Technology Corp Ｍｏｓ構造を有する半導体装置およびその製造方法
JP2007036116A (ja) * 2005-07-29 2007-02-08 Renesas Technology Corp 半導体装置の製造方法
KR100697694B1 (ko) * 2005-08-02 2007-03-20 삼성전자주식회사 듀얼 게이트를 갖는 반도체 장치 및 그 제조 방법
US20070048920A1 (en) * 2005-08-25 2007-03-01 Sematech Methods for dual metal gate CMOS integration
JP2007088122A (ja) * 2005-09-21 2007-04-05 Renesas Technology Corp 半導体装置
JP2007123548A (ja) * 2005-10-28 2007-05-17 Renesas Technology Corp 半導体装置の製造方法
KR100647472B1 (ko) * 2005-11-23 2006-11-23 삼성전자주식회사 반도체 장치의 듀얼 게이트 구조물 및 그 형성 방법.
US20070152276A1 (en) * 2005-12-30 2007-07-05 International Business Machines Corporation High performance CMOS circuits, and methods for fabricating the same
US7811891B2 (en) * 2006-01-13 2010-10-12 Freescale Semiconductor, Inc. Method to control the gate sidewall profile by graded material composition
US7452777B2 (en) * 2006-01-25 2008-11-18 Fairchild Semiconductor Corporation Self-aligned trench MOSFET structure and method of manufacture
KR100827435B1 (ko) * 2006-01-31 2008-05-06 삼성전자주식회사 반도체 소자에서 무산소 애싱 공정을 적용한 게이트 형성방법
US7446026B2 (en) * 2006-02-08 2008-11-04 Freescale Semiconductor, Inc. Method of forming a CMOS device with stressor source/drain regions
US8084367B2 (en) * 2006-05-24 2011-12-27 Samsung Electronics Co., Ltd Etching, cleaning and drying methods using supercritical fluid and chamber systems using these methods
KR100729367B1 (ko) * 2006-06-01 2007-06-15 삼성전자주식회사 반도체 장치 및 그 제조 방법
TW200818271A (en) * 2006-06-21 2008-04-16 Tokyo Electron Ltd Method of forming TaSiN film
JP2008016538A (ja) * 2006-07-04 2008-01-24 Renesas Technology Corp Ｍｏｓ構造を有する半導体装置及びその製造方法
WO2008042981A2 (en) 2006-10-05 2008-04-10 Asm America, Inc. Ald of metal silicate films
US7727864B2 (en) * 2006-11-01 2010-06-01 Asm America, Inc. Controlled composition using plasma-enhanced atomic layer deposition
US7435652B1 (en) * 2007-03-30 2008-10-14 International Business Machines Corporation Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET
KR100835430B1 (ko) * 2007-05-21 2008-06-04 주식회사 동부하이텍 반도체 소자의 듀얼 게이트 전극 형성 방법
US20080290416A1 (en) * 2007-05-21 2008-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. High-k metal gate devices and methods for making the same
US7709331B2 (en) * 2007-09-07 2010-05-04 Freescale Semiconductor, Inc. Dual gate oxide device integration
US7732872B2 (en) * 2007-10-25 2010-06-08 International Business Machines Corporation Integration scheme for multiple metal gate work function structures
US8030709B2 (en) * 2007-12-12 2011-10-04 International Business Machines Corporation Metal gate stack and semiconductor gate stack for CMOS devices
US8945675B2 (en) 2008-05-29 2015-02-03 Asm International N.V. Methods for forming conductive titanium oxide thin films
JP2010010224A (ja) * 2008-06-24 2010-01-14 Panasonic Corp 半導体装置及びその製造方法
US20100038715A1 (en) * 2008-08-18 2010-02-18 International Business Machines Corporation Thin body silicon-on-insulator transistor with borderless self-aligned contacts
KR101603500B1 (ko) * 2008-12-10 2016-03-15 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR101161667B1 (ko) * 2008-12-30 2012-07-03 에스케이하이닉스 주식회사 반도체 소자의 금속배선 및 그 형성방법
US8557702B2 (en) * 2009-02-02 2013-10-15 Asm America, Inc. Plasma-enhanced atomic layers deposition of conductive material over dielectric layers
JP2011009329A (ja) * 2009-06-24 2011-01-13 Panasonic Corp 半導体装置およびその製造方法
US8441071B2 (en) 2010-01-05 2013-05-14 International Business Machines Corporation Body contacted transistor with reduced parasitic capacitance
KR101656444B1 (ko) 2010-01-25 2016-09-09 삼성전자주식회사 상보형 ｍｏｓ 트랜지스터, 상기 상보형 ｍｏｓ 트랜지스터를 포함하는 반도체 장치, 및 상기 반도체 장치를 포함하는 반도체 모듈
US8435878B2 (en) 2010-04-06 2013-05-07 International Business Machines Corporation Field effect transistor device and fabrication
KR20120030710A (ko) 2010-09-20 2012-03-29 삼성전자주식회사 게이트 구조물, 그 형성 방법 및 이를 포함하는 반도체 소자의 제조 방법
KR101853316B1 (ko) 2012-03-29 2018-04-30 삼성전자주식회사 반도체 소자
US9540729B1 (en) 2015-08-25 2017-01-10 Asm Ip Holding B.V. Deposition of titanium nanolaminates for use in integrated circuit fabrication
US9523148B1 (en) 2015-08-25 2016-12-20 Asm Ip Holdings B.V. Process for deposition of titanium oxynitride for use in integrated circuit fabrication

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045053A (ja) 1983-08-22 1985-03-11 Mitsubishi Electric Corp 半導体装置
US4974056A (en) * 1987-05-22 1990-11-27 International Business Machines Corporation Stacked metal silicide gate structure with barrier
JPH06151828A (ja) * 1992-10-30 1994-05-31 Toshiba Corp 半導体装置及びその製造方法
JP2536413B2 (ja) * 1993-06-28 1996-09-18 日本電気株式会社 半導体集積回路装置の製造方法
EP0637073A1 (en) * 1993-07-29 1995-02-01 STMicroelectronics S.r.l. Process for realizing low threshold P-channel MOS transistors for complementary devices (CMOS)
US5576579A (en) * 1995-01-12 1996-11-19 International Business Machines Corporation Tasin oxygen diffusion barrier in multilayer structures
US5942786A (en) * 1996-02-01 1999-08-24 United Microelectronics Corp. Variable work function transistor high density mask ROM
US6028339A (en) * 1996-08-29 2000-02-22 International Business Machines Corporation Dual work function CMOS device
US5923999A (en) * 1996-10-29 1999-07-13 International Business Machines Corporation Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device
US6084279A (en) 1997-03-31 2000-07-04 Motorola Inc. Semiconductor device having a metal containing layer overlying a gate dielectric
US5846871A (en) * 1997-08-26 1998-12-08 Lucent Technologies Inc. Integrated circuit fabrication
US6261887B1 (en) 1997-08-28 2001-07-17 Texas Instruments Incorporated Transistors with independently formed gate structures and method
KR19990051182A (ko) * 1997-12-19 1999-07-05 윤종용 폴리실리콘 저항 소자 및 그 형성 방법
US6087225A (en) * 1998-02-05 2000-07-11 International Business Machines Corporation Method for dual gate oxide dual workfunction CMOS
JP3025478B2 (ja) 1998-07-13 2000-03-27 松下電器産業株式会社 半導体装置およびその製造方法
US6204103B1 (en) 1998-09-18 2001-03-20 Intel Corporation Process to make complementary silicide metal gates for CMOS technology
US6140688A (en) * 1998-09-21 2000-10-31 Advanced Micro Devices Inc. Semiconductor device with self-aligned metal-containing gate
US6066533A (en) 1998-09-29 2000-05-23 Advanced Micro Devices, Inc. MOS transistor with dual metal gate structure
DE19845066C2 (de) * 1998-09-30 2000-08-03 Siemens Ag Integrierte Schaltungsanordnung und Verfahren zu deren Herstellung
US20020008257A1 (en) 1998-09-30 2002-01-24 John P. Barnak Mosfet gate electrodes having performance tuned work functions and methods of making same
US6137145A (en) * 1999-01-26 2000-10-24 Advanced Micro Devices, Inc. Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon
US6291282B1 (en) 1999-02-26 2001-09-18 Texas Instruments Incorporated Method of forming dual metal gate structures or CMOS devices
US6492688B1 (en) * 1999-03-02 2002-12-10 Siemens Aktiengesellschaft Dual work function CMOS device
US6168997B1 (en) * 1999-04-26 2001-01-02 Vanguard International Semiconductor Corporation Method of forming poly gate and polycide gate with equal height
US6281064B1 (en) * 1999-06-04 2001-08-28 International Business Machines Corporation Method for providing dual work function doping and protective insulating cap
US6174775B1 (en) * 1999-06-25 2001-01-16 Taiwan Semiconductor Manufacturing Company Method for making a dual gate structure for CMOS device
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6373111B1 (en) * 1999-11-30 2002-04-16 Intel Corporation Work function tuning for MOSFET gate electrodes
US6383879B1 (en) * 1999-12-03 2002-05-07 Agere Systems Guardian Corp. Semiconductor device having a metal gate with a work function compatible with a semiconductor device
US6355561B1 (en) * 2000-11-21 2002-03-12 Micron Technology, Inc. ALD method to improve surface coverage

Also Published As

Publication number Publication date
AU2002254726A1 (en) 2002-12-09
CN1520613A (zh) 2004-08-11
KR100867565B1 (ko) 2008-11-10
KR20040004657A (ko) 2004-01-13
EP1396024A2 (en) 2004-03-10
JP2006523008A (ja) 2006-10-05
US6518106B2 (en) 2003-02-11
WO2002097889A3 (en) 2003-05-01
TW557475B (en) 2003-10-11
US20020175384A1 (en) 2002-11-28
WO2002097889B1 (en) 2003-07-03
WO2002097889A2 (en) 2002-12-05

Similar Documents

Publication Publication Date Title
CN1288755C (zh) 半导体装置和形成半导体装置的方法
US7709331B2 (en) Dual gate oxide device integration
KR100529202B1 (ko) 이중 금속 게이트 ｃｍｏｓ 장치 및 그 제조 방법
CN101427386B (zh) 阻挡层的选择性实施以实现在具有高k电介质的CMOS器件制造中的阈值电压控制
CN102388451B (zh) 形成半导体器件的方法
US20090020792A1 (en) Isolated tri-gate transistor fabricated on bulk substrate
CN1717798A (zh) 新型场效应晶体管和制造方法
CN102203924A (zh) 具有设计的Ge分布和优化硅帽盖层的优化压缩SiGe沟道PMOS晶体管
CN101840863A (zh) 半导体装置及半导体装置的制造方法
KR20110095456A (ko) 트랜지스터 및 그 제조 방법
DE102009021484B4 (de) Höhere Gleichmäßigkeit einer Kanalhalbleiterlegierung durch Herstellen von STI-Strukturen nach dem Aufwachsprozess
US7253485B2 (en) Semiconductor device and manufacturing method thereof
CN101770987B (zh) 半导体集成电路装置的制造方法
US6998303B2 (en) Manufacture method for semiconductor device with patterned film of ZrO2 or the like
US7067434B2 (en) Hydrogen free integration of high-k gate dielectrics
US8629028B2 (en) Metal oxide semiconductor field effect transistor (MOSFET) gate termination
JP2001230247A (ja) 半導体装置の製造方法及び該方法により製造された半導体装置
US7129563B2 (en) Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material
US20050136580A1 (en) Hydrogen free formation of gate electrodes
KR870010636A (ko) 낮은 농도로 도핑된 드레인 터미날지역을 가지는 m0s-트랜지스터의 게이트 전극에 측벽마스크층을 제조하기 위한 공정과 이 공정을 사용하여 상보형 mos-트랜지스터를 제조하는 방법
CN113594094B (zh) 存储器及其制备方法
US20070205472A1 (en) Formation of a disposable spacer to post dope a gate conductor
JPH0629315A (ja) 半導体装置及び半導体装置の製造方法
CN117613007A (zh) 一种半导体结构的制备方法
KR20080106797A (ko) 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: FREESCALE SEMICONDUCTOR INC.

Free format text: FORMER OWNER: MOTOROLA, INC.

Effective date: 20041224

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20041224

Address after: texas

Applicant after: Fisical Semiconductor Inc.

Address before: Illinois

Applicant before: Motorola Inc.

C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: texas

Patentee after: NXP America Co Ltd

Address before: texas

Patentee before: Fisical Semiconductor Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20061206

Termination date: 20190424