CN1263161C - 硅/锗硅垂直结型场效应晶体管及其制造方法 - Google Patents

硅/锗硅垂直结型场效应晶体管及其制造方法 Download PDF

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CN1263161C
CN1263161C CNB981042503A CN98104250A CN1263161C CN 1263161 C CN1263161 C CN 1263161C CN B981042503 A CNB981042503 A CN B981042503A CN 98104250 A CN98104250 A CN 98104250A CN 1263161 C CN1263161 C CN 1263161C
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K·E·伊斯迈尔
B·S·梅耶尔森
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Abstract

描述了一种结型场效应管及其制作方法，包括窗口中的水平半导体层以形成沟道和其中开有窗口的半导体层，它形成环绕沟道的栅电极。水平半导体层可以是在源和漏附近具有渐变组分的SiGe合金。本发明克服了形成JFET低电阻的问题，提供了很容易降到亚微米尺寸的栅长以便用于RF、微波、毫米波和逻辑电路而没有短沟道效应。

Description

硅/锗硅垂直结型场效应晶体管及其制造方法
发明领域
本发明涉及结型场效应晶体管，更具体地涉及带有渐变SiGe合金的垂直沟道的结型场效应晶体管，渐变的SiGe合金为增大迁移率而提供应变，并在沟道的源端提供了一感应电场以加速载流子进入沟道。
技术背景
在标准的金属-氧化物-硅(MOS)工艺中，场效应管速度的增强通常伴随着四件尺寸的缩小。然而，当晶体管的栅长小于0.1微米或更小时，由于不能按比例小其它各种参数，存在尺寸极限。短沟道效应变得很重要，而且导致载流子(电子)以低的速度在沟道的源端移动的惯性(inertial)效应也变得很重要。
在1991年5月28日授予P.M.Solomon的美国专利5,019,882中描述了含有用作沟道的硅锗层的一种场效应晶体管。
已经公开了使用渐变的SiGe区以增强双极器件中的载流子加速，如1990年8月21日授予D.L.Harame等的美国专利4,951,115和1994年10月4日授予E.F.Crabbe等的美国专利5,359,912，它被转让给本申请的受让人。
已公开渐变SiGe和应变Si和SiGe层以在MOSFET器件中增强迁移率，如K.E.Ismail和F.Sern的美国专利5,534,713中所述，它已部分转让给本申请的受让人。
1994年11月22日授予A.Chantre的美国专利5,367,184中描述了具有优化的双极工作模式的垂直JFET的改进结构。为增强双极工作，提供了SiGe薄层以在n沟道中提供价带不连续性。该薄层从栅区延伸进入沟道区以从栅(基)区注入少数载流子(空穴)，垂直JFET工作不需要该SiGe薄层。
发明内容
根据本发明，公开了一种结型场效应晶体管及其制作方法，包括：第一类型的第一半导体层；形成在第一半导体层上轻掺杂的第一类型的第二半导体层；形成在第二半导体层上的第三半导体层，其上开有窗口，露出一部分第二半导体层；形成在第三半导体层上的介质材料层，其上开有和第三半导体层相通的窗口；Si1-xGex的第一类型的第四半导体层，具有一定厚度，形成在第三半导体层的窗口中的第二半导体层上；Si(1-y)Gey的第一类型的第五半导体层，y值设定在约0.1到约0.3的范围内，它形成在第三半导体层的开口中的第四半导体层上；Si(1-z)Gez的第一类型的第六半导体层，其有一定厚度，形成在介质材料层的开口中的第五半导体层上。第一和第二类型的半导体可以分别为n和p或p和n。
在上述结型场效应晶体管中，优选地，上述第四半导体层中的x为0至0.1；上述第五半导体层中的y优选地等于0.15；或者上述第六半导体层的z为0.15降低至0。
本发明提供了一种用于大规模集成(LSI)的结型场效应晶体管，其沟道长度为0.1微米量级或更小，这基于硅工艺，它能工作在用于卫星、无线广域网络和通讯设备的微波和毫米波频带。
本发明还提供了一种结型场效应晶体管结构，其中栅与源自对准。
本发明还提供了一种结型场效应晶体管结构，其中删长可轻易地降到0.1微米以下，并不受短沟道或惯性效应的影响。
本发明还提供了一种结型场效应晶体管结构，其中沟道本身由应变SiGe制成，这样轻电子有效质量易于在垂直方向输运。
本发明还提供了一种结型场效应晶体管结构，其中沟道的源侧的SiGe梯度提供了一电场以加速载流子或以高速将载流子(电子)注入沟道。
本发明还提供了一种结型场效应晶体管结构，其中沟道的漏侧的SiGe梯度降低了电场并因此增大了击穿电压和器件的可靠性，改善了饱和电流并因此增加了晶体管的增益。
本发明还提供了一种结型场效应晶体管结构，其中串联的源漏电阻可以极低，因为不需离子注入和退火即可生长高掺杂的外延层。
本发明还提供了适于体硅的体材料衬底和/或绝缘体上的硅(SOI)衬底的结型场效应晶体管结构。
本发明还提供了适于高速大规模集成(LSI)逻辑的一种结型场效应晶体管结构。
本发明还提供了一种制作垂直结型场效应晶体管的工艺，当外延层用超高真空化学汽相淀积(UHV-CVD)生长时，它不需要离子注入或任何560℃以上的高温步骤。
本发明的这些和其它特点、目的和优点参照本发明的详细描述和附图将变得很明显。
附图说明
图1-3是说明实现本发明一个实施例的制造步骤的剖面图；
图4是图2的顶视图；
图5是图3的顶视图；
图6是图3一部分的放大的剖视图；
图7是带有电极接触的图3实施例的剖视图的三维视图；
图8是图7的顶视图。
具体实施方式
现参照附图，尤其是图1-3，显示了制作垂直结型场效应晶体管(JFET)10的步骤。起始衬底12可以是如二氧化硅的绝缘体，或衬底12可以是如单晶硅、锗硅或绝缘体上的硅的半导体。在衬底12上可形成掺p-的半导体单晶层14，如硅或锗硅。起始衬底12，如果是绝缘体，和层14可以通过注氧隔离(SIMOX)形成，这在本领域中公知的，或通过链合和深刻蚀涂有氧化物的晶片和半导体载体衬底以形成绝缘体上的硅(BESOI)而形成。层14可以是重掺杂的n+层以形成图3所示的JFET10的漏电极15。
外延层16形成在层14上，它可以是掺杂的n-层以降低随后外延形成在层16上的栅层18的电容。栅层18可以是，例如Si或SiGe，p+掺杂，厚度在30-100nm之间。然后，如二氧化硅的介质层20形成在层18上，用以降低随后形成在其上的源电极21的电容。
Si或SiGe外延层的生长温度可在500-560℃之间，如果用超高真空化学汽相淀积(UHV-CVD)生长JFET10，如1994年3月24日授予B.S.Meyerson的美国专利5,298,452中所述，这将是最高的温度，该专利已转让给这里的受让人，亦在此引入作为参考。然而，该外延层不只限于UHV-CVD，也可以在700-800℃范围内用低压外延(LPE)生长。
其次，利用例如刻蚀在层20上开例如1×1μm的窗口24。然后，例如通过反应离子刻蚀(RIE)，窗口24延伸通过栅层18，它可以选择性地终止于层16。如果层18是SiGe合金，层16是Si，则在RIE过程中折射率的变化可用于停止刻蚀，如果层16被曝光。窗口24的顶视图示于图4。
1995年3月7日授予M.Aerienzo等的美国专利5,395,769中描述了一种控制硅刻蚀深度的方法，它可将刻蚀终止于合适的深度，其在这里引入作为参考。
然后，SiGe的外延渐变层30在层16上的窗口24中生长。Si(1-x)Gex的渐变层30可以n-掺杂，x在层16中可以为0并作为层厚的函数变化，在上表面31处为0.1。然后在层16上生长Si1-yGey外延层34，这里y是常数，设定在约0.1到约0.3的范围内，优选地等于约0.15。层34形成JFET10的沟道36的中心部分。然后，在层34的上表面37上生长Si(1-z)Gez的渐变外延层38，这里z为层厚的函数，在表面37处为约0.15，在层38的上表面39处为0。
层30和38中的Ge浓度分布和层34中Ge含量的选择由层14和16的晶格失配决定。JFET10中所需的层30、34和38的厚度与浓度分布将导致整个应变层30、34和38，而不产生错位以释放应变。
如果第一类型是p型，第二类型是n型则沟道36是p型。层30和38仍需以相同方式渐变。在所有方向都有应变。所谓压应变，通常是指在较小的晶格上生长较大的晶格，这样它的平面内(in-plane)晶格常数被压缩以调节下面的层晶格常数。然而，这样做使得，长在上面的层的晶格在平面内经受压应变，在垂直方向(如图6中箭头50所指的电流方向)经受拉伸应变。
层30、34和38的外延淀积或生长对层30、34和38是优选的或选择性的，在介质层20上没有诸如硅氧化物的晶核发生。其它适于作掩蔽层的氧化物在1995年6月27日授予C.Cabral，Jr等的美国专利5,427,630中有描述，它已转让给本申请受让人，并在此引入作为参考。
然后，例如Si的导电材料层44淀积在层38和介质层20上，随后如图3、5、6所示进行构图。层44可以n++重掺杂，用于提供JFET10的源电极21。
底层14和顶层44分别构成JFET10的漏电极15和源电极21。P型层18构成JFET10的栅电极19，从全部四个侧边整个包围导电沟道36。因此栅电极19对电荷载流子有很好的控制，不可能产生短沟道效应。由于栅电极19围绕沟道36的全部侧边，JFET10的调制效率被优化。然而JFET10将在沟道36的两边用栅电极19工作。
SiGe层38中渐次变化的Ge含量z和Ge含量y的选择，使得在沟道36的源侧感应出电场，它加速电子并以高速将它们送到沟道36中，因此避免了惯性效应。沟道36本身是应变SiGe，因此轻电子有效质量易于在图6中箭头50所示的垂直方向输运。在沟道36的漏侧处SiGe层30的Ge的梯度x降低了电场，因此增加了击穿电压和器件的可靠性，并改进了电流饱和度因此提高了晶体管的增益。在制造和操作JFET10时只在源侧或只在漏侧部分渐变Ge是可行的。
由于栅长由p型层18的厚度决定，层18的厚度可以很容易降到0.1微米以下的尺寸，例如从0.1μm或100nm至30nm，精度约1nm。
P型层18的厚度或栅长可以从几个nm如5nm到几百nm。给出优化的范围30至100nm，主要原因是层18做得很薄，p层18的电阻较高，因此可以降低如栅的RC时间常数。短至5nm的栅长也是可行的。
由于不需要离子注入和退火即可生长高掺杂处延层，串联的源漏电阻可以极低。使用例如用SIMOX工艺制作的SOI晶片，在p型层18下增加轻掺杂n-层16和在p型层18上加介质层20，使突生电容最小化。栅层18下面的n-层16有益于制作器件的电接触。如图3、6、7所示的JFET10的本征开关时间在栅长为50nm时小于1ps。
参考图6、7、8，可在构图的层44和介质层20上形成介质层52。通过刻蚀暴露出栅电极19，源电极21和漏电极15，在介质层52上开窗口53-55。如图7和8所示，可以淀积金属层或外延生长高掺杂多晶Si或Si/SiGe层并构图作为互连线56-58。如果互连线56-58为金属，到硅的接触可通过在400℃下金属烧结(sintering)1至5分钟形成。栅电极19和漏电极15也可分别用高掺杂的n型层14和p型层18形成，作为由反应离子刻蚀限定的互连线。JFET10可用于RF、微波或毫米波放大器电路以及高速LSI逻辑电路。
虽然已经描述和说明了一种含有栅的垂直结型场效应晶体管，该栅完全围绕沟道且栅长小至几十纳米，对本领域技术人员而言，可以做各种改进和变化而不背离本发明的范围，本发明的范围只由后面的权利要求书限定。

Claims (20)

1.一种结型场效应晶体管，包括：
第一导电类型的第一半导体层；
在第一半导体层上形成的轻掺杂第一导电类型的第二半导体层；
形成在第二半导体层上、其中开有窗口以暴露部分所述第二半导体层的第二导电类型的第三半导体层；
特征在于，还包括：
形成在所述第三半导体层上的介质材料层，其中开有与第三半导体层中的窗口相通的窗口；
Si1-xGex的第一导电类型的第四半导体层，它形成在所述第三半导体层的所述窗口中的第一半导体层上，其中x随厚度而增加；
形成在所述第三半导体层的所述窗口中第四半导体层上的、Si1-yGey的第一导电类型的第五半导体层，其中y是常数；和
形成在所述介质材料层的所述窗口中第五半导体层上的、Si1-zGez的第一导电类型的第六半导体层，其中z随厚度减少。
2.根据权利要求1的结型场效应晶体管，特征在于还包括在所述第一半导体层下的绝缘衬底。
3.根据权利要求1的结构场效应晶体管，特征在于还包括形成在所述介质材料层和所述第六半导体层上的第一导电类型的硅的第七半导体层。
4.根据权利要求1的结型场效应晶体管，特征在于所述第一导电类型是n型，第二导电类型是p型。
5.根据权利要求1的结型场效应晶体管，特征在于所述第一导电类型是p型，第二导电类型是n型。
6.根据权利要求1的结型场效应晶体管，特征在于所述第三半导体层形成栅电极。
7.根据权利要求6的结型场效应晶体管，特征在于，所述第三半导体层的厚度在30至100nm之间。
8.根据权利要求6的结型场效应晶体管，特征在于所述第三半导体层的厚度决定了所述晶体管的沟道长度。
9.根据权利要求1的结型场效应晶体管，特征在于，所述第五半导体层是应变的，使得利于在所述第五半导体层中完成横穿所述第三半导体层的轻电子有效质量的输运。
10.根据权利要求1的结型场效应晶体管，特征在于，所述第五半导体层是在所述第三半导体层和所述介质材料之间的界面上延伸的所述窗口中。
11.根据权利要求1的结型场效应晶体管，特征在于上述第四半导体层中的x从0增加到0.1。
12.根据权利要求1的结型场效应晶体管，特征在于，y在从约0.1到约0.3的范围内。
13.根据权利要求1的结型场效应晶体管，特征在于上述第六半导体层中的z从0.15降到0。
14.一种制备结型场效应晶体管的方法，包括以下步骤：
形成第一导电类型的第一半导体层；
在所述第一半导体层上形成轻掺杂的第一导电类型的第二半导体层‘
在所述第二半导体层上形成第二导电类型的所述第三半导体层，其中开有窗口以暴露部分所述第二半导体层；
特征在于还包括以下步骤：
在所述第三半导体层上形成介质材料层，其中开有与所述第三半导体层中的窗口相通的窗口；
在所述第三半导体层的所述窗口中的第二半导体层上形成Si1-xGex的第一导电类型的第四半导体层，其中x随厚度增加；
在所述第三半导体层的所述窗口中的第四半导体层上形成Si1-yGey的第一导电类型的第五半导体层，其中y是常数；
在所述介质材料层的所述窗口中的第五半导体层上形成Si1-zGez的第一导电类型的第六半导体层，其中z随厚度而减少。
15.根据权利要求14的方法，特征在于还包括在介质材料层和所述第六半导体层上形成硅的第一导电类型的第七半导体层的步骤。
16.根据权利要求14的方法，特征在于在形成所述第四半导体层的步骤中使所述SiGe结构中Ge组分是渐变的，由此所述第五半导体层是应变的，使得有利于在所述第五半导体层中完成横穿所述第三半导体层的轻电子有效质量的输运。
17.根据权利要求14的方法，特征在于还包括下列步骤：在所述第六半导体层使SiGe中形成渐变的Ge组分，由此产生感应电场以加速载流子并以高速将载流子送入所述第五半导体层。
18.根据权利要求14的方法，特征在于在形成第五半导体层的所述步骤中，y值设定在约0.1到约0.3的范围内。
19.根据权利要求14的方法，特征在于在形成第四半导体层的步骤中使上述第四半导体层中的x从0增加到0.1。
20.根据权利要求14的方法，特征在于在形成第六半导体层的步骤中使上述第六半导体层中的z从0.15降到0。
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