CN1255739A - 形成具有多晶硅-硅化钛结构的栅极的方法 - Google Patents
形成具有多晶硅-硅化钛结构的栅极的方法 Download PDFInfo
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
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Abstract
本发明提供了一种在栅极的再氧化工序中防止栅极异常氧化,同时,可以减小栅极电阻的多晶硅－硅化物结构的栅极形成方法。包括依次形成栅极氧化膜、多晶硅膜和硅化钛膜;在硅化钛膜上,按照栅极的形状,形成屏蔽绝缘膜。接着,对屏蔽绝缘膜的屏蔽层进行腐蚀,对硅化钛膜和多晶硅膜进行腐蚀,形成栅极。又利用再氧化工序,对基板进行氧化,在上述栅极的侧面和上述基板表面上,形成厚度均匀的氧化膜。
Description
本发明涉及半导体元件的制造方法，特别是涉及形成具有多晶硅-硅化钛结构的栅极的方法，在上述多晶硅-硅化钛结构中，硅化钛层形成在多晶硅层上。
一般MOS(金属氧化物半导体)晶体管的栅极是用掺杂的多晶硅膜形成的。然而，由于半导体器件的高度集成化，栅极的线宽以及其它图形都做得非常微小。最近，结构的微小化达到元件的线宽为0.15微米(μm)以下的程度。与此相适应，通常作为栅极材料使用的掺杂的多晶硅，由于其比电阻特性高，延迟时间长，因此，对于要求快速动作的元件，难以适用。这个问题，随着半导体器件的高度集成化成为一个深刻的问题。因此，对于1GDRAM以上的半导体元件，主要采用由多晶硅膜和硅化钛膜层叠结构组成的多晶硅-硅化钛结构的栅极。
图1A至图1E为说明先前的多晶硅-硅化钛结构的栅极形成方法的截面图。
参见图1A，在半导体基底11上，用热生长方式或蒸镀方式，形成栅极氧化膜12，在该栅极氧化膜12上，再形成掺杂的多晶硅膜13。其次，如图1B所示，在多晶硅膜13上，使用硅化钛靶(TiSix)，采用物理气相沉积(PVD)法，蒸镀一层非晶体的硅化钛。(TiSix)膜14。然后，如图1C所示，在给定温度下，进行数秒钟的快速热处理(RTP)，使非晶相的硅化钛膜14相变(phasetransformation)为晶相的硅化钛膜14a。
再参见图1D，为了进行通常的自调整接触(SAC：self-aligned contact)工序等后续工序，在TiSi2膜14a上，按照栅极的形状，形成一个屏蔽绝缘膜15。这里，屏蔽绝缘膜15是用氧化膜或氮化膜制成的。接着，对屏蔽绝缘膜15的屏蔽层进行腐蚀，并对TiSi2膜14a和多晶硅膜13进行腐蚀，形成栅极100。
再参见图1E，为了除去腐蚀造成的损伤，并提高栅极氧化膜12的可靠性，要利用再氧化工序，对图1D的结构进行氧化，在栅极100的侧面和基底11的表面上，形成氧化膜16。这里，再氧化工序一般是在800℃以上的温度下，通过热氧化工序进行的。
但是，在进行上述再氧化工序时，由于TiSi2膜14a的快速氧化，栅极100的硅化钛(TiSi2)膜14a的侧面会过度氧化；这样，形成栅极100的TiSi2膜14a的线宽减少，栅极100的形态变形，如图1E所示。由于这样，难以进行用以形成源极和漏极的注入杂质离子的工序，而且栅极100电阻增加，结果，使元件的可靠性降低。
因此，本发明的目的是要提供一种在栅极再氧化工序时，可防止栅极的异常氧化，同时可以减少栅极电阻的多晶硅-硅化钛结构(titanium polycidestructure)的栅极的形成方法。
为了达到本发明的上述目的，本发明在半导体基底上，依次形成栅极氧化膜，多晶硅膜和硅化钛膜；在上述TiSi2膜上，按照栅极的形状，形成屏蔽绝缘膜；以上述屏蔽绝缘膜作为蚀刻掩模，对上述TiSi2膜和多晶硅膜进行腐蚀，形成栅极；和利用再氧化工序，对上述基板进行氧化，在上述栅极的侧面和上述基板表面上，形成厚度均匀的氧化膜；上述再氧化工序，是在750℃以下的温度下，利用在干燥气氛下进行氧化的方法进行的。
另外，再氧化工序是在700℃～750℃的温度下进行的，氧化膜的膜厚为30埃～60埃，最好为50埃。
通过以下结合附图对优选实施例的详细描述，本发明的上述以及其它目的、特点会更明显。附图中：
图1A～图.1E为用于说明现有技术的多晶硅-硅化钛结构的栅极形成方法的截面图；
图2A～图2E为用于说明本发明实施例的多晶硅-硅化钛结构的栅极形成方法的截面图；
图3为表示多晶硅膜和硅化钛(TiSi2)膜的氧化速度与温度的倒数(1/T)的关系的图。
以下，根据附图来详细说明本发明的优选实施例。
图2A～图2E为用于说明根据本发明的实施例的多晶硅-硅化钛结构的栅极形成方法的截面图。
参见图2A，在半导体基底21上，用热成长方式或蒸镀方式形成栅极氧化膜22，在栅极氧化膜22上，再蒸镀形成掺杂的多晶硅膜23。其次，如图2B所示，在多晶硅膜23上，采用使用硅化钛(TiSix)靶的物理气相沉积(PVD)法，蒸镀形成非晶相的硅化钛(TiSix)膜24。接着，如图2C所示，在给定温度下，在数秒钟内进行快速热处理(RTP)，将非晶体的TiSix膜24相变为晶相的硅化钛(TiSi2)膜24a。
再参见图2D，为了进行通常的自调整接触(SAC)工序等后续工序，在TiSi2膜24a上，按照栅极的形态，形成屏蔽绝缘膜25。这里，屏蔽绝缘膜25是由氧化膜或氮化膜或者氧化膜与氮化膜的复合膜形成的。其次，以屏蔽绝缘膜25作为蚀刻掩模，对TiSi2膜24a和多晶硅膜23进行腐蚀，形成栅极200。
又参见图2E，为了除去由蚀刻工艺造成的损伤，并恢复栅极氧化膜22的可靠性，通过再氧化工序，对图2D的结构再进行氧化，在栅极200的侧面和基底21的表面上形成氧化膜26。这里，为了使氧化膜26的厚度均匀，应在TiSi2膜24a和多晶硅膜23的氧化速度一致的温度范围内，进行再氧化工序。
例如，分别在700℃，750℃，800℃，850℃的温度下进行再氧化工序的实验结果显示，在800℃和850℃下，TiSi2膜24a的氧化速度比多晶硅膜23的氧化速度高。因此，如现有技术(参见图1E)那样，会发生TiSi2膜24a的侧面氧化过度的现象。另一方面，如图2E所示，在700℃和750℃下TiSi2膜24a和多晶硅膜23的氧化速度大致是一致的，因此，在栅极200的侧面上，可以形成厚度均匀的氧化膜26，如图2E所示。
图3为表示由上述实验得出的多晶硅膜23和TiSi2膜24a的氧化速度，与温度的倒数(1/T)的关系的图。如图3所示，当温度增加时，TiSi2膜的氧化速度也增加；而在750℃以下，多晶硅膜23和TiSi2膜24a的氧化速度大致是一致的。但是，在700℃以下，氧化速度太慢，工序时间长。因此，再氧化工序最好在700℃～750℃温度下进行。
另外，分别在700℃，750℃，800℃的温度下，利用在潮湿气氛下进行氧化的方法，进行再氧化工序的另一实验结果显示，在700℃和750℃下，在图2E所示的多晶硅膜23和TiSi2膜24a的侧面上，都能形成比较均匀的氧化膜26。相反，在800℃温度下，TiSi2膜24a的氧化速度快，因此，会发生如现有技术(参见图1E)那样的、TiSi2膜24a的侧面氧化过度的现象。但是，与在干燥气氛下进行的氧化比较，由于在潮湿气氛下进行氧化时的氧化均匀性差、氧化速度快，因此，再氧化工序最好采取在干燥的气氖下氧化的方法进行。
根据上述实验结果可知，再氧化工序最好是在700℃～750℃下，利用在干燥的气氛下进行氧化的方法进行，这样可形成厚度均匀的氧化膜26。另外，氧化膜26的膜厚为30(埃)～60埃，最好为50埃。
根据本发明，通过在TiSi2膜和多晶硅膜的氧化速度一致的温度范围内，利用在干燥气氛下进行氧化的方法进行再氧化工序，可以防止TiSi2膜的过度氧化。与此相适应，可以防止栅极的异常氧化，用于形成源极和漏极的注入杂质离子的工序容易进行，栅极电阻可以减小。结果，可以提高元件的可靠性。
本发明不是仅限于上述实施例。在不偏离本发明精神的范围内，可以作各种改变。
Claims (7)
1.一种形成具有多晶硅-硅化物结构的栅极的方法，该方法包括下列步骤：
在半导体基底上，依次形成栅极氧化膜，多晶硅膜和硅化钛膜；
在上述TiSi2膜上，按照栅极的形状，形成屏蔽绝缘膜；
以上述屏蔽绝缘膜作为蚀刻掩模，对上述TiSi2膜和多晶硅膜进行腐蚀，形成栅极；和
利用再氧化工序，对上述基板进行氧化，在上述栅极的侧面和上述基板表面上，形成厚度均匀的氧化膜；其特征为，上述再氧化工序，是在750℃以下的温度下，利用在干燥气氛下进行氧化的方法进行的。
2.如权利要求1所述的方法，其特征为，上述再氧化工序是在700℃～750℃温度下进行的。
3.如权利要求1所述的方法，其特征为，上述氧化膜的膜厚为30埃～60埃。
4.如权利要求3所述的方法，其特征为，上述氧化膜的膜厚大致为50埃。
5.如权利要求1所述的方法，其特征为，形成上述硅化钛膜的步骤包括：在上述多晶硅膜上，沉积一层非晶相的硅化钛膜的步骤；和对上述非晶相的硅化钛膜进行热处理，使该硅化钛膜相变为晶相的硅化钛膜的步骤。
6.如权利要求5所述的方法，其特征为，上述非晶相的硅化钛膜，是用物理气相沉积方式沉积形成的。
7.如权利要求5所述的方法，其特征为，上述热处理是利用快速热处理工序进行的。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR51104/1998 | 1998-11-26 | ||
| KR1019980051104A KR100291512B1 (ko) | 1998-11-26 | 1998-11-26 | 반도체 소자의 게이트 전극 형성방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1255739A true CN1255739A (zh) | 2000-06-07 |
| CN1161822C CN1161822C (zh) | 2004-08-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991248996A Expired - Fee Related CN1161822C (zh) | 1998-11-26 | 1999-11-26 | 形成具有多晶硅-硅化钛结构的栅极的方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6255206B1 (zh) |
| JP (1) | JP3605718B2 (zh) |
| KR (1) | KR100291512B1 (zh) |
| CN (1) | CN1161822C (zh) |
| DE (1) | DE19956987B4 (zh) |
| GB (1) | GB2344216B (zh) |
| TW (1) | TW425638B (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100440441C (zh) * | 2005-06-30 | 2008-12-03 | 海力士半导体有限公司 | 用于制作具有栅的半导体器件的方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3875077B2 (ja) * | 2001-11-16 | 2007-01-31 | 富士通株式会社 | 電子デバイス及びデバイス接続方法 |
| DE10214126A1 (de) * | 2002-03-28 | 2003-10-23 | Infineon Technologies Ag | Herstellungsverfahren für eine Mehrzahl von ungefähr gleich hohen und gleich beabstandeten Gatestapeln auf einem Halbleitersubstrat |
| KR100486294B1 (ko) * | 2002-12-30 | 2005-04-29 | 삼성전자주식회사 | 게이트 패턴을 갖는 반도체소자의 제조방법 |
| KR100460069B1 (ko) * | 2003-04-14 | 2004-12-04 | 주식회사 하이닉스반도체 | 반도체소자의 게이트전극 형성방법 |
| TW200501317A (en) * | 2003-06-17 | 2005-01-01 | Promos Technologies Inc | Method of forming a contact hole and method of forming a semiconductor device |
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| JPS62145859A (ja) | 1985-12-20 | 1987-06-29 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US5268321A (en) | 1985-12-20 | 1993-12-07 | Mitsubishi Denki Kabushiki Kaisha | Method of making DRAM cell having improved radiation protection |
| JPH0258874A (ja) | 1988-08-24 | 1990-02-28 | Nec Corp | 半導体集積回路装置 |
| JP2558931B2 (ja) | 1990-07-13 | 1996-11-27 | 株式会社東芝 | 半導体装置およびその製造方法 |
| US5130266A (en) | 1990-08-28 | 1992-07-14 | United Microelectronics Corporation | Polycide gate MOSFET process for integrated circuits |
| DE69211329T2 (de) * | 1992-03-27 | 1996-11-28 | Ibm | Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur |
| JP2630292B2 (ja) | 1995-02-27 | 1997-07-16 | 日本電気株式会社 | 半導体装置の製造方法 |
| JP3631279B2 (ja) | 1995-03-14 | 2005-03-23 | 富士通株式会社 | 半導体装置の製造方法 |
| JP3714995B2 (ja) | 1995-07-05 | 2005-11-09 | シャープ株式会社 | 半導体装置 |
| JPH09162409A (ja) | 1995-12-06 | 1997-06-20 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法と液晶表示装置の製造方法 |
| JPH09199614A (ja) | 1996-01-23 | 1997-07-31 | Sony Corp | 半導体記憶装置及びその製造方法 |
| US5672544A (en) | 1996-04-22 | 1997-09-30 | Pan; Yang | Method for reducing silicided poly gate resistance for very small transistors |
| JPH09293864A (ja) | 1996-04-26 | 1997-11-11 | Sony Corp | 半導体装置の製造方法および半導体装置 |
| US5648287A (en) | 1996-10-11 | 1997-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of salicidation for deep quarter micron LDD MOSFET devices |
| KR100190105B1 (ko) | 1996-10-24 | 1999-07-01 | 윤종용 | 게이트전극의 제조방법 및 그에 따라 제조된 게이트구조 |
| TW322608B (en) | 1997-07-31 | 1997-12-11 | United Microelectronics Corp | Manufacturing method of self-aligned salicide |
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| US5994192A (en) * | 1998-05-29 | 1999-11-30 | Vanguard International Semiconductor Corporation | Compensation of the channel region critical dimension, after polycide gate, lightly doped source and drain oxidation procedure |
| KR100294637B1 (ko) * | 1998-06-29 | 2001-10-19 | 박종섭 | 모스펫의폴리사이드게이트형성방법 |
-
1998
- 1998-11-26 KR KR1019980051104A patent/KR100291512B1/ko not_active IP Right Cessation
-
1999
- 1999-11-04 TW TW088119190A patent/TW425638B/zh not_active IP Right Cessation
- 1999-11-05 US US09/434,647 patent/US6255206B1/en not_active Expired - Lifetime
- 1999-11-12 JP JP32298699A patent/JP3605718B2/ja not_active Expired - Fee Related
- 1999-11-18 GB GB9927341A patent/GB2344216B/en not_active Expired - Fee Related
- 1999-11-26 DE DE19956987A patent/DE19956987B4/de not_active Expired - Fee Related
- 1999-11-26 CN CNB991248996A patent/CN1161822C/zh not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100440441C (zh) * | 2005-06-30 | 2008-12-03 | 海力士半导体有限公司 | 用于制作具有栅的半导体器件的方法 |
| US7605069B2 (en) | 2005-06-30 | 2009-10-20 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with gate |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19956987B4 (de) | 2008-10-30 |
| GB9927341D0 (en) | 2000-01-12 |
| KR100291512B1 (ko) | 2001-11-05 |
| GB2344216A (en) | 2000-05-31 |
| JP3605718B2 (ja) | 2004-12-22 |
| JP2000164871A (ja) | 2000-06-16 |
| TW425638B (en) | 2001-03-11 |
| GB2344216B (en) | 2003-09-24 |
| CN1161822C (zh) | 2004-08-11 |
| KR20000034009A (ko) | 2000-06-15 |
| DE19956987A1 (de) | 2000-05-31 |
| US6255206B1 (en) | 2001-07-03 |
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