CN1248317C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1248317C
CN1248317C CNB031475302A CN03147530A CN1248317C CN 1248317 C CN1248317 C CN 1248317C CN B031475302 A CNB031475302 A CN B031475302A CN 03147530 A CN03147530 A CN 03147530A CN 1248317 C CN1248317 C CN 1248317C
Authority
CN
China
Prior art keywords
insulating film
film
element isolation
mentioned
isolation insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB031475302A
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English (en)
Chinese (zh)
Other versions
CN1472820A (zh
Inventor
饭沼俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1472820A publication Critical patent/CN1472820A/zh
Application granted granted Critical
Publication of CN1248317C publication Critical patent/CN1248317C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CNB031475302A 2002-07-10 2003-07-09 半导体器件及其制造方法 Expired - Fee Related CN1248317C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002201127A JP2004047608A (ja) 2002-07-10 2002-07-10 半導体装置及びその製造方法
JP201127/2002 2002-07-10

Publications (2)

Publication Number Publication Date
CN1472820A CN1472820A (zh) 2004-02-04
CN1248317C true CN1248317C (zh) 2006-03-29

Family

ID=30112550

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031475302A Expired - Fee Related CN1248317C (zh) 2002-07-10 2003-07-09 半导体器件及其制造方法

Country Status (4)

Country Link
US (2) US6770942B2 (https=)
JP (1) JP2004047608A (https=)
CN (1) CN1248317C (https=)
TW (1) TWI227509B (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005005510A (ja) * 2003-06-12 2005-01-06 Toshiba Corp 半導体装置及びその製造方法
US7023059B1 (en) * 2004-03-01 2006-04-04 Advanced Micro Devices, Inc. Trenches to reduce lateral silicide growth in integrated circuit technology
US20060040481A1 (en) * 2004-08-17 2006-02-23 Bor-Wen Chan Methods and structures for preventing gate salicidation and for forming source and drain salicidation and for forming semiconductor device
JP2006128605A (ja) * 2004-09-29 2006-05-18 Toshiba Corp 半導体装置の製造方法
JP2008071890A (ja) * 2006-09-13 2008-03-27 Toshiba Corp 半導体装置及びその製造方法
KR100809335B1 (ko) 2006-09-28 2008-03-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
JP2008103465A (ja) * 2006-10-18 2008-05-01 Toshiba Corp 半導体装置及びその製造方法
US20080116521A1 (en) 2006-11-16 2008-05-22 Samsung Electronics Co., Ltd CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same
US7534678B2 (en) 2007-03-27 2009-05-19 Samsung Electronics Co., Ltd. Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
US7902082B2 (en) 2007-09-20 2011-03-08 Samsung Electronics Co., Ltd. Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers
US8134208B2 (en) * 2007-09-26 2012-03-13 Globalfoundries Inc. Semiconductor device having decreased contact resistance
US7923365B2 (en) 2007-10-17 2011-04-12 Samsung Electronics Co., Ltd. Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon
TWI462294B (zh) * 2010-09-21 2014-11-21 Toshiba Kk Semiconductor element and manufacturing method thereof
JP5687582B2 (ja) 2010-09-21 2015-03-18 株式会社東芝 半導体素子およびその製造方法
US20120119302A1 (en) 2010-11-11 2012-05-17 International Business Machines Corporation Trench Silicide Contact With Low Interface Resistance
CN103855023A (zh) * 2012-12-04 2014-06-11 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法及半导体器件
JP6178118B2 (ja) * 2013-05-31 2017-08-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10428931B2 (en) * 2017-02-27 2019-10-01 Toyota Motor Engineering & Manufacturing North America, Inc. Braze preform for powder metal sintering

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545581A (en) * 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
JPH11204791A (ja) * 1997-11-17 1999-07-30 Toshiba Corp 半導体装置及びその製造方法
US5915199A (en) * 1998-06-04 1999-06-22 Sharp Microelectronics Technology, Inc. Method for manufacturing a CMOS self-aligned strapped interconnection
US6323103B1 (en) * 1998-10-20 2001-11-27 Siemens Aktiengesellschaft Method for fabricating transistors
JP3205306B2 (ja) * 1998-12-08 2001-09-04 松下電器産業株式会社 半導体装置およびその製造方法
JP4010724B2 (ja) 1999-12-28 2007-11-21 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
US6770942B2 (en) 2004-08-03
JP2004047608A (ja) 2004-02-12
CN1472820A (zh) 2004-02-04
US20040241936A1 (en) 2004-12-02
TW200414273A (en) 2004-08-01
US7049222B2 (en) 2006-05-23
US20040007745A1 (en) 2004-01-15
TWI227509B (en) 2005-02-01

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Granted publication date: 20060329