CN1246729A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1246729A CN1246729A CN99118338A CN99118338A CN1246729A CN 1246729 A CN1246729 A CN 1246729A CN 99118338 A CN99118338 A CN 99118338A CN 99118338 A CN99118338 A CN 99118338A CN 1246729 A CN1246729 A CN 1246729A
- Authority
- CN
- China
- Prior art keywords
- resin
- supporting wire
- semiconductor chip
- lead
- encapsulated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 297
- 238000000034 method Methods 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000002390 adhesive tape Substances 0.000 claims abstract description 79
- 229920005989 resin Polymers 0.000 claims abstract description 79
- 239000011347 resin Substances 0.000 claims abstract description 79
- 238000007789 sealing Methods 0.000 claims abstract description 15
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims 2
- 230000001070 adhesive effect Effects 0.000 claims 2
- 238000005516 engineering process Methods 0.000 description 17
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 16
- 238000005538 encapsulation Methods 0.000 description 13
- 238000000465 moulding Methods 0.000 description 11
- 239000011230 binding agent Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 238000012536 packaging technology Methods 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 4
- 241000272168 Laridae Species 0.000 description 4
- 238000007493 shaping process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000002787 reinforcement Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- -1 phenolic aldehyde Chemical class 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 208000034189 Sclerosis Diseases 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 235000010290 biphenyl Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- RTZKZFJDLAIYFH-UHFFFAOYSA-N ether Substances CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29007—Layer connector smaller than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
一种半导体器件包括具有形成于其第一主表面上的多个电极的半导体芯片;于其中密封半导体芯片的树脂封装;电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线。半导体芯片用粘合带键合于支撑引线上。
Description
本发明涉及一种半导体器件,特别涉及可有效地应用于采用铜支撑金属引线框的半导体器件的技术。
一般情况下,采用引线框,用组装工艺制造通过将具有电路系统和形成于电路形成表面即主表面上的多个电极的半导体芯片密封于密封树脂封装中形成的半导体器件。具体说,制备具有框体、支撑引线、由支撑引线支撑于框体上的管芯垫(翼片)、和多个利用拉杆(挡杆)连接的引线的引线框。将混合粘合膏例如热固性环氧树脂和Ag粉制备的Ag膏以粘合树脂膜的形式散布于引线框的管芯垫的安装表面上。具有形成于其主表面上的电极的半导体芯片安装于涂有粘合树脂膜的管芯垫的安装表面上,半导体芯片的第二主表面与接触形成在管芯垫上的粘合树脂膜的第一主表面相对。粘合树脂膜硬化,将半导体芯片固定于管芯垫上。形成于半导体芯片第一主表面上的电极通过导电键合线与引线框引线的内引线部分电连接。然后半导体芯片、内引线、管芯垫、支撑引线和键合线被密封在树脂封装中。然后从引线框的框体上切掉外引线,切割拉杆,按预定形状成形外引线,然后从引线框的框体上切割支撑引线。
顺便提及,有关表面安装半导体器件例如方形扁平封装(QFP)技术的重要的问题是,防止由于温度周期试验即环境试验中作用于表面安装的半导体器件的热,或在将半导体器件安装于布线板上时回流焊期间作用于其上的热造成的树脂封装龟裂,即封装龟裂。已知有两种引起封装龟裂的基本封装龟裂机制。
第一种封装龟裂机制是由于管芯垫从树脂封装上分离、由于温度周期试验或回流焊期间作用于半导体器件上的热造成的树脂封装中所含湿汽蒸发和膨胀引起的封装龟裂。
第二种封装龟裂机制是由于温度周期试验或回流焊期间作用于半导体器件上的热造成的粘合膏中所含湿汽蒸发和膨胀,引起了半导体芯片从管芯垫上分离,由此造成了封装龟裂。
有人提出了解决这个问题的一种技术,例如,日本专利特许公开昭63-204753采用具有小于将安装于其上的半导体芯片的面积的管芯垫。根据该现有技术,管芯垫和树脂封装间的接触面积变小,因此可以抑制由于树脂封装中吸收的湿汽的蒸发和膨胀造成的封装龟裂发生。另外,由于夹在管芯垫和半导体芯片间的粘合膏膜的面积小,所以可以抑制由于粘合膏膜吸收的湿汽的蒸发和膨胀造成的封装龟裂发生。
还有人提出了解决这个问题的另一技术,例如,日本专利特许公开平8-204107采用由两个交叉的支撑引线形成的X形管芯垫(十字形翼片),只在其面对管芯垫的表面的一部分支撑半导体芯片。这种现有技术也可以抑制由于树脂封装中吸收的湿汽的蒸发和膨胀造成的封装龟裂发生,和由于粘合膏膜吸收的湿汽的蒸发和膨胀造成的封装龟裂发生。
在制造半导体器件时,采用Fe-Ni(铁-镍)合金引线框。近来,出现了一种Cu(铜)合金引线框的延伸体。与采用Fe-Ni合金引线框的半导体器件相比,采用Cu合金引线框的半导体器件在散热性能和信号传输速度方面性能优异。然而,由于Cu合金引线框的热膨胀系数大于Fe-Ni合金引线框,所以半导体芯片易从Cu合金引线框的管芯垫上分离下来,造成为防止封装龟裂而采用Cu合金引线框的半导体器件的可靠性下降。
在采用Cu引线框时,有效的是通过将半导体芯片键合到最小可能宽度的支撑引线上,从而减小支撑引线与半导体芯片的接触面积。然而,减小支撑引线宽度时,又产生了新的问题。
形成于支撑引线的芯片支撑部分上的粘合树脂膜的厚度随支撑引线宽度的减小而减小。支撑引线和半导体芯片间的热膨胀系数差异造成的应力由粘合树脂膜吸收。粘合树脂膜吸收应力的能力随粘合树脂膜厚度的减小而减小。在加热支撑引线和半导体芯片的键合工艺和模制工艺其间,超薄粘合树脂膜很难吸收支撑引线和半导体芯片间热膨胀系数差异造成的应力。因而,支撑引线和半导体芯片易彼此分离,键合到支撑引线上的半导体芯片会从支撑引线上脱落,降低了半导体器件组装工艺的成品率。
因此,本发明的目的是提供一种能够提高半导体器件组装工艺的成品率的技术。
从以下说明书和各附图中的介绍,可以更加清楚本发明的上述和其它目的及新特点。
下面简要介绍本专利申请所公开的发明的各例子。
(1)一种半导体器件包括:具有形成于其第一主表面上的多个电极的半导体芯片;于其中密封半导体芯片的树脂封装;电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线;其中半导体芯片用粘合带键合于支撑引线上。
(2)一种半导体器件包括:具有形成于其第一主表面上的多个电极的方形半导体芯片;于其中密封半导体芯片的方形树脂封装;电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线,其延伸通过半导体芯片的两对角;其中半导体芯片用粘合带键合于支撑引线上。
(3)一种半导体器件包括:具有形成于其第一主表面上的多个电极的方形半导体芯片;于其中密封半导体芯片的方形树脂封装;电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线,其延伸穿过半导体芯片的两相对侧边;其中半导体芯片用粘合带键合于支撑引线上。
(4)一种半导体器件包括:具有形成于其第一主表面上的多个电极的方形半导体芯片;于其中密封半导体芯片的方形树脂封装;电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线;其中树脂封装的第一角部具有树脂传递部分,支撑引线从树脂封装的第一角部向着与第一角相对的树脂封装的第二角部延伸,半导体芯片用粘合带键合于支撑引线上。
(5)一种半导体器件包括:具有形成于其第一主表面上的多个电极的方形半导体芯片;于其中密封半导体芯片的方形树脂封装;电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线;其中树脂封装第一侧的中部具有树脂传递部分,支撑引线在连接树脂封装的第一侧的中部和与第一侧相对的树脂封装的第二侧的中部的假想线上延伸,半导体芯片用粘合带键合于支撑引线上。
根据上述方法,可以不管支撑引线的宽度,形成大厚度的粘合带。因此,可以根据支撑引线和半导体芯片间热膨胀系数差异造成的应力确定粘合带的厚度。因而,可以抑制管芯键合工艺后半导体芯片从支撑引线上脱落问题的发生,从而可以提供半导体器件组装工艺的成品率。
图1是本发明第一实施例半导体器件的平面图,其中去掉了树脂封装的上部;
图2是沿图1中线A-A取的剖面图;
图3是沿图1中线B-B取的剖面图;
图4是沿图1中线C-C取的剖面图;
图5是半导体器件的主要部件的透视图;
图6是图3所示主要部件的剖面图;
图7是制造半导体器件时采用的引线框的平面图;
图8是粘合带形成工艺中树脂膜的典型平面图;
图9是沿图8中的线D-D取的典型剖面图;
图10是粘合带形成工艺中树脂膜的典型平面图;
图11是用于解释制造半导体器件的方法的平面图;
图12是用于解释制造半导体器件的方法的剖面图;
图13是用于解释制造半导体器件的方法的剖面图;
图14第一改形的树脂膜的主要部分的平面图;
图15第二改形的树脂膜的主要部分的平面图;
图16第三改形的树脂膜的主要部分的平面图;
图17是制造半导体器件时将采用的另一引线框的平面图;
图18是制造半导体器件时将采用的另一引线框的平面图;
图19是制造半导体器件时将采用的另一引线框的平面图;
图20是制造半导体器件时将采用的另一引线框的平面图;
图21是根据本发明第二实施例的半导体器件的平面图,其中去掉了树脂封装的上部;
图22是沿图21中的线E-E取的剖面图;
图23是制造半导体器件中采用的引线框的平面图。
下面结合附图介绍本发明的优选实施例,其中具有相同功能的部件用相同的参考标记表示,不再对其作介绍。
第一实施例
根据本发明第一实施例的半导体器件是引线设置于其四个边上的QFP(方形扁平封装)型。
下面结合图1-6介绍半导体器件的构成。图1是本发明第一实施例的半导体器件的平面图,其中去掉了树脂封装的上部,图2是沿图1中线A-A取的剖面图,图3是沿图1中线B-B取的剖面图,图4是沿图1中线C-C取的剖面图,图5是半导体器件的主要部件的透视图,图6是图3所示主要部件的剖面图。
参见图1、2、3和4,在支撑引线3和辅助引线4的交叉处5上安装半导体芯片10,并将半导体芯片10密封于树脂封装13中,从而形成第一实施例的半导体器件1。
半导体芯片10的平面形状为方形。半导体芯片10例如是边长为9mm的方形。半导体芯片10包括作为主要部件的单晶硅半导体衬底及形成于半导体衬底上的布线层。该半导体芯片10具有3×10-6[1/℃]的热膨胀系数。
电路系统,例如逻辑电路系统或由逻辑电路系统和存储电路系统构成的组合电路系统形成于半导体芯片10的电路形成表面(第一主表面)10X上。电路系统包括形成于半导体衬底上的半导体元件,和形成于半导体衬底上电连接各半导体元件的布线。多个电极(键合焊盘)11沿其侧边形成于半导体芯片10的电路形成表面10X上。多个电极11形成在半导体芯片10的各布线层的上层上,并主要通过布线与电路系统的各构成半导体元件电连接。多个电极11是通过加工金属膜例如铝(Al)或铝合金形成的。
树脂封装13的平面形状是方形的。该实施例中,树脂封装13具有边长为14mm的方形。树脂封装由诸如联二苯树脂或邻甲酚酚醛清漆树脂等含酚醛硬化剂的树脂、硅酮和填料构成,以抑制应力的产生。树脂封装13具有13×10-6[1/℃]的热膨胀系数。
树脂封装13是利用适用于批量生产的传递模法形成的。传递模法采用具有传递材料槽、流道、传递浇口和凹腔的模具,将从传递槽提供的树脂供到流道,将树脂通过传递浇口传递到凹腔中,以模制树脂封装。
多个引线2沿树脂装13的侧边设置于半导体芯片10的周围。多个引线2的每个引线在树脂封装13内部和外部延伸,具有在树脂封装13内延伸的内引线部分2A,和在树脂封装13外延伸的外引线部分2B。
多个引线2的内引线部件2A分别通过导电丝12与半导体芯片10的电极11电连接,其外引线部分2B按适于表面安装的形状成形,例如鸥翼形。例如,导电丝12是金丝(Au丝)。例如,采用热压键合和超声焊接的键合法,连接导电线12和内引线部分2A。
支撑引线3、辅助引线4和导电丝12与半导体芯片10一起密封在树脂封装13中。
参见图1和3,支撑引线3在树脂封装13的第一角部13A和沿对角线与第一角部13A相对的树脂封装的第二角部13B之间延伸,并穿过半导体芯片10的第一角部10A和沿对角线与第一角部10A相对的半导体芯片10的第二角部10B;即,支撑引线在连接树脂封装13的第一角部13A和第二角部13B的对角线上延伸。
如图3所示,支撑引线3具有引线部分3A和3B,引线部分3A在厚度方向上(垂直方向)包含在包括图2所示的引线2的内引线部分2A的平面内。引线部分3B在厚度方向上(垂直方向)包含在包括图2所示的引线2的内引线部分2A的平面之下的平面内。
如图1和4所示,辅助引线4在树脂封装13的第三角部13C和沿对角线与第三角部13C相对的第四角部13D之间延伸,并穿过半导体芯片10的第三角部10C和沿对角线与第三角部10C相对的半导体芯片10的第四角部10D;即,辅助引线4在连接树脂封装13的第三角部13C和第四角部13D的对角线上延伸。
如图4所示,辅助引线4具有引线部分4A和4B。引线部分4A在厚度方向上(垂直方向)包含在包括图3所示的引线3的引线部分3A的平面内。引线部分4B在厚度方向上(垂直方向)包含在包括图3所示的引线3的引线部分3A的平面之下的平面内。
如图5所示,浇口断开标记13X形成在树脂封装13的第一角部13A。浇口断开标记13X在树脂浇口与树脂封装13时断开形成。半导体器件1在树脂封装13的第一角部13A处具有树脂传递部分。
如图3所示,半导体芯片10用粘合带8键合到支撑引线3的引线部分3B上。粘合带8沿支撑引线3纵向延伸。该实施例中,粘合带8以其在半导体芯片10外延伸的部分粘到引线部分3B上。粘合带8粘合到支撑引线3的引线部分3B上,以便沿支撑引线3纵向延续。于是半导体芯片10用沿支撑引线3纵向延伸的粘合带8键合到支撑引线3的引线部分3B上。
粘合带8例如包括树脂基带8A和分别形成于基带8A的主表面(相对表面)上的粘合层8B。树脂基带8A由热膨胀系数例如为2.5×10-5[1/℃]的聚酰亚胺树脂构成。粘合层8B由热塑性聚(醚酰胺)或环氧树脂或热膨胀系数例如为5×10-5[1/℃]的热固性树脂构成。
在半导体芯片热压键合到支撑引线3上时,粘合带8的厚度稍有减小。在半导体芯片10热压键合到支撑引线3上之前,粘合带8厚约0.061mm,树脂基带8A厚约0.025mm,粘合层8B厚约0.018mm。半导体芯片10热压键合到支撑引线3上之后,粘合带8的厚度约为0.05mm。
不管支撑引线3的宽度如何,都可以增大粘合带8的厚度。因此,粘合带8的厚度可以根据支撑引线3和半导体芯片10间的热膨胀系数间差异可能造成的应力确定。
支撑引线3的宽度范围例如为0.3-0.5mm。因此,支撑引线3在半导体芯片10的与其第一主表面10X相对的第二主表面10Y的一部分处支撑半导体芯片10。
尽管在前面介绍的实施例中,支撑引线3和辅助引线4可以作为一根引线,但可以建议具有从交叉处5分别在相反方向延伸的两个支撑引线3,和从交叉处5分别在相反方向延伸的两个辅助引线4。
下面结合平面展示了引线框的图7介绍用于半导体器件1的引线框。
参见图7,引线框LF1具有方形框体7、用于电连接的多个引线2、支撑半导体芯片10的支撑引线3和增强支撑引线3的机械强度的辅助引线4。树脂传递部分形成在引线框LF1的框体7的第一角部7A处。
各引线2分为四组引线,四组引线分别沿框体7的各构件排列。每组引线的每根引线2都具有在树脂封装内延伸的内引线部分2A和在树脂封装外部延伸的外引线部分2B。每组引线的引线2通过拉杆6连接,防止用模具模制树脂封装时树脂从模具中泄漏。各引线组的引线2的外引线部分2B与框体7一体形成。
支撑引线3在框体7的第一角部7A和沿对角线与第一角部7A相对的其第二角部7B间延伸。支撑引线3的一端连接到框体7的第一角部7A,另一端连接到拉杆6。支撑引线3在连接引线框LF1的框体7的第一角部7A和第二角部7B的对角线上延伸。
辅助引线4在框体7的第三角部7C和沿对角线与第三角部7C相对的其第四角部7D间延伸。辅助引线4的相对端皆与拉杆6连接。辅助引线4在连接引线框LF1的框体7的第三角部7C和第四角部7D的对角线上延伸。
支撑引线3和辅助引线4在框体7包围的区域的中部彼此交叉且彼此连接。支撑引线3和辅助引线4弯曲,以便在安装到支撑引线3上时,半导体芯片10的背面即下表面处于低于包括引线2的上连接面的平面的平面内。
粘合带8粘附在支撑引线3的芯片安装部分上。粘合带8粘附到支撑引线的引线部分3B上,以便沿支撑引线3纵向延续。粘合带8的宽度大约等于支撑引线3的宽度。
引线框LF1例如由热膨胀系数为17×10-6[1/℃]的铜合金构成。引线框LF1是通过以下步骤形成的,对金属片进行腐蚀工艺或冲压加工工艺,形成包括引线2、支撑引线3和辅助引线4的引线框LF1构件,通过冲压工工艺,成形支撑引线3和辅助引线4,并将粘合带8粘附到支撑引线3的芯片安装表面上。顺便提及,例如含42%或50%的Ni的Fe-Ni合金引线框的热膨胀系数为4.3×10-6[1/℃]。
如图8(用于解释形成粘合带的工艺的典型平面图)和图9(沿图中的线D-D取的典型剖面图)所示,采用夹具16,切割粘合带材15的垂直宽度,形成粘合带8。一般情况下,沿垂直于粘合带材15长边(长度)的切割线,切割粘合带材15,从而形成粘合带8。如图10(用于解释形成粘合带的工艺的典型平面图)所示,分别沿与粘合带材15的长边成锐角倾斜的倾斜切割线,切割粘合带材15,从而形成不同长度的粘合带8。沿与粘合带材15的长边成锐角倾斜的倾斜切割线切割粘合带材15形成的粘合带8的形状为平行四边形。
下面结合图11-13介绍制造半导体器件1的方法。图11是处于完成了引线键合工艺后的制造阶段的半导体器件的平面图,图12和13是用于解释模制工艺的剖面图。图12是沿图1中的线A-A取的剖面图,图13是沿图1中的线C-C取的剖面图。
制造图7所示的引线框LF1。制备图12和13所示的模具20。模具20具有上模20A和下模20B。凹腔21由上模20和下模20B限定。模具20具有开口向着凹腔21的传递浇口22、与浇口22连接的流道23、与流道23连接未示出的材料槽。
利用热压键合工艺,用粘合带8将半导体芯片10键合到支撑引线3的芯片安装部分上。尽管热压键合工艺要加热支撑引线3和半导体芯片10,但由于根据可能由于支撑引线3和半导体芯片10间的热膨胀系数差造成的应力确定粘合带8的厚度,所以半导体芯片10不会从支撑引线3上脱落下来。
借助于采用热压键合和超声键合的引线键合工艺,分别用导电丝12将半导体芯片10的电极11电连接到引线2的内引线部分2A上。尽管在引线键合工艺中要热加引线和半导体芯片10,但由于根据可能由于支撑引线3和半导体芯片10间的热膨胀系数差异造成的应力确定粘合带8的厚度,所以半导体芯片10不会从支撑引线3上脱落下来。这些工艺示于图11中。
参见图12和13,框体7设置于模具20的上模20A和下模20B之间,其第一角部7A(树脂传递部分)位于对应于传递浇口22的位置,半导体芯片10、引线2的内引线部分、支撑引线3、辅助引线4和导电丝12设置于凹腔22中。
在模制工艺中,树脂从材料槽提供,树脂在压力的作用下流过流道23和传递浇口22进入凹腔21。于是,将半导体芯片10、引线2的内引线部分、支撑引线3、辅助引线4和导电丝12密封于树脂中。在模制工艺中,由于半导体芯片10键合到远离传递浇口22延伸的支撑引线3上,所以可以抑制在压力作用下被迫进入凹腔21并在凹腔21中流动的树脂流易引起半导体芯片10的垂直位置的变化的问题。由于辅助引线4与支撑引线2连接,支撑引线的机械强度得到辅助引线4的加强。因而,可以抑制在压力作用下被迫进入凹腔21并在凹腔21中流动的树脂流易引起半导体芯片10的垂直位置的变化的问题。
从模具20中取出引线框LF1,去掉连接到树脂封装13第一角部13A的树脂浇口,切掉连接引线2的拉杆6,从框体7上切割引线2的外引线部分2B,按适于表面安装的形状成形外引线部分2B,例如鸥翼形,然后,从框体7上切割支撑引线3和辅助引线4,从而得到图1-6所示的基本上完成的半导体器件1。
对半导体器件1进行温度周期试验,然后将半导体器件1作为产品发货。作为产品发货的半导体器件1安装到布线板上。温度周期试验重复试验周期1000次。例如,试验周期使半导体器件1保持在-55℃10分钟,然后在150℃保持10分钟。对本发明半导体器件进行温度周期试验。半导体器件1的树脂装13中没有形成任何龟裂。
第一实施例具有以下效果。
(1)半导体芯片10借粘合带8键合到支撑引线3上。因此,可以不管支撑引线3的宽度如何确定粘合带8的厚度,并可以根据支撑引线3和半导体芯片10的热膨胀系数差异造成的应力确定粘合带8的厚度。因而,可以抑制管芯键合工艺后半导体芯片10从支撑引线3上脱离下来问题的发生,从而可以提高组装半导体器件1的组装工艺的成品率。
由于粘合带8的厚度可以根据支撑引线3和半导体芯片10热膨胀系数间的差异造成的应力确定,所以可以提高组装采用Cu合金引线框LF1的半导体器件1的组装工艺的成品率。
(2)半导体芯片10键合到远离树脂传递浇口延伸的支撑引线3上。因此,可以抑制在压力作用下被迫进入凹腔21并在凹腔21中流动的树脂流造成的半导体芯片10的垂直位置的变化。因此,可以抑制例如半导体芯片10和导电丝12露出树脂封装13外等缺陷的发生,可以提高组装半导体器件1的组装工艺的成品率。
由于可以抑制半导体芯片10和导电丝12露出树脂封装13外的可能性,树脂封装13的厚度可以形成得很小,进而可以形成小厚度的半导体器件1。
(3)支撑引线3连接辅助引线4。因此,支撑引线3的机械强度得到辅助引线4的加强,可以抑制在压力作用下被迫进入凹腔21中的树脂流造成的半导体芯片10垂直位置的变化。
(4)半导体芯片10键合到在对角线上相对的第一角部10A和第二角部10B间延伸的支撑引线3上。因此,与半导体芯片10中部键合的情况相比,可以抑制在压力作用下被迫进入凹腔21中的树脂流引起的支撑引线3的垂直运动。
(5)支撑引线3延伸,以便穿过半导体芯片10的两相对角部10A和10B,辅助引线4延伸,以穿过两相对角部10C和10D。由于支撑引线3和辅助引线4不在半导体芯片10和引线2的端部间的空间延伸,所以即使导电丝12垂下,也可以避免导电丝12与支撑引线3和辅助引线4接触的可能性。导电丝12越长,导电丝12的悬垂度便会越大。
由于支撑引线3和辅助引线4不在半导体芯片10和引线2的端部间的空间延伸,所以即使半导体芯片10的外部尺寸减小,并且导电丝12垂下,导电丝12也不会与支撑引线3和辅助引线4接触,因此,可以在支撑引线3上支撑不同尺寸的半导体芯片10。所以,可以标准化能够安装不同外部尺寸的半导体芯片10的引线框。
该实施例中,粘合带8的宽度等于支撑引线3的宽度。粘合带8的宽度W2可以小于支撑引线3的宽度W1,如图14所示。
该实施例中,纵向延续的粘合带8附着到支撑引线3上,以便沿支撑引线3的长度延伸。粘合带8可以按如图15所示每隔一段距离粘到支撑引线3上。按图15所示的各种间隔排列粘合带8,可以方便将粘合带8附着于支撑引线3上的加工。
该实施例中,粘合带8的宽度等于支撑引线3的宽度。粘合带8的宽度W2可以大于支撑引线3的宽度W1。
制造半导体器件时可以采用图17所示的引线框LF2。引线框LF2不具有任何对应于辅助引线4的部件。采用这种引线框LF2的半导体器件的效果与第一实施例的半导体器件1的效果相同。省略了辅助引线4后,引线2的间距可以增大,这可以有效地降低形成树脂封装时树脂流可能造成的导电丝间接触的可能性。
制造半导体器件时可以采用图18所示的引线框LF3。该引线框LF3具有宽于支撑引线3和辅助引线4的衬垫25,其形成在支撑引线3和辅助引线4的交叉处。采用引线框LF3的半导体器件的效果与第一实施例的半导体器件10相同。由于支撑引线3具有加强的抗弯强度,所以可以有效地抑制形成树脂封装时树脂流可能造成的支撑引线3垂直位置的变化。
制造半导体器件时可以采用图19所示的引线框LF4,引线框LF4具有形成在支撑引线3和辅助引线4的交叉处的衬垫25和从衬垫25延伸并且宽于支撑引线3和辅助引线4的衬垫26。采用引线框LF4的半导体器件的效果与第一实施例的半导体器件1相同。
在制造半导体器件时可以采用图20所示的引线框LF5。引线框LF5具有形成在支撑引线3和辅助引线4的交叉处的衬垫25,离开衬垫25在支撑引线3和辅助引线4的中部的小衬垫26。采用引线框LF5的半导体器件的效果与第一实施例的半导体器件1相同。
半导体器件可以采用未示出的具有支撑引线3的引线框,该支撑引线3具有在其上支撑半导体芯片10的支撑部分,且其宽度大于不对应于半导体芯片10的部分的宽度。
尽管该实施例中,半导体芯片10用粘合带键合到支撑引线上,但半导体芯片10可以用粘合层键合到支撑引线3上,粘合层可以形成为小于30微米的厚度。
第二实施例
根据本发明第二实施例的半导体器件是具有设置于其两侧上的引线的SOP(小外形封装)型。
下面将结合图21和22介绍该半导体器件的构成。图21是本发明第二实施例的半导体器件的平面图,其中去掉了树脂封装的上部,图22是沿图21中的线E-E取的剖面图。
参见图21和22,将半导体芯片10安装在支撑引线3的芯片安装部分上,并将半导体芯片10封装在树脂封装13中,从而形成第二实施例的半导体器件30。
该实施例中,半导体芯片10的平面形状为方形,半导体芯片10例如为矩形。半导体芯片10具有电路形成表面10X。多个电极沿其相对的长边形成于电路形成表面10X上。该实施例中,树脂封装13的平面形状为方形,树脂封装13例如为矩形。
多个引线2沿树脂封装13的相对长边排列于半导体芯片10外部。多个引线2的每根引线在树脂封装13的内部和外部延伸,并具有在树脂封装13内部延伸的内引线部分2A,和在树脂封装13的外部延伸的外引线部分2B。
多个引线2的内引线部分2A分别通过导电丝12与半导体芯片10的电极11电连接,其外引线部分2B按适于表面安装的形状成形,例如鸥翼形。支撑引线3、导电丝12和半导体芯片10密封在树脂封装13中。
支撑引线3在树脂封装13第一边的中间和与第一边13X相对的其第二边13Y的中部间延伸的假想线上延伸。支撑引线3跨越半导体芯片10背面的第一边10S和与第一边10S相对的其第二边10T延伸。
未示出的浇口断开标记留在树脂封装13的第一边13X上。浇口断开标记是在断开与树脂封装13连接的树脂浇口时形成的。因此,该实施例的半导体器件30具有在树脂封装13的第一边13X的中部的树脂传递部分。
半导体芯片10用粘合带8键合到支撑引线3的引线部分3B上。粘合带8沿支撑引线3纵向延伸。该实施例中,粘合带8粘附到其各部分在半导体芯片10外延伸的引线部分3B上。粘合带8粘附到支撑引线3的引线部分3B上,以便沿支撑引线3纵向延续。于是,半导体芯片10用沿支撑引线3纵向延伸的粘合带8键合到支撑引线3的引线部分3B上。
可以不管支撑引线3的宽度增大粘合带8的厚度。因此,可以根据支撑引线3和半导体芯片10间热膨胀系数差异可能造成的应力确定粘合带8的厚度。
支撑引线3的宽度例如约为0.4mm。因此,支撑引线3在与其第一主表面10X相对的半导体芯片10的第二主表面10Y(背面)的一部分处支撑半导体芯片10。
下面结合平面展示引线框的图23介绍制造半导体器件30时采用引线框。
参见图23,引线框LF6具有方形框体7、多个用于电连接的引线2和支撑半导体芯片10的支撑引线3。树脂传递部分形成于引线框LF6框体7的第一框体部件7X中。
多个引线2被分成两个引线组,两组引线分别设置在框体7的两相对框体部件上。每个引线组的各引线2沿框体部件排列。每个引线组的每根引线2都具有在树脂封装内延伸的内引线部分2A和在树脂封装外部延伸的外引线部分2B,每个引线组的引线2由拉杆6连接,防止用模具模制树脂封装时树脂从模具中泄漏出。各引线组的引线2的外引线部分2B与框体7形成为一体。
支撑引线3在框体7的第一框体部件7X的中部和与第一框体部件7X相对的第二框体部件7Y的中部之间延伸。支撑引线3的一端连接到框体7的第一框体部件7X,另一端连接到拉杆6。支撑引线3在连接引线框LF6框体7的第一框体7X和第二框体7Y的对角线上延伸。
粘合带8粘附到支撑引线3的芯片安装部分上。粘合带8粘附到支撑引线3的引线部分3B上,从而沿支撑引线3纵向延续。粘合带8的宽度约等于支撑引线3的宽度。
下面介绍制造半导体器件30的方法。制造图23所示的引线框LF6。制备模具。模具具有上模和下模。上模和下模限定一个凹腔。该模具具有向着凹腔开口的传递浇口、连接到传递浇口的流道和连接到流道的材料槽。
半导体芯片10利用粘合带8热压键合到支撑引线3的芯片安装部分上。尽管热压键合工艺中要加热支撑引线3和半导体芯片10,但由于根据支撑引线3和半导体芯片10热膨胀系数差异可能造成的应力确定粘合带的厚度,半导体芯片10不会从支撑引线3上脱落下来。
采用热压键合和超声键合结合的引线键合工艺,分别通过导电丝12电连接半导体芯片10的电极11与引线2的内引线部分2B。尽管引线键合工艺中要加热支撑引线3和半导体芯片10,但由于根据支撑引线3和半导体芯片10热膨胀系数差异可能造成的应力确定粘合带8的厚度,半导体芯片10不会从支撑引线3上脱落下来。
框体7设置于模具的上模和下模之间,其树脂传递部分位于对应于传递浇口的位置,半导体芯片10、引线2的内引线部分、支撑引线3和导电丝12设置于凹腔内。
在模制工艺中,从材料槽提供树脂,树脂在压力作用下被迫流过流道和传递浇口进入凹腔。于是,将半导体芯片10、引线2的内引线部分、支撑引线3和导电丝12密封在树脂中。模制工艺中,由于半导体芯片10键合到离开传递浇口延伸的支撑引线3上,所以可以抑制在压力作用下被迫进入凹腔中并在凹腔中流动的树脂流易造成半导体芯片10垂直位置变化的问题。
从模具中取出引线框LF6,去掉连接到树脂封装13的第一边13X上的树脂浇口,并切掉连接引线2的拉杆6,从框体7上切割引线2的外引线部分2B,按适于表面安装的形状例如鸥翼形成形外引线部分2B,然后从框体7上切割支撑引线3,以得到图21和22所示基本上完成的半导体器件30。第二实施例具有与第一实施例相同的效果。
尽管结合优选实施例介绍了本发明,但这里所介绍的实施例不是限制性,在不背离本发明范围的情况下,可以作出许多改变和变化。
例如,本发明可应用于引线排列成单行的SIP(单列直插式封装)型和ZIP(曲折排列直插式封装)型半导体器件。
本发明还可以应用于引线排列成两行的SOJ(小外形J引线封装)型和TSOP(薄小外形封装)型半导体器件。
本发明还可以应用于引线排列成四行的QFJ(方形扁平J引线封装)型半导体器件。
Claims (19)
1·一种半导体器件,包括:
具有形成于其第一主表面上的多个电极的半导体芯片;
于其中密封半导体芯片的树脂封装;
电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;
在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线;
其中半导体芯片用粘合带键合于支撑引线上。
2·一种半导体器件,包括:
具有形成于其第一主表面上的多个电极的方形半导体芯片;
于其中密封半导体芯片的方形树脂封装;
电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;
在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线,其延伸通过半导体芯片的两对角;
其中半导体芯片用粘合带键合于支撑引线上。
3·一种半导体器件,包括:
具有形成于其第一主表面上的多个电极的方形半导体芯片;
于其中密封半导体芯片的方形树脂封装;
电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;
在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线,其延伸穿过半导体芯片的两相对侧边;
其中半导体芯片用粘合带键合于支撑引线上。
4·一种半导体器件,包括:
具有形成于其第一主表面上的多个电极的方形半导体芯片;
于其中密封半导体芯片的方形树脂封装;
电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;
在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线;
其中树脂封装的第一角部具有树脂传递部分,支撑引线从树脂封装的第一角部向着与第一角相对的树脂封装的第二角部延伸,半导体芯片用粘合带键合于支撑引线上。
5·一种半导体器件,包括:
具有形成于其第一主表面上的多个电极的方形半导体芯片;
于其中密封半导体芯片的方形树脂封装;
电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;
在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线;
其中树脂封装第一侧的中部具有树脂传递部分,支撑引线在连接树脂封装的第一侧的中部和与第一侧相对的树脂封装的第二侧的中部的假想线上延伸,半导体芯片用粘合带键合于支撑引线上。
6·根据权利要求1的半导体器件,其中粘合带具有树脂基件和分别形成于树脂基件的相对主表面上的粘合层。
7·根据权利要求1的半导体器件,其中粘合带沿支撑引线的长度纵向延伸。
8·根据权利要求1的半导体器件,其中粘合带粘附到支撑引线上,以便其部分在半导体器件外延伸。
9·根据权利要求1的半导体器件,其中粘合带粘附到支撑引线上,以便沿支撑引线的长度纵向延续。
10·根据权利要求1的半导体器件,其中粘合带沿支撑引线的长度每隔一段距离粘附到支撑引线上。
11·根据权利要求1的半导体器件,其中支撑引线由铜或铜合金构成。
12·一种制造半导体器件的方法,半导体器件包括:具有形成于其第一主表面上的多个电极的半导体芯片;于其中密封半导体芯片的树脂封装;电连接半导体芯片电极的多个引线,其形成为在树脂封装内部和外部延伸;在与第一主表面相对的半导体芯片第二主表面的一部分处支撑半导体芯片的支撑引线;
其中半导体芯片用粘合带键合于支撑引线上。
13·一种制造半导体器件的方法,所说方法包括以下步骤:
制备引线框,所说引线框具有平面形状为方形的框体、多个支撑于框体上的引线、支撑于框体上的支撑引线、及粘附于支撑引线上的粘合带,所说框体在其第一角部具有树脂传递部分,每根所说引线都具有内引线部分和外引线部分,所说支撑引线在框体的第一角部和与第一角部相对的其第二角部间延伸,模具包括上模和下模,并具有由上模和下模限定的凹腔和向着凹腔开口的树脂传递浇口;
利用粘合带将半导体芯片粘合键合到支撑引线上;
用导电丝分别将半导体芯片的各电极电连接到各引线的内引线部分上;及
将引线框设置于模具的上下模之间,以便框体的树脂传递部分与树脂传递浇口吻合,通过树脂传递浇口将树脂注入到凹腔中,在树脂中密封半导体芯片、引线的内引线部分、支撑引线和导电丝。
14·一种制造半导体器件的方法,该方法包括以下步骤:
制备引线框,所说引线框具有平面形状为方形的框体、多个支撑于框体上的引线、支撑于框体上的支撑引线、及粘附于支撑引线上的粘合带,所说框体在其第一框体部件上具有树脂传递部分,每根所说引线都具有内引线部分和外引线部分,所说支撑引线在框体的第一框体件的中部和与第一框体件相对的其第二框体件的中部之间延伸的假想线上延伸,模具包括上模和下模,并具有由上模和下模限定的凹腔和向着凹腔开口的树脂传递浇口;
利用粘合带将半导体芯片粘合键合到支撑引线上;
用导电丝分别将半导体芯片的各电极电连接到各引线的内引线部分上;及
将引线框设置于模具的上下模之间,以便框体的树脂传递部分与树脂传递浇口吻合,通过树脂传递浇口将树脂注入到凹腔中,在树脂中密封半导体芯片、引线的内引线部分、支撑引线和导电丝。
15·根据权利要求11制造半导体器件的方法,其中粘合带具有树脂基件和分别形成于树脂基件的相对主表面上的粘合层。
16·根据权利要求11制造半导体器件的方法,其中粘合带沿支撑引线的长度纵向延伸。
17·根据权利要求11制造半导体器件的方法,其中粘合带粘附到支撑引线上,以便沿支撑引线的长度纵向延续。
18·根据权利要求11制造半导体器件的方法,其中粘合带沿支撑引线的长度每隔一段距离粘附到支撑引线上。
19·根据权利要求11制造半导体器件的方法,其中支撑引线由铜或铜合金构成。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10245406A JP2000077435A (ja) | 1998-08-31 | 1998-08-31 | 半導体装置及びその製造方法 |
JP245406/1998 | 1998-08-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1246729A true CN1246729A (zh) | 2000-03-08 |
CN1204622C CN1204622C (zh) | 2005-06-01 |
Family
ID=17133188
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB99118338XA Expired - Fee Related CN1204622C (zh) | 1998-08-31 | 1999-08-31 | 半导体器件及其制造方法 |
Country Status (7)
Country | Link |
---|---|
US (3) | US6340837B1 (zh) |
JP (1) | JP2000077435A (zh) |
KR (1) | KR100674548B1 (zh) |
CN (1) | CN1204622C (zh) |
MY (1) | MY123034A (zh) |
SG (1) | SG77704A1 (zh) |
TW (1) | TW508702B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100421240C (zh) * | 2002-11-22 | 2008-09-24 | 国际整流器公司 | 具有连接外部元件的引片的半导体装置 |
CN100454530C (zh) * | 2004-06-08 | 2009-01-21 | 罗姆股份有限公司 | 面装配型电子部件及其制造方法 |
US8105871B2 (en) | 2006-08-16 | 2012-01-31 | Fujitsu Semiconductor Limited | Semiconductor device and manufacturing method of the same |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000077435A (ja) * | 1998-08-31 | 2000-03-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR100350046B1 (ko) * | 1999-04-14 | 2002-08-24 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 방열판이 부착된 반도체패키지 |
KR100381892B1 (ko) * | 1999-11-24 | 2003-04-26 | 삼성전자주식회사 | 듀얼-리드 타입 정방형 반도체 패키지 및 그를 사용한양면 실장형 메모리 모듈 |
JP2001291720A (ja) * | 2000-04-05 | 2001-10-19 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP3403699B2 (ja) * | 2000-05-31 | 2003-05-06 | 宮崎沖電気株式会社 | 半導体装置および半導体装置の製造方法 |
JP2002299540A (ja) | 2001-04-04 | 2002-10-11 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002343816A (ja) * | 2001-05-18 | 2002-11-29 | Lintec Corp | 樹脂タイバー形成用テープ、樹脂タイバー、樹脂タイバー付リードフレーム、樹脂封止型半導体装置およびその製造方法 |
TW568355U (en) * | 2002-01-16 | 2003-12-21 | Orient Semiconductor Elect Ltd | Improved leadframe structure for integrated circuit |
SG105544A1 (en) * | 2002-04-19 | 2004-08-27 | Micron Technology Inc | Ultrathin leadframe bga circuit package |
JP3851845B2 (ja) * | 2002-06-06 | 2006-11-29 | 株式会社ルネサステクノロジ | 半導体装置 |
TWI267959B (en) * | 2002-11-27 | 2006-12-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with chip-supporting member |
JP2004253706A (ja) * | 2003-02-21 | 2004-09-09 | Seiko Epson Corp | リードフレーム、半導体チップのパッケージング部材、半導体装置の製造方法、及び、半導体装置 |
WO2004112298A2 (en) * | 2003-05-27 | 2004-12-23 | The Trustees Of Columbia University In The City Of New York | Multichannel time encoding and decoding of a signal |
US7102159B2 (en) * | 2004-06-12 | 2006-09-05 | Macronix International Co., Ltd. | Ultra thin image sensor package structure and method for fabrication |
US20060220191A1 (en) * | 2005-04-01 | 2006-10-05 | Honeywell International Inc. | Electronic package with a stepped-pitch leadframe |
JP2009099709A (ja) * | 2007-10-16 | 2009-05-07 | Nec Electronics Corp | 半導体装置 |
US7868433B2 (en) * | 2008-08-29 | 2011-01-11 | National Semiconductor Corporation | Low stress cavity package |
EP3428962B1 (en) * | 2016-03-07 | 2022-03-30 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
CN110166111B (zh) * | 2019-05-24 | 2021-08-31 | 上海众执芯信息科技有限公司 | 一种5g卫星移动通信信号转发器 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2534251B2 (ja) | 1987-02-20 | 1996-09-11 | 日東電工株式会社 | 半導体装置 |
US5177032A (en) * | 1990-10-24 | 1993-01-05 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
JP2994510B2 (ja) | 1992-02-10 | 1999-12-27 | ローム株式会社 | 半導体装置およびその製法 |
KR100552353B1 (ko) * | 1992-03-27 | 2006-06-20 | 가부시키가이샤 히타치초엘에스아이시스템즈 | 리이드프레임및그것을사용한반도체집적회로장치와그제조방법 |
US5327008A (en) * | 1993-03-22 | 1994-07-05 | Motorola Inc. | Semiconductor device having universal low-stress die support and method for making the same |
JPH07263470A (ja) | 1994-03-18 | 1995-10-13 | Fujitsu Ltd | 半導体チップの装着方法 |
US5429992A (en) * | 1994-05-25 | 1995-07-04 | Texas Instruments Incorporated | Lead frame structure for IC devices with strengthened encapsulation adhesion |
KR100366111B1 (ko) | 1994-11-08 | 2003-03-06 | 오끼 덴끼 고오교 가부시끼가이샤 | 수지봉합형 반도체장치의 구조 |
JPH08204107A (ja) | 1995-01-27 | 1996-08-09 | Rohm Co Ltd | 樹脂封止型半導体装置 |
JPH09111204A (ja) | 1995-10-16 | 1997-04-28 | Shinko Electric Ind Co Ltd | 導電性接着テープおよびこれを用いた半導体装置用パッケージ |
JPH1012760A (ja) | 1996-06-24 | 1998-01-16 | Hitachi Cable Ltd | 半導体装置 |
US6002165A (en) * | 1998-02-23 | 1999-12-14 | Micron Technology, Inc. | Multilayered lead frame for semiconductor packages |
JP2000077435A (ja) * | 1998-08-31 | 2000-03-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
DE19941037C1 (de) * | 1999-08-28 | 2001-01-04 | Wilfried Strothmann Gmbh & Co | Positionierungsförderer zum horizontalen Ausrichten von Platten |
-
1998
- 1998-08-31 JP JP10245406A patent/JP2000077435A/ja active Pending
-
1999
- 1999-08-04 SG SG1999003757A patent/SG77704A1/en unknown
- 1999-08-05 TW TW088113382A patent/TW508702B/zh not_active IP Right Cessation
- 1999-08-10 MY MYPI99003416A patent/MY123034A/en unknown
- 1999-08-30 KR KR1019990036219A patent/KR100674548B1/ko not_active IP Right Cessation
- 1999-08-31 US US09/387,052 patent/US6340837B1/en not_active Expired - Lifetime
- 1999-08-31 CN CNB99118338XA patent/CN1204622C/zh not_active Expired - Fee Related
-
2002
- 2002-01-22 US US10/051,009 patent/US6476479B2/en not_active Expired - Fee Related
- 2002-01-22 US US10/051,077 patent/US6441400B1/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100421240C (zh) * | 2002-11-22 | 2008-09-24 | 国际整流器公司 | 具有连接外部元件的引片的半导体装置 |
CN100454530C (zh) * | 2004-06-08 | 2009-01-21 | 罗姆股份有限公司 | 面装配型电子部件及其制造方法 |
US8105871B2 (en) | 2006-08-16 | 2012-01-31 | Fujitsu Semiconductor Limited | Semiconductor device and manufacturing method of the same |
Also Published As
Publication number | Publication date |
---|---|
CN1204622C (zh) | 2005-06-01 |
MY123034A (en) | 2006-05-31 |
SG77704A1 (en) | 2001-01-16 |
JP2000077435A (ja) | 2000-03-14 |
US6476479B2 (en) | 2002-11-05 |
US20020056904A1 (en) | 2002-05-16 |
US6441400B1 (en) | 2002-08-27 |
KR20000017634A (ko) | 2000-03-25 |
US6340837B1 (en) | 2002-01-22 |
KR100674548B1 (ko) | 2007-01-26 |
TW508702B (en) | 2002-11-01 |
US20020056905A1 (en) | 2002-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1204622C (zh) | 半导体器件及其制造方法 | |
US7948068B2 (en) | Semiconductor device having a chip mounting portion and a plurality of suspending leads supporting the chip mounting portion and each suspension lead having a bent portion | |
US7410834B2 (en) | Method of manufacturing a semiconductor device | |
JP4173346B2 (ja) | 半導体装置 | |
US6157074A (en) | Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same | |
CN1312748C (zh) | 制造半导体集成电路器件的方法 | |
US9385072B2 (en) | Method of manufacturing semiconductor device and semiconductor device | |
US7410835B2 (en) | Method for fabricating semiconductor package with short-prevented lead frame | |
CN1490870A (zh) | 引线框及其制造方法,以及用该引线框制造的半导体器件 | |
US6777262B2 (en) | Method of packaging a semiconductor device having gull-wing leads with thinner end portions | |
CN1512574A (zh) | 半导体器件及其制造方法 | |
CN1412843A (zh) | 引线框架、其制造方法及使用它的半导体器件的制造方法 | |
JP2014007363A (ja) | 半導体装置の製造方法および半導体装置 | |
CN1751390A (zh) | 包括无源器件的引线框架 | |
US20100181628A1 (en) | Semiconductor device | |
CN1457094A (zh) | 半导体器件及其制造方法 | |
JP2003282809A (ja) | 半導体装置およびその製造方法 | |
CN1435882A (zh) | 半导体装置及其制造方法 | |
CN1143371C (zh) | 模制塑料型半导体器件及其制造工艺 | |
US20100200973A1 (en) | Leadframe structure for electronic packages | |
JPH11145369A (ja) | リードフレームおよびそれを用いた半導体装置ならびにその製造方法 | |
JP2004087998A (ja) | 表面実装型半導体装置およびその製造方法 | |
JP3419898B2 (ja) | 半導体装置及びその製造方法 | |
JP3798303B2 (ja) | 半導体装置及びその製造方法 | |
JPH02181956A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050601 Termination date: 20140831 |
|
EXPY | Termination of patent right or utility model |