CN1435882A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN1435882A CN1435882A CN03103562A CN03103562A CN1435882A CN 1435882 A CN1435882 A CN 1435882A CN 03103562 A CN03103562 A CN 03103562A CN 03103562 A CN03103562 A CN 03103562A CN 1435882 A CN1435882 A CN 1435882A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 164
- 238000000034 method Methods 0.000 title claims description 40
- 239000011347 resin Substances 0.000 claims abstract description 200
- 229920005989 resin Polymers 0.000 claims abstract description 200
- 230000002093 peripheral effect Effects 0.000 claims abstract description 27
- 238000007789 sealing Methods 0.000 claims description 103
- 239000011148 porous material Substances 0.000 claims description 62
- 238000004519 manufacturing process Methods 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002245 particle Substances 0.000 abstract 4
- 239000000428 dust Substances 0.000 abstract 2
- 230000007812 deficiency Effects 0.000 abstract 1
- 238000009434 installation Methods 0.000 description 34
- 230000015572 biosynthetic process Effects 0.000 description 13
- 229910052718 tin Inorganic materials 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000007747 plating Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000006071 cream Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- 208000002513 Flank pain Diseases 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- 208000034189 Sclerosis Diseases 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910002855 Sn-Pd Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
一种半导体装置及其制造方法,在现有半导体装置中,在安装半导体装置时,在安装基板和半导体装置的安装面进入树脂溢料等垃圾,产生安装不良这一问题。在此,在作为本发明的半导体装置21中,在作为半导体装置21的安装面的树脂密封体22的内面224形成凹部25。另外,在凹部25的外周侧,引线26的露出区域和树脂密封体22的内面224,大致形成同一平面。因此,在本发明的QFN型半导体装置21中即使产生引线26溢料的碎片和树脂溢料等垃圾,也能通过使这些垃圾位于凹部25形成区域,来避免安装时的安装不良。
Description
技术领域
本发明的半导体装置是内面安装型的无引线半导体装置,它涉及一种半导体装置结构及其制造方法,用于在安装该半导体装置时降低安装不良的产生。
背景技术
半导体装置每年都在大容量化,因此,构成各种信号线的引线端子数也有增加的倾向。而且,随着这种倾向,开始使用引线端子由4个方向导出的QFP(Quad Flat Package四边扁平引线封装)型半导体装置及QFN(Quad FlatNon-leaded package四边扁平无引线封装)型半导体装置。作为这种QFP型的制造方法的一实施例,例如在特开平8-181160号公报开示。
以下参照附图,说明目前的实施例的制造方法。图12是引线架平面图,图13是金属模具立体图,图14是树脂密封后的引线架平面图。
首先,通过作为粘合剂的银膏等在图12所示的引线架1的载物台2上搭载半导体元件。半导体元件虽没有图示但在其表面具有多个电极部,搭载固定在载物台上。之后将该电极和引线端子3利用导线连接进行电气连接。
这样搭载半导体元件后,将引线架1设置在图13所示的上模7和下模8之间。之后合模形成作为注入区域的型腔。
然后,向上模7的直浇道10’,以规定压力注入熔融的树脂。树脂流进上模7的型腔及下模8,并通过横浇口11填充到型腔9,密封半导体元件。在树脂注入前,腔9内存在空气,但是在树脂进入腔内的阶段树脂将空气挤出,向气孔逃逸。然后该空气通过形成在引线架的孔5向外部逃逸。气孔在金属模具7、8形成,为不使树脂通过的程度的间隙。
填充后,在树脂冷却固化后打开金属模具,取出引线架1。图14表示在该时刻的引线架1。但是,为了容易地认出树脂的流路,将在树脂密封时存在直浇道及横浇道的部分以虚线表示。由图14可以明确,从位于四个密封区域的中央部分的直浇道部10通过浇口4流入树脂。由此,搭载于载物台的半导体元件及其周围部分的引线端子3的一部分被树脂覆盖,形成一组合件12。之后,将引线端子3的连接部分切断,根据需要将分离的各引线端子3进行弯曲加工,由此完成QFP型的半导体装置。
其次,图15是利用与所述的QFP型的半导体装置的制造方法同样的方法,形成的QFN型的半导体装置。
图15(A)是含有引线15形成部的半导体装置的断面图。如图所示,在目前的半导体装置中,半导体元件16通过银(以下称为Ag)膏等导电膏17固定在Cu框架等组成的中间凸起14上。而且半导体元件16的电极座(没有图示)和引线15通过金属细线18进行电气连接。在由Cu框架等组成的中间凸起14及引线15上形成将半导体元件16等覆盖为一体的树脂密封体19。在中间凸起14及引线15的内面侧考虑到防止氧化及焊锡湿润性而实施了镀金。利用这种结构,例如相对于安装基板(没有图示),利用焊锡安装引线15。这时,形成半导体装置的内面形成为大致具有同一平面,半导体装置稳定地安装在安装基板上。
其次,图15(B)是含有吊线13形成部的半导体装置的断面图。如图所示,在从树脂密封体19的侧面露出的吊线13的上面,树脂溢料19与树脂密封体19的侧面连续形成。这是流入到设置在金属模具的气孔部的树脂硬化形成的,形成例如30μm的程度。
发明内容
如上所述,在目前的QFN型的半导体装置中,如图15(A)所示,半导体装置的安装面侧大致具有同一平面。因此,当在将半导体装置向安装基板安装时,在基板和半导体装置的安装面之间进入树脂碎片等垃圾时,会产生安装不良。
而且如上所述,在目前的半导体装置的制造方法中,如图13所示,腔9内存在的空气被驱赶到腔9端部,通过设置在金属模具的气孔排到腔9外部。但是,通过该气孔挤出空气时,在引线架1和上模7、或者引线架1和下模8之间产生树脂溢料。然后,在将组合件12从引线架1切断时,要在固定组合件12周边部之后再切断。但是如图15(B)所示,在该固定区域,特别是在吊线13表面产生树脂溢料19A,由于该树脂溢料19A引起的凸凹,使引线3不能可靠地固定。其结果是,在形成在引线3间的树脂切断面上产生微裂纹。在其后的工序中,该微裂纹恶化,形成树脂碎片,特别是在安装工序中,会由于该树脂碎片等,诱发安装不良的问题。
另外,在目前的半导体装置的制造方法中,腔9内存在的空气被驱赶到腔9端部,通过设置在金属模具7的气孔排到腔9外部。但是,通过该气孔挤出空气时,在引线架1和上模7、或者引线架1和下模8之间产生树脂溢料。但由于该树脂溢料的厚度为30μm那样薄,所以在将组合件从金属模具6脱模时,该树脂溢料有时不与组合件整体脱模,而残留在金属模具内。由于该树脂溢料残留在金属模具内,在下次树脂铸模时,就会阻塞存在于腔9内的空气的路径。其结果是,空气不向外部排出,在腔9内被压缩残留,从而在组合件内产生空隙、未填充区域。
本发明是鉴于所述的目前的课题而开发的,本发明的半导体装置具有:至少一个中间凸起;固定在所述中间凸起表面的半导体元件;从所述中间凸起附近向外延伸的多个引线及从所述中间凸起的角部连续向外延伸的吊线;将所述中间凸起、所述半导体元件、所述引线及所述吊线整体覆盖的树脂密封体;所述引线的一端在与所述树脂密封体的内面大致同一平面露出,所述树脂密封体的内面在被所述引线的露出面包围的区域的至少一部分具有凹部。
而且,本发明的半导体装置,从所述树脂密封体露出的所述引线间硬化的树脂、及从述树脂密封体露出的所述引线和所述吊线之间硬化的树脂的厚度,与所述引线架厚度,具有大致一样的厚度。
而且,本发明的半导体装置,所述引线的一端及所述吊线的一端,在树脂密封体的安装面侧具有冲切面。
本发明是鉴于所述的目前的课题而开发的,本发明的半导体装置的制造方法包括:准备引线架,并将半导体元件固定在所述引线架的中间凸起的工序,该引线架至少具有一个搭载部,该搭载部至少由中间凸起、引线及吊线组成;将所述半导体元件和所述引线通过金属细线进行电气连接,将树脂密封体在每一个所述搭载部形成的工序;将所述引线架切断,将所述各搭载部的所述树脂密封体逐个分离的工序;在形成所述树脂密封体的工序中,以树脂密封模具夹持位于所述树脂密封体端部的所述引线架,通过气孔进行树脂的填充、空气及树脂的排出,该气孔设置在位于所述夹持的面的所述引线架上。
附图说明
图1是说明本发明半导体装置的(A)立体图(B)平面图;
图2是说明本发明半导体装置的(A)断面图(B)断面图;
图3是说明本发明半导体装置的(A)立体图(B)立体图;
图4是说明本发明半导体装置的制造方法的图;
图5是说明本发明半导体装置的制造方法的图;
图6是说明本发明半导体装置的制造方法的图;
图7是说明本发明半导体装置的制造方法的图;
图8是说明本发明半导体装置的制造方法的图;
图9是说明本发明半导体装置的制造方法的图;
图10是说明本发明半导体装置的制造方法的图;
图11是说明本发明半导体装置的制造方法的图;
图12是说明目前的半导体装置的制造方法的图;
图13是说明目前的半导体装置的制造方法的图;
图14是说明目前的半导体装置的制造方法的图;
图15是说明目前的半导体装置的(A)断面图(B)断面图。
具体实施方式
以下,参照图1~图11说明本发明的半导体装置及其制造方法。
首先,采用图1~图3说明作为本发明的一实施例的QFN型的半导体装置。
图1(A)是本发明的半导体装置的立体图,图1(B)是本发明的半导体装置的平面图。如图1(A)所示,在本实施例的半导体装置21的表面侧,中间凸起23及吊线24的一端241的一部分在树脂密封体22的表面侧221露出,树脂密封体22由构成组合件的绝缘树脂形成。另外,从树脂密封体22的侧面侧222,引线26的一端稍稍露出。如在后述的制造方法中详细说明的,作为露出区域,只要具有在将引线26从引线架41(参照图4)切断时,能由引线切断卡具固定引线26的区域即可。具体地说,从树脂密封体22露出50~200μ m的程度。另外,从露出引线26的四个侧面222各自相交的树脂密封体22的四个角侧面223,吊线24的另一端242稍稍露出。这时也与引线26的情况一样,作为露出区域,只要具有在将吊线24从引线架41切断时固定吊线24的区域即可。同样具体地说,从树脂密封体22露出50~200μm的程度。
因此,在本实施例中,通过使中间凸起23在树脂密封体22的表面221露出,能提高从半导体元件产生的热的散热性。另外,使树脂密封体22的表面221和中间凸起23及吊线24的一端241的内面,大致位于同一平面,实现了半导体装置21自身的薄型化。另外,中间凸起23的位置不必特别限定,也可以是可形成后述的凹部25的位置。
另一方面,如图1(B)所示,本实施例的半导体装置21的内面侧起着作为半导体装置21的安装区域的功能。在树脂密封体22的内面224侧的外周部,吊线24的另一端242及引线26的另一端的安装面(与安装基板的接触面)露出,与树脂密封体22的内面224大致共有同一平面。而且,在吊线24的另一端242及引线26的另一端的安装面,通过焊锡等固定材料(没有图示)安装在安装基板上。这时,在本发明的半导体装置中,吊线24的另一端242,也在树脂密封体22的内面224侧露出。利用这种结构,可使安装面积增加,能提高安装强度。因此,在树脂密封体22的内面224,将吊线24的另一端242的露出领域配制在凹部25的周围,并使其位于比引线26的露出领域更外侧。通过采用这种结构,使在树脂密封体22内面224角部的安装区域的密集缓和。可防止相互邻接的吊线24和引线26产生焊锡架桥,能将每个导线26和安装基板侧的希望的导电图形(没有图示)可靠地进行电气连接。另外,在吊线24露出领域,在安装区域的密集度缓和时,通过使吊线24露出领域增大,更能提高安装强度。这是因为,通过焊锡固定增大了的露出领域和安装基板的导电图形的缘故。
在本发明的半导体装置中,将凹部25设置在树脂密封体22的内面224上也是特征。这种结构的细节,参照图2如下进行说明。
图2(A)是图1(A)所示的本发明的半导体装置的X-X线方向的断面图。图2(B)是图1(A)所示的本发明的半导体装置的Y-Y线方向的断面图。首先如图2(A)所示,说明本实施例的半导体装置21的断面结构。如上所述,在树脂密封体22的表面221,中间凸起23露出,共有大致同一平面。在该中间凸起23露出面和对面,例如通过Ag膏等导电膏27固定半导体元件28。而且半导体元件28的电极座部(没有图示)和引线26,通过金属细线29电气连接。与该金属细线29连接的引线26的另一端261位于树脂密封体22内,该引线26的一端262露出,与树脂密封体22内面224大致共有同一平面。
而且,如上所述,作为本发明半导体装置的特征,是将凹部25设置在树脂密封体22的内面224。具体地说,在树脂密封体22的内面224,引线26的一端262露出,而且考虑半导体装置21安装时的稳定性,树脂密封体22自身具有平坦面。在比该区域更内侧,例如占树脂密封体22的内面224三分之二左右的面积形成凹部25。在本发明实施例中,该凹部25的深度以例如10~200μm的程度形成。但是,凹部25的深度,能根据半导体装置21自身的厚度、树脂密封体22内的中间凸起23的位置、以及使用目的等自由地变化。也就是说,通过具有这种结构,在将半导体装置21安装在安装基板等时,即使树脂溢料等垃圾在半导体装置21和安装基板之间存在,通过使其位于凹部25形成区域,所以也能大幅改善安装不良。另外,凹部25的形成区域,也可以同深度一样改变,还可以根据使用目的在树脂密封体22的内面224形成多个。
其次,如图2(B)所示,在本实施例的半导体装置21中,使中间凸起23从树脂密封体22的表面221露出。由此确保从半导体装置28表面到树脂密封体22的内面224的树脂厚度,在半导体装置21的安装面确保凹部25形成区域。另外,在本实施例中,使中间凸起23在树脂密封体22的表面221露出,提高了从半导体元件28产生的热的散热性。而且在本实施例中,为了使QFN型的半导体装置21的安装面积增大,使吊线24的另一端242从树脂密封体22的内面224露出。这时,如上所述,为了实现半导体装置21的安装强度的提高,使吊线24的另一端242也从树脂密封体22的内面224露出。而且,在吊线24露出的树脂密封体的角部,由于安装区域的密集造成的焊锡跨接,有时会引起短路。因此,吊线24的露出区域要考虑与角部的引线26的安装区域的密集来决定。
另外,虽没有图示,但对中间凸起23的固定区域,考虑与导电膏27的粘接性,有时也实施镀银或镀金。另外,在引线26上,考虑金属细线29的粘接性实施镀银或镀金。
其次,图3(A)是本发明的半导体装置的特征部的立体图,图3(B)是本发明的半导体装置的引线的放大图。如图3(A)所示,实际上,在从树脂密封体22露出的引线26的一端262之间,一体形成有树脂。另外,在引线26的一端262和吊线24的另一端242之间,也一体形成有树脂。这是由于,从树脂密封体22的侧面222、223露出的引线26及吊线24极少。而吊线24和引线26自身的厚度也是例如100~250μm的程度,所以,该吊线24和引线26之间的树脂22A与树脂密封体22本身一体化。而且作为本发明的半导体装置的特征,就是以吊线24、引线26及吊线24和引线26之间的树脂22A形成的外周面30大致是同一平面,并且是以同一厚度形成。在后叙的制造方法中详细说明,利用该结构,在将半导体装置21从引线架41切断时,能以引线切断卡具将吊线24、引线26可靠地固定。
而且如图3(B)所示,本发明的半导体装置的特征在于,在引线26的一端262,树脂密封体22的内面224侧具有冲切面32,引线26的溢料31产生侧位于树脂密封体22的表面221侧。若反之,溢料31发生则处于树脂密封体22的内面224侧,则在将半导体装置21安装在安装基板时,溢料3 1破碎,有可能因该破碎的溢料31引起安装不良。另外,在溢料31不破碎而残存时,树脂密封体22的内面224平坦性恶化,会使安装精度及安装强度降低。也就是说,通过具有该结构,可以提高半导体装置的安装精度及安装强度。另外,如图所示,冲切面32具有曲面。而且可以说在吊线24也一样,吊线24也具有同样的结构。
另外,在上述的说明中,说明了QFN型的半导体装置,但没有特别的限定,QFP型等其他半导体装置也能得到同样的效果。而且其他的在不脱离本发明的宗旨的范围内能有种种变化。
其次,采用图4~图10说明作为本发明一实施例的QFN型导体装置的制造方法。另外,在制造方法的说明中,与用于说明所述的半导体装置的附图及符号,采用同一图面及符号,说明同一结构要素。
第一工序,如图4及图5所示,是准备引线架的工序。
图4是用于本发明半导体装置的引线架的平面图。如图所示,用于本实施例的引线架41,由例如厚度为约100~250μm的铜为主要材料的框架构成。但是,也可以Fe-Ni为主要材料,也可以是其他金属原料。而且在引线架41上,形成多个搭载部42,该搭载部表示与以点划线所示的一个半导体装置对应的单元。在图4中,只图示4个搭载部42,但只要至少配置一个即可。该搭载部42由相对于纸面左右方向延伸的一对第一连接条体43和相对于纸面上下方向延伸的一对第二连接条体44包围。而且,利用该第一及第二连接条体43、44在一个引线架41上设置多个搭载部42。
而且,图5是将图4所示的引线架41的一个搭载部放大的平面图。具体地说,如图所示,搭载部42主要由以下组成,中间凸起23和支撑中间凸起23的吊线24、位于中间凸起23的四侧边附近,将该四边包围,向第一及第二连接条体43、44延伸的多个引线26、位于吊线24的延伸方向,吊线24和第一及第二连接条体43、44包围的区域47、设置在区域47的第一气孔45和第二气孔46。在本实施例中,在三个气孔区域47分别形成第一气孔45和第二气孔46,但只要至少在一处设置即可。另外,树脂注入口至少需要一个,在此,设置在没有形成第二气孔46的右下角区域48。另外,树脂注入口的位置,不一定必须设置在四个角部,也可以在四个角部全部的气孔形成区域47分别形成第一气孔45和第二气孔46。另外在本实施例中,将设置在引线架41的两种类型的孔分别定义为第一气孔45和第二气孔46。以下同样。
第二工序如图6所示是电气连接工序,在引线架41的中间凸起23上,将半导体元件28装片,将该半导体元件28的电极座部(没有图示)和引线26用金属细线29导线连接。
本工序在引线架41的每一个搭载部42,在中间凸起23表面由Ag膏等导电膏27将半导体元件28装片固定。之后以金属细线29连接半导体元件28的电极座部和引线26。作为所述细线例如由Au构成。这时,金属细线29利用导线连接法,球连接在电极座上,引线26侧针脚式接合连接。另外,虽没有图示,但在中间凸起23上,有时会考虑与导电膏的粘接性,也有时镀金或镀银。另外,在引线26上考虑与金属细线29的粘接性,实施镀银或镀镍。另外,根据使用用途,作为半导体元件28的粘接装置,也可用由Cu-Si箔、焊锡等焊料、绝缘材料做成的粘接件或薄模等。
第三工序如图7~图9所示,是采用树脂密封金属模具,以树脂将引线架上的每个搭载部进行铸模的工序。
图7(A)是上模内部的平面图,图7(B)是树脂铸模时的气孔形成区域部的断面图。图7(C)是浇口部的树脂注入部的断面图。
如图7(A)所示,在上模50的型腔51的各角部,与图5所示的气孔形成区域47配合形成接触面52。该接触面52起如下功能,与下模54组合,在型腔51内支撑引线架41。另外,在引线架41形成的第一及第二气孔45、46由设置在上模50的排气槽55连接。如图7(B)所示,该排气槽55覆盖使第一气孔45和第二气孔46分离的引线架21的一部分56。具体地说,排气槽55的深度例如从接触面52起为10~50μm程度。排气槽55的长度只要可以将第一气孔45和第二气孔46连接即可,是与两者稍有重合的长度。下模54上也可以与上模50一样,形成用于连接第一及第二气孔45、46的排气槽。
其次,参照图7(B)说明腔51内的空气流,特别说明在腔51的角部的空气流,腔51具有形成第一、第二气孔45、46的接触面52。如图所示,树脂铸模时,被挤入腔51内角部的空气及树脂,流入第一气孔45内。这时,引线架41的厚度例如有100~250μm程度,所以第一气孔45的深度也一样,例如有100~250μm程度。因此,向第一气孔45内,不只是腔51内的空气,树脂也一起流入。在第一气孔45内,空气集积在HL2附近,通过设置在上模50或下模54的排气槽55流向第二气孔46。这时,排气槽55例如以30~50μm程度的宽度形成。如上所述,第一气孔45由于具有100~250μm程度的深度,所以,在构成外周面30的树脂的切断面的前面,几乎不形成未填充区域。
而且,在本发明的制造方法中,如图7(C)所示,在浇口部57,也采用第一气孔45将树脂注入到腔51内。这一点也具有如下特征。如图所示,设置在上模50的浇口部57,不直接与腔51相连形成,前端部位于第一气孔45的HL2侧。因此,如箭头所示,从浇口部57流入的树脂,通过第一气孔45流入腔51内。与其它角部一样,在浇口部57,第一气孔45上面也设有上模50的接触面52。其结果是,在与树脂密封体22的侧面222、223连续形成的外周面30(参考图3)上面,不产生目前结构下的树脂溢料19A(参照图15(B)),外周面30能够大致形成同一平面。
也就是说,在本发明的制造方法中,腔51由金属模具51、54的接触面52大致密封,向腔51内的树脂注入、及向腔51外的树脂及空气的排出,通过第一气孔45进行。该结构与目前不具有与腔连续设置在金属模具的气孔及浇口部的这一点有很大的不同。因此,能将与所述树脂密封体22连续形成的外周面30,形成在大致同一平坦面,而没有树脂造成的凹凸。如上所述,通过使浇口部57也同样形成,能将所述树脂密封体22侧面的外周面30的全部,形成为大致同一平面。
通过采用所述的树脂密封金属模具50、54,如图8及图9所示,树脂密封体22形成于每一个搭载部42,覆盖引线架41。图8是表示在引线架41上形成的树脂密封体22的平面图,图9是在图8所示的搭载部42的第一及第二气孔45、46形成的树脂密封体22的平面图。通过采用图7所示的树脂密封金属模具50、54,从腔51流出的树脂至少在第一气孔45、排气槽55及第二气孔46的至少一部分硬化。因此组合件脱模时,引线架41及树脂密封体22以一体脱模。而且,腔51内的空气如图7(B)的箭头所示,可通过排气槽55,由第二气孔46向外部逃逸。利用本发明的制造方法,将腔51内的空气,排出到以图5的虚线所示的原来的树脂密封体22形成区域外部。其结果是,在第一气孔45,引线架41厚的空气通过路径能可靠确保,在树脂密封体22的端部不形成未填充区域。另外,虽没有图示,但为了在树脂密封体22的内面224侧形成凹部25,所以在下模54的腔51侧,形成与凹部25对应的凸部。
第四工序是,在从树脂密封体22露出的引线架41实施电镀的工序。
在本工序中,考虑防止引线氧化、焊锡沾湿性等,在引线架41实施电镀。这时,对形成多个搭载部42的引线架41整体实施电镀。例如,在引线架41或载置引线架41的电镀辅助架侧准备阴极、在电镀槽侧准备阳极,一次对多个引线架41实施电镀。这时,在电镀槽准备Pd、Sn、Ni、Sn-Pd、Sn-Bi、Sn-Ag、Sn-Cu、Au-Ag、Sn-Ag-Cu等电镀液,利用这些电镀液的组合,至少在引线架41镀一层电镀膜。在引线架41采用镀Pd时,采用在树脂铸模工序之前,预先实施镀Pd的引线架41。
第五工序如图10及图11所示,是将在引线架41上形成的多个半导体装置21从引线架41切断的工序。
图10是将第一及第二气孔形成区域切断的引线架的平面图。图11(A)是吊线24或引线26切断时的立体图,图11(B)是表示作为本发明特征的引线26切断时的固定区域的平面图。首先如图9所示,在所述的本发明的半导体装置的制造方法中,从腔51流出的树脂在第一气孔45内硬化。所以,在树脂密封体22附近,在包含引线架41上的外周面30上产生树脂溢料。
引线架41例如具有100~250μm程度的厚度,所以,从腔51流出的树脂在第一气孔45、排气槽55及第二气孔46内一体化硬化。就是说,第一及第二气孔45、46内的树脂,以引线架41的厚度牢固地硬化,排气槽55内的树脂与两者形成一体。因此,从腔51流出的树脂能在规定的位置使树脂硬化。其结果是,将第一及第二气孔45、46切断时,第一及第二气孔45、46间的引线架56上的树脂溢料也能全部除去。而且在切断吊线24的工序中,能以可靠地固定与树脂密封体22连续的外周面30上的状态,切断吊线24及树脂。就是说,如图3(A)所示,在外周面30上不形成由树脂造成的凹凸,所以,可用支撑装置62(参考图11)将吊线24及树脂22A可靠地固定,并将这些切断。而且切断状态是留下外周面30,在到达各侧边的引线26终端时切断,故形成如图的形状。而且,通过保留引线架41的一部分,并与第一及第二连接条43、44连接,搭载部42不从引线架41分离。
其次,如图11所示,本发明的半导体装置21是QFN型的半导体装置,在从树脂密封体22露出引线26的边界部附近将引线26切断。而且在该工序同时将各个半导体装置21从引线架41切断。如图11(A)所示,首先将实施了电镀的半导体装置21设置在台座59、60上。然后以支撑装置62将半导体装置21的引线26的露出边界部固定,另一方面,引线26的前端也以支撑装置63固定。然后用冲头64将引线26切断,使半导体装置21从引线架41独立。
而且,作为本发明半导体装置制造方法的特征,如图所示,在引线26切断时,冲头64从半导体装置21的安装面一侧进入,将引线26及其周边的树脂22A(参考图3)切断。利用这种制造方法如图3(B)所示,将引线26的冲切面32(参考图3)形成在半导体装置21的安装面一侧。另一方面,引线26的飞边31(参考图3)形成在与半导体装置21的安装面相反侧的面上。而且,具有该构造的效果,如上所述,在此就不叙述了。另外,将吊线24切断时也同样从安装面一侧切断,所以,能得到同样的效果。就是说,在本发明半导体装置中,冲切面32在安装面一侧形成。
而且,作为本发明半导体制造方法的特征,就是在切断吊线24及引线26时,要在利用支撑装置62可靠地固定引线26后用冲头64切断。如图11(B)所示在切断后的树脂密封体22附近以影线表示,例如以支撑装置62固定50~200μm程度的固定区域65。而且,由图就可以明白,还固定吊线24露出区域的周边。这时,在第三工序的树脂密封体22形成工序中,也如上所述,在与树脂密封体22的侧面222、223连续的外周面30不形成凹凸。特别是如上所述,气孔形成区域47(参考图5),在与树脂密封体22的侧面223连续的外周面30,也不产生树脂溢料。在注入树脂的浇口部57(参照图7),在外周面30上也不产生树脂溢料。因此,在本发明中,在以○标记66表示的区域,不形成目前的树脂溢料19A(参考图15(B)),在位于外周面30的固定区域65,没有树脂溢料产生的凹凸大致形成同一平面。而且如上所述,利用支撑装置62可靠地固定引线26,将引线26及其周边的树脂22A切断。其结果是,能抑制在引线26间的、及吊线24和引线26间的树脂22A切断面产生微裂纹,形成稳定的规定的形状。而且在后工序的半导体装置的特性判断工序、包装工序、安装工序中,微裂纹不生长,树脂22A不破坏。特别是在安装工序中,能够实现不会诱发树脂碎片等造成的安装不良的半导体装置。还能提高冲头64的寿命周期。之后完成图1所示的半导体装置21。
就是说,如果归纳所述的工序,在本发明的半导体装置的制造方法中,采用了夹片吊线24从树脂密封体22露出的侧面223形成第一气孔45的引线架。而且在第一气孔45形成区域,由金属模具50、54的接触面52将吊线24夹住。在该接触面52,向腔51内注入树脂,来自腔51内的空气及树脂的排出,大致只通过第一气孔45进行。因此,与树脂密封体22露出的侧面222、223连续形成的外周面30具有大致同一平面,并且在该表面不形成树脂溢料产生的凹凸。而且,由于具有该构造,所以,在将吊线24、引线26从引线架41切断时,将与树脂密封体22侧面连续的外周面以引线切断卡具的支撑装置62可靠地固定并切断。其结果是,能最大限度地抑制切断时在外周面30的树脂22A产生微裂纹,随之能最大限度地抑制半导体装置21的安装不良。
另外,在本实施例中,对本发明半导体制造方法说明了形成两个气孔的情况,但不必特别限定。只要具有至少与腔连续的第一气孔,就能得到同样的效果。另外,采用预先实施了镀敷的引线等时,也能得到同样的效果。而且,在不脱离本发明的宗旨的范围内,可以有其他种种变化。
第一,根据本发明半导体装置,具有以下特征,在作为半导体装置的安装面的树脂密封体的内面,在除去引线露出的外周部的安装区域的区域,形成凹部。因此,在半导体装置安装时,即使在安装基板和半导体装置的安装面进入树脂溢料等垃圾,通过使所述垃圾位于凹部形成区域,也能大幅改善产生安装不良的概率。
第二,根据本发明半导体装置,具有以下特征,使从树脂密封体侧面露出的吊线及其附近的树脂厚度,以与吊线大致同一厚度形成。因此,能将吊线及其附近的树脂的上面形成大致同一平面,在切断引线时,能作为引线固定区域采用。其结果是,能使引线及其附近的树脂的切断面稳定。
第三,根据本发明半导体装置,具有以下特征,将引线的一端在半导体装置的安装面露出。因此,能使半导体装置的安装面积增加,能提高安装强度。
第四,根据本发明半导体装置,从与半导体装置的安装面相反的面即树脂密封体表面,露出中间凸起。因此使从半导体元件产生的热从中间凸起直接扩散到外部,能提高散热性。
第五,根据本发明半导体装置的制造方法,在树脂密封体形成工序中,将树脂向腔内的注入、来自腔内的空气及树脂的排出,大致只通过形成在引线架的第一气孔进行。因此在与树脂密封体的侧面连续形成的外周面上,能够形成没有树脂溢料造成的凹凸的大致同一的平坦面。
第六,根据本发明半导体装置的制造方法,其特征在于,从引线架将各个半导体装置切断时,将树脂密封体和从树脂密封体侧面露出的引线的边界附近可靠地固定并切断。因此能使引线及引线周边的树脂的切断面稳定。其结果是,能抑制在位于切断面的树脂产生微裂纹,也能抑制该裂纹的生长造成的树脂垃圾,能大幅降低产生半导体装置安装不良等的可能性。
第七,根据本发明半导体装置的制造方法,其特征在于,将引线、吊线及其周边的树脂切断时,从半导体装置的安装面侧切断。因此这三者的冲切面形成在安装面一侧。另一方面,这三者的溢料形成在与安装面相反的面侧。其结果是,在半导体装置的安装面不形成凹凸,能提高半导体装置的安装精度及稳定性。
Claims (15)
1.一种半导体装置,其特征在于,其包括:至少一个中间凸起;
固定在所述中间凸起表面的半导体元件;
从所述中间凸起附近向外延伸的多个引线及从所述中间凸起的角部连续向外延伸的吊线;
将所述中间凸起、所述半导体元件、所述引线及所述吊线整体覆盖的树脂密封体,
所述引线的一端在与所述树脂密封体的内面大致同一平面露出,所述树脂密封体的内面,在被所述引线的露出面包围的区域的至少一部分具有凹面。
2.权利要求书1所述的半导体装置,其特征在于,在从所述树脂密封体露出的所述引线间硬化的树脂、及从述树脂密封体露出的所述引线和所述吊线之间硬化的树脂的厚度,具有与所述引线架厚度大致相同的厚度。
3.权利要求书2所述的半导体装置,其特征在于,由所述引线、所述吊线及所述硬化树脂的表面构成的外周面,与所述树脂密封体侧面连续形成,所述外周面将所述树脂密封体包围,大致是同一平坦面。
4.如权利要求书1至权利要求书3任一项所述的半导体装置,其特征在于,所述引线的一端及所述吊线的一端,在所述树脂密封体的内面侧具有冲切面。
5.权利要求书1所述的半导体装置,其特征在于,所述中间凸起内面位于所述树脂密封体的表面,所述中间凸起内面至少一部分从所述树脂密封体的表面露出,所述中间凸起内面和所述树脂密封体的表面大致形成同一平面。
6.权利要求书1所述的半导体装置,其特征在于,所述吊线一端的内面在与所述树脂密封体的内面大致同一平面的角部露出。
7.权利要求书6所述的半导体装置,其特征在于,所述吊线的露出面相对于所述凹部位于外侧,并且位于比所述引线的露出面更外侧。
8.一种半导体装置,其特征在于,其包括:至少一个中间凸起;
固定在所述中间凸起表面的半导体元件;
从所述中间凸起附近向外延伸的多个引线及从所述中间凸起的角部连续向外延伸的吊线;
将所述中间凸起、所述半导体元件、所述引线及所述吊线整体覆盖的树脂密封体,
从所述树脂密封体露出的所述引线间硬化的树脂、及从所述树脂密封体露出的所述引线和所述吊线之间硬化的树脂的厚度具有与所述引线架厚度大致一样的厚度。
9.权利要求书8所述的半导体装置,其特征在于,由所述引线、所述吊线及所述硬化树脂的表面构成的外周面与所述树脂密封体侧面连续形成,所述外周面将所述树脂密封体包围,大致是同一平坦面。
10.权利要求书8或权利要求书9所述的半导体装置,其特征在于,所述引线的一端及所述吊线的一端,在所述树脂密封体的内面侧具有冲切面。
11.权利要求书8所述的半导体装置,其特征在于,所述中间凸起内面位于所述树脂密封体的表面,所述中间凸起内面至少一部分从所述树脂密封体的表面露出,所述中间凸起内面和所述树脂密封体的表面大致形成同一平面。
12.权利要求书7所述的半导体装置,其特征在于,所述吊线一端的内面在与所述树脂密封体的内面大致同一平面的角部露出。
13.权利要求书12所述的半导体装置,其特征在于,所述吊线的露出面相对于所述凹部位于外侧,并且位于所述引线露出面的更外侧。
14.一种半导体装置的制造方法,其特征在于,包括:准备引线架,并将半导体元件固定在所述引线架的中间凸起上的工序,该引线架至少具有一个搭载部,该搭载部至少由中间凸起、引线及吊线组成;
将所述半导体元件和所述引线通过金属细线进行电气连接,按每一个所述搭载部形成树脂密封体的工序;
将所述引线架切断,将所述各搭载部的所述树脂密封体逐个分离的工序;
在形成所述树脂密封体的工序中,以树脂密封模具将位于所述树脂密封体端部的所述引线架夹住,通过气孔进行树脂的填充、空气及树脂的排出,所述气孔设置在位于所述夹持的面的所述引线架上。
15.权利要求书14所述的半导体装置的制造方法,其特征在于,在将所述树脂密封体分离的工序中,将所述引线及所述吊线从所述树脂密封体的内面冲切。
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JP2002020297A JP2003224239A (ja) | 2002-01-29 | 2002-01-29 | 半導体装置およびその製造方法 |
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JP (1) | JP2003224239A (zh) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102246262A (zh) * | 2008-11-17 | 2011-11-16 | 派希斯系统整合私人有限公司 | 用于密封半导体裸片的方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6856006B2 (en) | 2002-03-28 | 2005-02-15 | Siliconix Taiwan Ltd | Encapsulation method and leadframe for leadless semiconductor packages |
US6891256B2 (en) * | 2001-10-22 | 2005-05-10 | Fairchild Semiconductor Corporation | Thin, thermally enhanced flip chip in a leaded molded package |
JP3805338B2 (ja) * | 2003-11-07 | 2006-08-02 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP2006086273A (ja) * | 2004-09-15 | 2006-03-30 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
JP5054923B2 (ja) * | 2006-01-23 | 2012-10-24 | Towa株式会社 | 電子部品の樹脂封止成形方法 |
US7642638B2 (en) * | 2006-12-22 | 2010-01-05 | United Test And Assembly Center Ltd. | Inverted lead frame in substrate |
JP4987041B2 (ja) * | 2009-07-27 | 2012-07-25 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2011091145A (ja) * | 2009-10-21 | 2011-05-06 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP6116817B2 (ja) * | 2012-04-27 | 2017-04-19 | ラピスセミコンダクタ株式会社 | 樹脂封止方法および半導体装置の製造方法 |
JP6063690B2 (ja) * | 2012-10-01 | 2017-01-18 | 株式会社ニコン | 中空パッケージ用容器及びその製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5293065A (en) * | 1992-08-27 | 1994-03-08 | Texas Instruments, Incorporated | Lead frame having an outlet with a larger cross sectional area than the inlet |
JPH06209054A (ja) * | 1993-01-08 | 1994-07-26 | Mitsubishi Electric Corp | 半導体装置 |
US5559366A (en) * | 1994-08-04 | 1996-09-24 | Micron Technology, Inc. | Lead finger tread for a semiconductor lead package system |
US6388338B1 (en) * | 1995-04-28 | 2002-05-14 | Stmicroelectronics | Plastic package for an integrated electronic semiconductor device |
JPH08181160A (ja) | 1994-12-26 | 1996-07-12 | Fujitsu Ltd | 半導体装置の製造方法 |
US6072239A (en) * | 1995-11-08 | 2000-06-06 | Fujitsu Limited | Device having resin package with projections |
CA2180807C (en) * | 1996-07-09 | 2002-11-05 | Lynda Boutin | Integrated circuit chip package and encapsulation process |
JP2907186B2 (ja) * | 1997-05-19 | 1999-06-21 | 日本電気株式会社 | 半導体装置、その製造方法 |
JP2915892B2 (ja) * | 1997-06-27 | 1999-07-05 | 松下電子工業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
KR100350046B1 (ko) * | 1999-04-14 | 2002-08-24 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 방열판이 부착된 반도체패키지 |
JP2000332162A (ja) * | 1999-05-18 | 2000-11-30 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
JP2001035961A (ja) * | 1999-07-21 | 2001-02-09 | Sony Corp | 半導体装置及びその製造方法 |
JP2001068613A (ja) * | 1999-08-27 | 2001-03-16 | Sony Corp | 半導体装置及びその製造方法 |
JP2001085574A (ja) * | 1999-09-09 | 2001-03-30 | Aoi Electronics Co Ltd | 樹脂封止半導体装置及びモールド装置 |
JP3733114B2 (ja) * | 2000-07-25 | 2006-01-11 | 株式会社メヂアナ電子 | プラスチックパッケージベース及びエアキャビティ型パッケージ |
JP3660861B2 (ja) * | 2000-08-18 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
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CN102246262A (zh) * | 2008-11-17 | 2011-11-16 | 派希斯系统整合私人有限公司 | 用于密封半导体裸片的方法 |
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US20030143779A1 (en) | 2003-07-31 |
KR20030065385A (ko) | 2003-08-06 |
KR100679598B1 (ko) | 2007-02-08 |
TW584949B (en) | 2004-04-21 |
CN1307718C (zh) | 2007-03-28 |
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US7119424B2 (en) | 2006-10-10 |
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