JP2003224239A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

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Publication number
JP2003224239A
JP2003224239A JP2002020297A JP2002020297A JP2003224239A JP 2003224239 A JP2003224239 A JP 2003224239A JP 2002020297 A JP2002020297 A JP 2002020297A JP 2002020297 A JP2002020297 A JP 2002020297A JP 2003224239 A JP2003224239 A JP 2003224239A
Authority
JP
Japan
Prior art keywords
resin
lead
semiconductor device
island
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002020297A
Other languages
English (en)
Japanese (ja)
Inventor
Akira Ochiai
公 落合
Toshiyuki Take
俊之 武
Tetsuya Fukushima
哲也 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2002020297A priority Critical patent/JP2003224239A/ja
Priority to TW91135129A priority patent/TW584949B/zh
Priority to CNB031035620A priority patent/CN1307718C/zh
Priority to KR20030005701A priority patent/KR100679598B1/ko
Priority to US10/352,859 priority patent/US6893903B2/en
Publication of JP2003224239A publication Critical patent/JP2003224239A/ja
Priority to US10/872,454 priority patent/US7119424B2/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2002020297A 2002-01-29 2002-01-29 半導体装置およびその製造方法 Pending JP2003224239A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2002020297A JP2003224239A (ja) 2002-01-29 2002-01-29 半導体装置およびその製造方法
TW91135129A TW584949B (en) 2002-01-29 2002-12-04 Semiconductor device and manufacturing method thereof
CNB031035620A CN1307718C (zh) 2002-01-29 2003-01-29 半导体装置及其制造方法
KR20030005701A KR100679598B1 (ko) 2002-01-29 2003-01-29 반도체 장치 및 그 제조 방법
US10/352,859 US6893903B2 (en) 2002-01-29 2003-01-29 Semiconductor device and method for manufacturing the same
US10/872,454 US7119424B2 (en) 2002-01-29 2004-06-22 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002020297A JP2003224239A (ja) 2002-01-29 2002-01-29 半導体装置およびその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005210905A Division JP4225990B2 (ja) 2005-07-21 2005-07-21 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JP2003224239A true JP2003224239A (ja) 2003-08-08

Family

ID=27606271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002020297A Pending JP2003224239A (ja) 2002-01-29 2002-01-29 半導体装置およびその製造方法

Country Status (5)

Country Link
US (2) US6893903B2 (zh)
JP (1) JP2003224239A (zh)
KR (1) KR100679598B1 (zh)
CN (1) CN1307718C (zh)
TW (1) TW584949B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086273A (ja) * 2004-09-15 2006-03-30 Dainippon Printing Co Ltd 樹脂封止型半導体装置
JP2007194558A (ja) * 2006-01-23 2007-08-02 Towa Corp 電子部品の樹脂封止成形方法と金型及びリードフレーム
JP2009246395A (ja) * 2009-07-27 2009-10-22 Renesas Technology Corp 半導体装置の製造方法
JP2011091145A (ja) * 2009-10-21 2011-05-06 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2013232544A (ja) * 2012-04-27 2013-11-14 Lapis Semiconductor Co Ltd 樹脂封止方法および半導体装置の製造方法
JP2014072830A (ja) * 2012-10-01 2014-04-21 Nikon Corp 中空パッケージ用容器及びその製造方法

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US6856006B2 (en) * 2002-03-28 2005-02-15 Siliconix Taiwan Ltd Encapsulation method and leadframe for leadless semiconductor packages
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
JP3805338B2 (ja) * 2003-11-07 2006-08-02 沖電気工業株式会社 半導体装置及びその製造方法
US7642638B2 (en) * 2006-12-22 2010-01-05 United Test And Assembly Center Ltd. Inverted lead frame in substrate
WO2010056212A2 (en) * 2008-11-17 2010-05-20 Pyxis Systems Integration Pte Ltd Method for encapsulating semiconductor dies

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US5293065A (en) * 1992-08-27 1994-03-08 Texas Instruments, Incorporated Lead frame having an outlet with a larger cross sectional area than the inlet
JPH06209054A (ja) * 1993-01-08 1994-07-26 Mitsubishi Electric Corp 半導体装置
US5559366A (en) * 1994-08-04 1996-09-24 Micron Technology, Inc. Lead finger tread for a semiconductor lead package system
US6388338B1 (en) * 1995-04-28 2002-05-14 Stmicroelectronics Plastic package for an integrated electronic semiconductor device
JPH08181160A (ja) 1994-12-26 1996-07-12 Fujitsu Ltd 半導体装置の製造方法
US6072239A (en) * 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
CA2180807C (en) * 1996-07-09 2002-11-05 Lynda Boutin Integrated circuit chip package and encapsulation process
JP2907186B2 (ja) * 1997-05-19 1999-06-21 日本電気株式会社 半導体装置、その製造方法
JP2915892B2 (ja) * 1997-06-27 1999-07-05 松下電子工業株式会社 樹脂封止型半導体装置およびその製造方法
KR100350046B1 (ko) * 1999-04-14 2002-08-24 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 방열판이 부착된 반도체패키지
JP2000332162A (ja) * 1999-05-18 2000-11-30 Dainippon Printing Co Ltd 樹脂封止型半導体装置
JP2001035961A (ja) * 1999-07-21 2001-02-09 Sony Corp 半導体装置及びその製造方法
JP2001068613A (ja) * 1999-08-27 2001-03-16 Sony Corp 半導体装置及びその製造方法
JP2001085574A (ja) * 1999-09-09 2001-03-30 Aoi Electronics Co Ltd 樹脂封止半導体装置及びモールド装置
JP3733114B2 (ja) * 2000-07-25 2006-01-11 株式会社メヂアナ電子 プラスチックパッケージベース及びエアキャビティ型パッケージ
JP3660861B2 (ja) * 2000-08-18 2005-06-15 株式会社ルネサステクノロジ 半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086273A (ja) * 2004-09-15 2006-03-30 Dainippon Printing Co Ltd 樹脂封止型半導体装置
JP2007194558A (ja) * 2006-01-23 2007-08-02 Towa Corp 電子部品の樹脂封止成形方法と金型及びリードフレーム
JP2009246395A (ja) * 2009-07-27 2009-10-22 Renesas Technology Corp 半導体装置の製造方法
JP2011091145A (ja) * 2009-10-21 2011-05-06 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2013232544A (ja) * 2012-04-27 2013-11-14 Lapis Semiconductor Co Ltd 樹脂封止方法および半導体装置の製造方法
JP2014072830A (ja) * 2012-10-01 2014-04-21 Nikon Corp 中空パッケージ用容器及びその製造方法

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KR100679598B1 (ko) 2007-02-08
TW200302559A (en) 2003-08-01
KR20030065385A (ko) 2003-08-06
US6893903B2 (en) 2005-05-17
US20040222513A1 (en) 2004-11-11
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