CN102246262A - 用于密封半导体裸片的方法 - Google Patents

用于密封半导体裸片的方法 Download PDF

Info

Publication number
CN102246262A
CN102246262A CN2009801493287A CN200980149328A CN102246262A CN 102246262 A CN102246262 A CN 102246262A CN 2009801493287 A CN2009801493287 A CN 2009801493287A CN 200980149328 A CN200980149328 A CN 200980149328A CN 102246262 A CN102246262 A CN 102246262A
Authority
CN
China
Prior art keywords
sealant
seal isolation
isolation body
hole
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2009801493287A
Other languages
English (en)
Inventor
阿蒙兰森
许振源
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pyxis Systems Integration Pte Ltd
Original Assignee
Pyxis Systems Integration Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pyxis Systems Integration Pte Ltd filed Critical Pyxis Systems Integration Pte Ltd
Publication of CN102246262A publication Critical patent/CN102246262A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

本发明描述用于密封半导体裸片的两个方法(200,400)。两个方法(200,400)涉及将具有一个或多于一个孔(104,304)的密封隔离体(102,302,302a,302b)附接在相关联的衬底(150)上,从而一组芯片(160)被定位在所述孔(104,304)中。第一方法(200)涉及将密封剂(103)直接分配到孔中。第二方法(400)涉及将密封剂传输层(350,351)附接到所述密封隔离体上,并通过凹进浇口(308)将密封剂排入孔中。

Description

用于密封半导体裸片的方法
相关申请
一份对应的PCT专利申请与本案在同一天递交,但该PCT专利申请涉及用于密封半导体裸片的系统。
技术领域
本发明涉及用于密封半导体裸片的方法,其省去了与喷射模塑法或传递模塑法相关联的型腔模具(cavity mould)。特别是,本发明涉及一种将密封剂排入由设置在相关联的衬底或载体上的密封隔离体限定的型腔中的方法。
背景技术
传统的用于半导体裸片封装的方法涉及粘片过程、打线过程、密封模塑过程、打磨过程和切割过程。传递模塑法典型地用于密封一组半导体裸片以及相应的与导电衬底的打线互连以形成半导体封装体。在所述过程中,导电衬底与打线的裸片一起被放置在分裂型腔(split cavity)的下模板中。通过在衬底的周界处于分裂模板的中间时将上模板夹持到下模板上、将液化的密封剂注入到型腔中并允许密封剂固化,裸片被物理密封并不受外部环境的影响。通过切割塑性封装体,得到单独的半导体芯片。
由于在输送密封剂时所使用的高压,打线中的一些可能被移位或移动为与邻近的打线接触。其它问题在于将贮存池、流槽、浇口和通气口设计为给出足以符合无空隙密封的密封剂流动特性。这些模具是昂贵的且需要不断的清洁以从模具内的通道中移除密封剂。
因此可见,存在对克服现有技术缺点的新的用于密封半导体裸片的系统和方法的需求。
发明内容
下文提出简单总结以提供对本发明的基本理解。该总结不是本发明的广义概述,并不致力于确定本发明的关键特征。而是以概括的形式提出本发明的一些发明概念,作为随后的详细描述的前序。
本发明通过去除与喷射模塑法或传递模塑法相关联的型腔模具而寻求一种简单且成本低廉的用于密封半导体裸片的系统和方法;实际上,制造用于密封隔离体的工具的成本低于用于制造传统的型腔模具的成本。在本发明中,具有简单的滚筒(platen)和压盘(pressure plate)的小巧简单的压机(press)(例如4柱压机)足以用于本发明。在型腔模具的情况下,这些工具通常为简单且平坦的金属部件并避免对不断清洁的需要,并且在使用本发明时这转变到更高的生产力。
在一个实施例中,本发明提供一种用于密封半导体裸片的方法。该方法包括:将密封隔离体(102,302)附接在在一衬底上,在该衬底上附接有一些半导体裸片,从而根据在所述衬底上的导电图案设置的一组裸片通过所述密封隔离体(102,302)上的孔(104,304)被看见;将密封剂分配到所述孔中;以及使所述密封剂固化。
附图说明
将参照附图通过本发明的非限制性实施例对本发明进行描述,附图中:
图1A例示出根据本发明一实施例的密封系统;
图1B例示出根据在图1A中所示的密封系统的一实施例的密封隔离体;
图2A-2G例示出在使用图1A中所示的密封系统时涉及的各个步骤;
图3A例示出根据本发明另一实施例的密封系统;
图3B例示出根据在图3A中所示的密封系统的一实施例的密封隔离体,图3C例示出与图3B中所示的密封隔离体一起使用的密封剂输送层;
图3D例示出根据图3A中所示的密封系统的另一实施例的密封隔离体,图3E例示出与图3D中所示的密封隔离体一起使用的密封剂输送层;
图4A-4F例示出在使用图3A中所示的密封系统时的各个步骤。
具体实施方式
现在将参照所附附图描述本发明的一个或多于一个特定且可替换的实施例。然而,对于本领域技术人员来说明显的是,本发明可在没有这种特定细节的情况下实施。一些细节可能没被详细地描述以不会使本发明变得晦涩。为了易于参照,当参照附图中共有的相同或相似的特征时,在全部附图中将使用共用的附图标记或成系列的附图标记。
图1A示出根据本发明一实施例的密封系统100。如图1A中所示,密封系统100由附接到半导体衬底或载体150的密封隔离体102组成。一个或多于一个半导体裸片或芯片160根据衬底/载体上的导电图案附接到衬底/载体150上。裸片/芯片160可为被打线的器件,衬底150为相关联的布线板,比如QFN导线架、柔性衬底、球栅衬底等。密封隔离体102具有多个通孔104。为了描述简单,图1A示出简单的具有一排孔104的密封隔离体102,其中,当密封隔离体102附接到衬底/载体150时,一组裸片/芯片160位于每个孔104内。沿着每个孔104的一侧或多侧存在过流贮存池110。孔104的厚度根据待密封的裸片/芯片160的高度和裸片/芯片顶部的溢出物的量而预先确定。每个过流贮存池110通过通气口114连接到相应的孔104。通过用密封剂103填充孔104、对密封剂施加热和压力以最小化其中的任何空隙空间、允许密封剂固化然后将密封的裸片/芯片切割成单独的封装体,密封系统100提供一种简单且成本低廉的用于形成半导体封装体的方法。
密封隔离体102不必为如图1A中所示的板的形式。在另一实施例中,密封隔离体形成为单独的密封环102的形式。图1B示出密封环102形成为四边形形状,但其在形状上不限于此。如在先前的实施例中,过流贮存池110通过通气口114连接到密封环102的内部。
在密封环102的另一实施例中,存在另外的过流贮存池110a。在一个实施例中,该另外的过流贮存池110a被定位为与过流贮存池110相对。在另一实施例中,该另外的过流贮存池110a为圆形形状,并被定位在密封环的与过流贮存池110相对的角部。在又一实施例中,密封环102具有两种类型的这种另外的过流贮存池110a和相关联的通气口114a。
在一个实施例中,密封隔离体102由金属制成。在另一实施例中,密封隔离体由热塑性塑料制成。密封隔离体可通过传统的机加工、模塑、蚀刻、激光切割或成形方法形成。例如,密封隔离体102可通过对金属片(优选由铜制成)蚀刻而制成。在另一示例中,密封隔离体102可通过掩饰处理一金属片并利用金属(比如铜)对该金属片电镀来形成暴露的金属片而制成。密封隔离体的材料不限于此;可使用任何其他的低成本且易于通过传统的机加工或成形而形成的材料。
在图1A和图1B中,密封隔离体/环102被示出包括单层。在另一实施例中,密封隔离体/环102包括两个或多于两个层,其中相邻的层可利用粘合剂结合。通气口114、114a和过流贮存池110、110a的深度可由组成密封隔离体/环102a的相关层的厚度限定。本实施例的优点在于,形成密封隔离体102的层或者为纯实心的或具有孔104;由此,密封隔离体102的高度可根据待密封的裸片160而配置。
在使用时,密封隔离体102、102a可利用粘合剂安装在衬底150上。图2A至图2G例示出使用上述密封隔离体/环102、102a密封半导体裸片/芯片的过程200。如图2A中所示,裸片/芯片160的组根据衬底上的导电图案被安装210在衬底150上。在图2B中,密封隔离体/环102、102a利用粘合剂118被安装220在衬底150上。然后,密封剂103被分配230到密封隔离体102、102a的每个孔104中或密封环102、102a的内部,直到密封剂103到达密封隔离体/环102、102a的顶部并将通过相应的通气口114、114a过流到过流贮存池110、110a中。密封剂的分配可手动执行或通过配量系统自动地执行。如图2D中所示,在孔被填充后,压力可被施加240到密封剂的表面上。然后,覆盖板130被施加250在密封隔离体/环102、102a的顶部上以覆盖密封剂103。然后,整个组件被设置260在压机内,在该压机中,根据密封环102、102a的孔104或密封环102、102a的内部而确定形状和尺寸的滚筒向密封剂103施加265热和压力。所述热和压力可保持预定时间以允许密封剂103至少部分地固化。图2G示出在过程100的最后被密封到密封隔离体102、102a的孔104内的在衬底150上的裸片160。然后,整个组件可被设置在烘炉内以完全固化密封剂103。在密封剂103完全固化之后,密封的裸片/芯片被切割以形成单独的半导体封装体。
图3A示出根据本发明另一实施例的密封系统300。密封系统300由衬底/载体150、密封隔离体302和密封剂输送层350组成。如图3A中所示,密封隔离体302附接到衬底/载体150,密封剂输送层350相应地附接到密封隔离体302;这种附接可利用粘合剂118。当描述密封系统300的各个部件时,本发明更加清楚。
图3B示出根据本发明一实施例的密封隔离体302。密封隔离体302被例示为细长带,该细长带具有多个孔304。在图3B中,为了更简单的描述,孔304沿细长带的较长尺寸方向排列成一排,但它们不限于此。如同在先前的实施例中,一组半导体裸片/芯片160附接到衬底/载体150,从而裸片/芯片在孔304中被看见,并且密封隔离体302的在孔处的厚度限定围绕裸片/芯片160的密封剂的厚度。
如图3B中所示,在细长带的较短尺寸方向上有四个缺口(relief)320。缺口320的尺寸适于例如在密封剂固化后在密封隔离体302将从衬底/载体150剥离时或者在密封剂输送层350将从密封隔离体302剥离时,提供供四指和拇指抓持的空间。
如图3B中所见,密封隔离体302的右手侧具有比左手侧更大的边缘。在右手边缘中,封闭的假想线306示出在密封剂输送层350附接到密封隔离体302时密封剂103贮存在密封剂输送层350中的位置。如在图3B中所见的在密封隔离体302的后侧的凹进浇口308从封闭的假想线306的内部延伸到相关联的孔304。由另一个假想线限定的平面309穿过凹进浇口308。密封隔离体302的在平面309的右手侧的区域可在密封剂被输送到孔304中且已至少部分地固化之后被断开或切断。如在图3B中所见,在每个孔304的左侧和后侧存在过流贮存池310。通气口314将每个过流贮存池310连接到相应的孔304。
在一个实施例中,密封隔离体302由单层制成。例如,当密封隔离体302是金属制时,形成的层可通过将金属电镀在衬底上而沉积而成,而凹陷或孔可通过掩饰处理和蚀刻暴露的金属表面而形成。在另一实施例中,密封隔离体302a由两个或多于两个层组成;相邻的层可利用粘合剂结合;在另一示例中,相邻的层可层压到一起;凹进浇口308、通气口314和过流贮存池310的深度可由组成密封隔离体302a的相关层的厚度限定。
图3C示出与密封隔离体302、302a一起使用的根据本发明一实施例的密封剂输送层350。如图3A中所示,密封剂输送层350的尺寸适于与密封隔离体302、302a匹配,其中密封剂贮存在贮存池352中。密封输送层350由薄且柔性的塑料组成,但足够坚韧和有弹性以将密封剂保持在贮存池352中。在一示例中,可通过传统的塑料模塑(比如喷射模塑法或传递模塑法)来制造密封剂输送层350。在使用前,密封剂输送层350可由一剥离层覆盖;通过移除该剥离层,密封剂输送层350上的粘合剂被暴露,然后密封剂输送层350可附接到密封隔离体302、302a上。在使用时,密封系统300被放置在压机内,贮存池352上的压力使贮存池塌缩以通过凹进浇口308将密封剂输送到相关联的孔304中,从而密封设置在衬底/载体150上的裸片/芯片160。在围绕裸片/芯片的密封剂已固化之后,密封剂输送层350可被剥离;可替换地,密封隔离体304、304a与密封输送层350一起可在平面309处被断开或切断。
图3D示出根据本发明另一实施例的密封隔离体302b。密封隔离体302b与密封隔离体302、302a相似,不同之处在于凹进浇口308起始于凹进308a。每个凹进308a对应于在图3E中所示的匹配的密封剂输送层351上的分散的密封剂贮存池353。在另一实施例中,围绕凹进308a的区域的形状和尺寸可适于与相关联的密封剂贮存池353重叠,并且围绕凹进浇口308的区域足以依附到密封剂输送层351以允许密封剂被输送到孔304中,从而围绕凹进308a和凹进浇口308的材料是多余的;该多余的材料在被移除时形成开口324。
图4A至图4F例示出使用密封隔离体302、302a、302b密封半导体裸片的过程400。如图4A中所示,裸片160的组根据衬底上的导电图案被安装410到衬底150上。在图4B中,密封隔离体302、302a、302b例如通过粘合剂被安装420到衬底上。在图4C中,密封剂输送层350、351的贮存池或罐装容器352、353被密封剂103填充430。然后在图4D中,密封剂输送层350、351附接到密封隔离体302、302a、302b。然后,整个组件或系统300被设置在压机内,在该压机中,根据孔304确定形状和尺寸的滚筒将热和压力施加440到密封剂103。随后,如图4E中所示,例如通过使压头延伸在贮存池/罐装容器上而使密封剂输送层350、351的贮存池或罐装容器352、353塌缩450。如图4F中所示,所述热和压力可保持预定时间以允许密封剂103至少部分地固化。在密封剂固化且组件从压机移除之后,密封隔离体302、302a、302b和密封剂输送层350、351在密封的裸片被切割以形成单独的半导体封装体之前沿平面309被断开或切断460。可替换地,密封剂输送层350、351在切割以形成单独的半导体封装体之前被移除。
尽管已经描述并例示出特定的实施例,但应该理解,可在不脱离本发明的范围的情况下作出本发明的许多改变、修改、变型和组合。例如,密封隔离体102、102a、302、302a、302b可具有设置在每个过流贮存池110、110a、310旁边的真空通道111、311。每个真空通道111、311可具有用于在需要时连接到真空系统的真空端口312;然后,可在密封剂输送层350、351上提供对应于真空端口312的真空开口362。控制浇口315将过流贮存池连接到相关联的真空通道311。尽管已描述了密封系统300的板布置,但系统300同样适用于与单独的密封环和密封剂输送层351一起使用。

Claims (17)

1.一种用于密封(200,400)半导体裸片的方法,包括:
将密封隔离体(102,302)附接在一衬底上,在该衬底上附接有一些半导体裸片,从而根据在所述衬底上的导电图案设置的一组裸片通过所述密封隔离体(102,302)上的孔(104,304)被看见;
将密封剂分配到所述孔中;以及
使所述密封剂固化。
2.根据权利要求1所述的方法,其中,所述孔的形状和尺寸能根据所述衬底上的所述导电图案来配置。
3.根据权利要求1或2所述的方法,进一步包括使所述密封剂通过通气口从所述孔过流到过流贮存池中,从而所述孔被完全填充,并且空隙空间被最小化。
4.根据权利要求1至3中任一项所述的方法,其中,所述密封剂被直接分配到所述孔中,并且所述密封剂的分配手动执行或通过配量系统自动地执行。
5.根据权利要求4所述的方法,进一步包括将覆盖层设置在分配在所述孔中的所述密封剂的顶部上。
6.根据权利要求1至3中任一项所述的方法,其中,通过将密封剂传输层附接到所述密封隔离体上以及使设置在所述密封剂传输层中的密封剂的贮存池/罐状容器塌缩来执行所述密封剂的分配。
7.根据权利要求6所述的方法,其中,所述密封剂通过形成在所述密封隔离体上的凹进浇口从所述密封剂传输层传输。
8.根据权利要求4至7中任一项所述的方法,进一步包括将热和压力施加在设置在所述孔中的所述密封剂上。
9.根据权利要求8所述的方法,进一步包括保持施加在所述密封剂上的所述热和压力预定时间,以至少部分地固化所述密封剂。
10.根据权利要求9所述的方法,进一步包括将所述衬底、密封隔离体和密封剂设置在烘炉中,并使所述密封剂完全固化。
11.根据权利要求10所述的方法,进一步沿着剪切平面(309)断开所述密封隔离体和密封剂传输层。
12.根据权利要求10或11所述的方法,进一步包括将所述密封隔离体与所述衬底分离,将所述覆盖层与所述密封隔离体分离和/或将所述密封剂传输层与所述密封隔离体分离。
13.根据权利要求12所述的方法,其中,通过在所述密封隔离体的周界边缘上提供缺口,更易于实现将所述密封隔离体与所述衬底分离或者将所述覆层和密封剂传输层与所述密封隔离体分离。
14.根据权利要求1至13中任一项所述的方法,其中,所述密封隔离体由单层构成。
15.根据权利要求1至13中任一项所述的方法,其中,所述密封隔离体包括两个或多于两个层,并且相邻的层利用粘合剂结合。
16.根据权利要求2至15中任一项所述的方法,其中,所述密封隔离体进一步包括设置在相关联的过流贮存池旁边的真空通道,并且所述真空通道通过控制浇口连接到所述相关联的过流贮存池。
17.根据权利要求16所述的方法,其中,所述孔、凹进浇口、过流贮存池、通气口、真空通道或控制浇口的深度能根据所述密封隔离体的相关层的厚度来配置。
CN2009801493287A 2008-11-17 2009-11-17 用于密封半导体裸片的方法 Pending CN102246262A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11550508P 2008-11-17 2008-11-17
US61/115,505 2008-11-17
PCT/SG2009/000430 WO2010056212A2 (en) 2008-11-17 2009-11-17 Method for encapsulating semiconductor dies

Publications (1)

Publication Number Publication Date
CN102246262A true CN102246262A (zh) 2011-11-16

Family

ID=42170577

Family Applications (2)

Application Number Title Priority Date Filing Date
CN200980149327.2A Active CN102246261B (zh) 2008-11-17 2009-11-17 用于密封半导体裸片的系统
CN2009801493287A Pending CN102246262A (zh) 2008-11-17 2009-11-17 用于密封半导体裸片的方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN200980149327.2A Active CN102246261B (zh) 2008-11-17 2009-11-17 用于密封半导体裸片的系统

Country Status (4)

Country Link
US (2) US20110281403A1 (zh)
CN (2) CN102246261B (zh)
TW (2) TWI515842B (zh)
WO (2) WO2010056212A2 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61101054A (ja) * 1984-10-24 1986-05-19 Hitachi Micro Comput Eng Ltd 半導体装置およびその製造方法
US6080354A (en) * 1997-05-01 2000-06-27 Apic Yamada Corporation Resin molding method in which a movable cavity piece allows a direct resin feed
US6214640B1 (en) * 1999-02-10 2001-04-10 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages
US6469382B1 (en) * 2000-01-28 2002-10-22 Nec Corporation Semiconductor device substrate and method of manufacturing semiconductor device
CN1435882A (zh) * 2002-01-29 2003-08-13 三洋电机株式会社 半导体装置及其制造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3754846A (en) * 1972-01-21 1973-08-28 Cpi Inc Apparatus for single cavity injection molding of oil seals
US4843036A (en) * 1987-06-29 1989-06-27 Eastman Kodak Company Method for encapsulating electronic devices
NL8802879A (nl) * 1988-11-22 1990-06-18 Ireneus Johannes Theodorus Mar Werkwijze voor het verpakken van een afgepaste, voor het omhullen van een component bestemde hoeveelheid thermohardende kunststof, met deze werkwijze verkregen verpakking, werkwijze voor het bedrijven van een matrijs en matrijs voor het uitvoeren van deze werkwijze.
KR100199261B1 (ko) * 1990-04-27 1999-06-15 가나이 쓰도무 반도체장치 및 그 제조방법 그리고 그것에 사용되는 성형장치
EP0470559A1 (de) 1990-08-07 1992-02-12 Siemens Aktiengesellschaft Verfahren zur Montage von integrierten Halbleiterschaltkreisen
FR2673017A1 (fr) * 1991-02-18 1992-08-21 Schlumberger Ind Sa Procede de fabrication d'un module electronique pour carte a memoire et module electronique ainsi obtenu.
NL9200127A (nl) * 1992-01-23 1993-08-16 Ireneus Johannes Theodorus Mar Werkwijze voor het in een vormholte persen van een door een reactie uithardende kunststof, een daarbij te gebruiken pilvormig pershulpmateriaal alsmede een houder uit dergelijk materiaal.
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
NL9302265A (nl) * 1993-12-24 1995-07-17 Asm Fico Tooling Werkwijze en pellet voor het omhullen van leadframes en inrichting voor het vervaardigen van pellets.
NL9400119A (nl) * 1994-01-27 1995-09-01 3P Licensing Bv Werkwijze voor het met een hardende kunststof omhullen van een electronische component, electronische componenten met kunststofomhulling verkregen door middel van deze werkwijze en matrijs voor het uitvoeren der werkwijze.
EP0730937B1 (en) * 1994-11-21 1998-02-18 Apic Yamada Corporation A resin molding machine with release film
EP0742586A3 (en) * 1995-05-02 1998-03-11 Texas Instruments Incorporated Improvements in or relating to integrated circuits
US6531083B1 (en) * 1995-05-02 2003-03-11 Texas Instruments Incorporated Sproutless pre-packaged molding for component encapsulation
US5888443A (en) * 1996-05-02 1999-03-30 Texas Instruments Incorporated Method for manufacturing prepackaged molding compound for component encapsulation
US6060779A (en) 1997-04-30 2000-05-09 Shinko Electric Industries, Co., Ltd. Resin sealed ceramic package and semiconductor device
US6071457A (en) * 1998-09-24 2000-06-06 Texas Instruments Incorporated Bellows container packaging system and method
JP3194917B2 (ja) * 1999-08-10 2001-08-06 トーワ株式会社 樹脂封止方法
FR2809229B1 (fr) 2000-05-22 2002-12-13 St Microelectronics Sa Moule d'injection anti-bavure d'un materiau d'encapsulation d'une puce de circuits integres
JP2002026187A (ja) * 2000-07-07 2002-01-25 Sony Corp 半導体パッケージ及び半導体パッケージの製造方法
KR20030027413A (ko) * 2001-09-28 2003-04-07 삼성전자주식회사 칩 사이에 스페이서가 삽입된 멀티 칩 패키지와 그 제조방법
JP3790705B2 (ja) * 2001-12-27 2006-06-28 新光電気工業株式会社 配線基板およびこれを用いた半導体装置の製造方法
TWI327756B (en) * 2002-11-29 2010-07-21 Apic Yamada Corp Resin molding machine
JP5166870B2 (ja) * 2005-05-30 2013-03-21 スパンション エルエルシー 半導体装置の製造装置及び半導体装置の製造方法
US20070141751A1 (en) * 2005-12-16 2007-06-21 Mistry Addi B Stackable molded packages and methods of making the same
JP2008004570A (ja) 2006-06-20 2008-01-10 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置の製造方法、樹脂封止型半導体装置の製造装置、および樹脂封止型半導体装置
US7833456B2 (en) 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61101054A (ja) * 1984-10-24 1986-05-19 Hitachi Micro Comput Eng Ltd 半導体装置およびその製造方法
US6080354A (en) * 1997-05-01 2000-06-27 Apic Yamada Corporation Resin molding method in which a movable cavity piece allows a direct resin feed
US6214640B1 (en) * 1999-02-10 2001-04-10 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages
US6469382B1 (en) * 2000-01-28 2002-10-22 Nec Corporation Semiconductor device substrate and method of manufacturing semiconductor device
CN1435882A (zh) * 2002-01-29 2003-08-13 三洋电机株式会社 半导体装置及其制造方法

Also Published As

Publication number Publication date
WO2010056212A2 (en) 2010-05-20
TWI502653B (zh) 2015-10-01
CN102246261A (zh) 2011-11-16
TWI515842B (zh) 2016-01-01
US20110281403A1 (en) 2011-11-17
US20110271902A1 (en) 2011-11-10
TW201030861A (en) 2010-08-16
US9082775B2 (en) 2015-07-14
WO2010056211A3 (en) 2010-07-15
TW201030906A (en) 2010-08-16
CN102246261B (zh) 2015-08-12
WO2010056211A2 (en) 2010-05-20
WO2010056212A3 (en) 2010-08-12

Similar Documents

Publication Publication Date Title
US10629787B2 (en) Lid and an optical device package having the same
CN101266934B (zh) 制造多个半导体器件的方法和设备
US10573537B2 (en) Integrated circuit package mold assembly
CN102810488A (zh) 半导体传感器装置及其封装方法
EP0971401A3 (en) Method of manufacturing semiconductor devices and a resin molding machine therefor
CN102246262A (zh) 用于密封半导体裸片的方法
CN102214635A (zh) 半导体封装结构及其制作方法
JP6034078B2 (ja) プリモールドリードフレームの製造方法、および、半導体装置の製造方法
CN103021902A (zh) 半导体封装铸模装置及方法
JP2006269786A (ja) 樹脂封止金型、それを用いた樹脂封止装置、および、樹脂封止方法
JP4202632B2 (ja) 一括封止型半導体パッケージの樹脂封止構造およびその製造装置
CN101150076A (zh) 半导体封装件制法与半导体元件定位结构及方法
KR100304680B1 (ko) 반도체장치및그제조방법
CN112397400A (zh) 半导体封装方法
CN110421752B (zh) 待封装pcb板、防溢胶的塑封模具及塑封方法
JP3857608B2 (ja) 加飾付き樹脂成形品の製造方法
TWI467705B (zh) 電子元件承載件以及封裝及分開電子元件之方法
KR100526846B1 (ko) 반도체패키지용 금형
JP6468455B1 (ja) 樹脂封止金型及び樹脂封止方法
CN111863772B (zh) 定位方法、封装组件及封装结构
CN213752629U (zh) 一种智能功率模块的封装系统
US20230067918A1 (en) Leadframe-less laser direct structuring (lds) package
CN109545694B (zh) 一种破损基板的模封方法
CN107180768B (zh) 指纹辨识封装结构的制作方法以及制作设备
JP3499269B2 (ja) カバーフレームと樹脂封止方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20111116