CN1244953C - 薄膜晶体管阵列基板及其制造方法 - Google Patents
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Abstract
一种薄膜晶体管阵列基板,包括:薄膜晶体管的栅极、与栅极相连的选通线,以及与选通线相连的栅焊盘;源/漏极图形,包含薄膜晶体管的源极和漏极、与源极相连的数据线、与数据线相连的数据焊盘、与数据线相交叠的存储电极;形成于基板较低部位的半导体图形;透明电极图形,包含与漏极和存储电极相连的像素电极、覆盖栅焊盘的栅焊盘保护电极以及覆盖数据焊盘的数据焊盘保护电极;以及在除形成有透明电极图形的区域之外的区域中层叠的保护图形和栅绝缘图形。
Description
本申请要求2002年12月12日提交的第10-2002-88323号韩国专利申请的优先权,在此全文引入作为参考。
技术领域
本发明涉及一种薄膜晶体管阵列基板及其制造方法,特别是涉及一种可以减少掩模工序次数的薄膜晶体管阵列基板及其制造方法。
背景技术
通常,液晶显示器通过利用电场调整液晶的透光率来显示图像。为了达到这个目的,液晶显示器包括:液晶显示屏,液晶单元按矩阵形式排列在其中;和驱动电路,用于驱动液晶显示屏。
液晶显示屏包括:彼此面对的薄膜晶体管阵列基板和滤色器阵列基板;用于在两基板间保持指定单元间隙的隔片;以及填入单元间隙中的液晶。
薄膜晶体管阵列基板包括:选通线和数据线、形成于选通线和数据线的各个交叉点处并用作开关装置的薄膜晶体管、与液晶单元形成的薄膜晶体管相连接的像素电极,以及布于其上的配向膜。选通线和数据线通过各个焊盘部从驱动电路接收信号。薄膜晶体管响应于施加给选通线的扫描信号,把施加在数据线上的像素电压信号施加给像素电极。
滤色器阵列基板包括:由液晶单元形成的滤色器、用于反射外部光并分隔滤色器的黑色基底(black matrix)、用于向液晶单元提供参考电压的公共电极,以及布于其上的配向膜。
液晶显示屏包括特制的薄膜晶体管阵列基板和滤色器阵列基板,液晶注入在其中,随后将该显示屏密封。对于此液晶屏,薄膜晶体管阵列基板包括半导体工序和多次掩模工序。从而,制造过程十分复杂,而且这也是液晶显示屏制造成本上涨的主要原因。为了解决上述问题,改进了薄膜晶体管阵列基板以便减少掩模工序的次数。采用这种措施的原因是一道掩模工艺包括了很多子工序,比如蒸镀工序、清洗工序、光刻工艺、蚀刻工艺、去胶工序以及检测工序。近来,已出现4道掩模工艺来替代传统的5道掩模工艺。
图1显示的是采用掩模工序的薄膜晶体管阵列基板的平面图,图2显示的是图1所示的薄膜晶体管阵列基板沿直线I-I’的剖视图。
图1和图2中所示的薄膜晶体管阵列基板包括:形成在下基板42上的选通线2和数据线4,二者彼此交叉,并且在其间置有栅绝缘膜;在各个交叉点处形成的薄膜晶体管6;以及交叉点处的单元区域中形成的像素电极18。薄膜晶体管阵列基板还包括:在像素电极18与前一个选通线2的交叠部分形成的存储电容20、与选通线2相连的栅焊盘部分26,以及与数据线4相连的数据焊盘部分34。
薄膜晶体管6包括:与选通线2相连的栅极8、与数据线4相连的源极10、与像素电极18相连的漏极12,以及在源极10和与栅极8交叠的漏极12之间形成沟道的有源层14。有源层14与数据焊盘36、存储电极22、数据线4、源极10和漏极12相交叠,并且还包括源极10和漏极12之间的沟道部分。在有源层14上还形成了数据焊盘36、存储电极22、数据线4、源极10、漏极12,以及用于进行欧姆接触的欧姆接触层48。该薄膜晶体管6响应于施加给选通线2的选通信号,在像素电极18处提供施加在数据线4上的像素电压信号。
像素电极18通过穿透保护膜50的第一接触孔16与薄膜晶体管6的漏极12相连。当向像素电极18提供像素电压时,在像素电极18与形成在上基板(图中未显示)上的公共电极之间产生电势差。通过该电势差,位于薄膜晶体管基板和上基板之间的液晶由于介电各向异性而产生旋转,使来自光源(图中未显示)的入射光通过像素电极18射向上基板。
存储电容20包括:前一级选通线2、交叠在选通线2上的存储电极、栅绝缘膜44、有源层14、位于其间的欧姆接触层48,以及通过形成于保护膜50上的第二接触孔24相连的存储电极22。此外电容20与存储电极22交叠于保护膜50上。该存储电容20使得向像素电极18提供的像素电压保持恒定,直到向其提供下一个像素电压。
选通线2通过栅焊盘部分26与选通驱动器(图中未显示)相连。栅焊盘部分26包括:从选通线2引出的栅焊盘28;和栅焊盘保护电极32,其通过穿透栅绝缘膜44和保护膜50的第三接触孔30与栅焊盘28相连。
数据线4通过数据焊盘部分34与数据驱动器(图中未显示)相连。数据焊盘部分34包括:从数据线4引出的数据焊盘36;和数据焊盘保护电极40,其通过穿透保护膜50的第四接触孔38与数据焊盘36相连。
具有这种结构的薄膜晶体管阵列基板可以通过4道掩模工艺来制造。
图3a和图3d显示的是这种薄膜晶体管阵列基板的制造方法的剖视图。
参照图3a,在下基板42上形成栅图形。
在下基板42上,通过诸如溅镀方法之类的蒸镀方法来形成栅极金属层。随后,利用第一掩模,通过光刻工艺和蚀刻工艺来形成栅极金属层的图形,从而形成包括选通线2、栅极8和栅焊盘28的栅图形。作为栅极金属,可以使用铬(Cr)、钼(Mo)、铝(Al)等等形成单层或双层结构。
参照图3b,在形成了栅图形的下基板42上,还相继形成栅绝缘膜44、有源层14、欧姆接触层48和源/漏极图形。
在通过诸如PECVD、溅镀等的蒸镀方法形成有栅图形的下基板42上,相继形成栅绝缘膜44、非晶硅层、n+非晶硅层和源/漏极金属层。
在源/漏极金属层上,利用第二掩模,由光刻工艺形成光刻胶图形。其中,对于第二掩模,使用了在薄膜晶体管的沟道部分中具有衍射曝光部分的衍射曝光掩模(diffraction exposure mask)。沟道部分的光刻胶图形的高度低于其它源/漏极部分的高度。
随后,利用光刻胶图形,由湿法蚀刻工艺对源/漏极金属层进行构图,形成包含数据线4、源极10、与源极10合为一体的漏极12以及存储电极22的源/漏极图形。
然后,利用相同的光刻胶图形,由干法蚀刻工艺对n+非晶硅层和非晶硅层同时进行构图,从而形成欧姆接触层48和有源层14。
在沟道部分中,在通过灰化工艺去除具有相对较低高度的光刻胶图形之后,通过干法蚀刻工艺蚀刻沟道部分的源/漏极图形和欧姆接触层48。这样,暴露出了沟道部分的有源层14,并分开了源极10和漏极12。
随后,通过剥离工艺除去存在于源/漏图形部分上的光刻胶图形。
作为栅绝缘膜44的材料,使用了诸如氧化硅(SiOx)或氮化硅(SiNx)之类的无机绝缘材料。作为源/漏极金属,使用了钼(Mo)、钛(Ti)、钽(Ta)、钼合金等金属。
参照图3c,在形成有源/漏极图形的栅绝缘膜44上,形成了包括第1至第4接触孔16、24、30和38的保护膜50。
在形成有源/漏极图形的栅绝缘膜44上,通过诸如PECVD之类的蒸镀方法来整体形成保护膜50。利用第3掩模,由光刻工艺和蚀刻工艺对保护膜50进行构图,形成第1至第4接触孔16、24、30、38。第1接触孔16穿透保护膜50,并且露出漏极12。第2接触孔24穿透保护膜50,并且露出存储电极22。第3接触孔30穿透保护膜50和栅绝缘膜44,并且露出栅焊盘28。第4接触孔38穿透保护层50,并且露出数据焊盘6。
作为保护膜50的材料,使用了和栅绝缘膜44类似的无机绝缘材料或者丙稀基有机化合物、BCB和PFCB之类的具有低介电系数的有机绝缘材料。
参照图3d,在保护膜50上形成透明电极图形。
在保护膜50上,通过诸如溅镀之类的蒸镀方法来整体蒸镀透明电极材料。随后,利用第4掩模,由光刻工艺和蚀刻工艺对透明电极材料进行构图,形成包括像素电极18、栅焊盘保护电极32和数据焊盘保护电极4的透明电极图形。像素电极18通过第1接触孔16与漏极12电连接,并通过第2接触孔24和与前一级选通线2交叠的存储电极电连接。栅焊盘保护电极32通过第3接触孔30与栅焊盘28电连接。数据焊盘保护电极40通过第4接触孔38与数据焊盘36电连接。作为透明电极材料,使用了铟锡氧化物(ITO)、锡氧化物(TO)或铟锌氧化物(IZO)。诸如此类的现有技术薄膜晶体管基板及其制造方法通过采用与先前使用的5道掩模工艺相对的4道掩模工艺来减少制造工序次数。此外,这也可以适当地降低制造成本。但是,由于4道掩模工艺的制造过程依然十分复杂,成本降低的余地也就有限。这就需要一种薄膜晶体管基板及其制造方法,以通过进一步简化制造过程来进一步降低制造成本。
发明内容
据此,本发明的一个优点是提供了一种可以减少掩模工序次数的薄膜晶体管阵列基板及其制造方法。
因而,本发明旨在一种可以减少掩模工序次数的薄膜晶体管阵列基板及其制造方法,以基本消除由现有技术的限制和缺点导致的一个或多个问题。
本发明的一个优点是提供了一种薄膜晶体管阵列基板,它包括:栅图形、源/漏极图形、半导体图形、透明电极图形,以及保护图形和栅绝缘图形。其中,栅图形在薄膜晶体管阵列基板上包括薄膜晶体管的栅极、与栅极相连的选通线以及与选通线相连的栅焊盘;源/漏图形包括薄膜晶体管的源极和漏极、与源极相连的数据线、与数据线相连的数据焊盘、与数据线交叠形成的存储电极;半导体图形位于对应于源/漏极图形的较低部位;透明电极图形包括与漏极和存储电极相连的像素电极、可覆盖栅焊盘的栅焊盘保护电极,以及可覆盖数据焊盘的数据焊盘保护电极;保护图形和栅绝缘图形层叠在除透明电极图形所在区域以外的其它区域中。
保护图形部分地露出漏极和存储电极,并与像素电极相连。
该薄膜晶体管阵列基板的制造方法包括:利用第一掩模工序在基板上形成薄膜晶体管的栅极、与栅极相连的选通线、包含与选通线相连的栅焊盘的栅图形;在形成有栅图形的基板上形成栅绝缘膜;利用第二掩模工序在栅绝缘膜上形成薄膜晶体管的源极和漏极、与源极相连的数据线、与数据线相连的数据焊盘、包含与选通线交叠区域中的存储电极的源/漏极图形,以及位于较低部位的与源/漏极图形对应的半导体图形;以及利用第三掩模工序形成与漏极和存储电极相连的像素电极、用于覆盖栅焊盘的栅焊盘保护电极、包含用于覆盖数据焊盘的数据焊盘保护电极的透明电极图形,以及层叠在除透明电极图形所在区域以外的其它区域的栅绝缘图形和保护膜图形。
第二掩模工序在薄膜晶体管的沟道部分中使用了具有衍射曝光部分的衍射曝光掩模。
第二掩模工序包括:在栅绝缘膜上相继形成半导体层和源/漏极金属层;利用衍射曝光掩模形成光刻胶图形,其中薄膜晶体管的沟道部分的高度低于源/漏极图形部分的高度;利用光刻胶图形对源/漏极金属层和半导体层进行构图;灰化光刻胶图形至指定深度;利用灰化后的光刻胶图形来除去薄膜晶体管沟道部分的源/漏极金属层;以及通过剥离工艺去除光刻胶图形。
第三掩模工序包括:在形成有源/漏极图形的基板上形成保护膜;利用第三掩模形成光刻胶图形;利用光刻胶图形对保护膜和绝缘膜进行构图,从而形成栅绝缘图形和保护膜图形;在存在光刻胶图形的基板上蒸镀透明电极材料;以及通过剥离工艺去除光刻胶图形及其上的透明电极材料,从而形成透明电极图形。
保护膜图形部分地露出漏极和存储电极,并与像素电极相连。
本发明的其他特征和优点将在随后的说明中进行阐述,一部分可以通过说明书而明了,或者可以通过本发明的实践而体验到。通过说明书、权利要求书和附图中具体指出的结构,可以实现或获得本发明的这些和其它优点。
可以理解,前面的概述和下面的详细描述都是示例性和说明性的,旨在为权利要求所限定的本发明提供进一步的解释。
附图说明
附图帮助更好地理解本发明,并构成本申请的一部分,附图显示了本发明的实施例,并与说明书一起解释本发明的原理。
图中:
图1显示的是常规薄膜晶体管阵列基板的一部分的平面图;
图2显示的是图1所示的薄膜晶体管阵列基板沿线I-I’的剖视图;
图3a到3d是剖视图,解释图2所示的薄膜晶体管阵列基板的制造方法;
图4显示的是根据本发明实施例的薄膜晶体管阵列基板的平面图;
图5显示的是图4所示的薄膜晶体管阵列基板沿线II-II’的剖视图;以及
图6a到8d是剖视图,解释了根据本发明多个实施例的薄膜晶体管阵列基板的制造方法。
具体实施方式
现在对本发明的一些实施例进行详细的介绍,其实例示出在附图中。
下面参照图4到图8d,对本发明的实施例进行详细的说明。
图4显示的是根据本发明实施例的薄膜晶体管阵列基板的平面图,图5显示的是图4所示的薄膜晶体管阵列基板沿线II-II’的剖视图。
图4和图5所示的薄膜晶体管阵列基板包括:在下基板88上以特定间距与数据线58和栅绝缘图形90交叉的选通线52、在各个交叉点处形成的薄膜晶体管80,以及位于由交叉结构形成的单元区域中的像素电极72。该薄膜晶体管阵列基板还包括:与像素电极72相连的存储电极66、由前一级选通线52的交叠部分形成的存储电容78、与选通线52相连的栅焊盘部分82,以及与数据线58相连的数据焊盘部分84。
薄膜晶体管80包括:与选通线52相连的栅极54、与数据线58相连的源极60、与像素电极72相连的漏极62,以及包含有源层92的半导体图形;其中有源层92在源极60和漏极62之间形成沟道70,并且交叠在栅极54和栅绝缘图形90上。薄膜晶体管80响应于提供给选通线52的选通信号,并且使经过数据线58提供给像素电极72的像素电压信号保持恒定。
半导体图形包括位于源极60和漏极62之间的沟道部分,并且与源极60、漏极62、数据线58和数据焊盘64相交叠。它使栅绝缘图形90与存储电极66相交叠,并且包括与选通线52部分交叠的有源层92。半导体图形还包括源极60、漏极62、存储电极66、数据线58,以及在有源层92上与数据焊盘64形成欧姆接触的欧姆接触层66。
像素电极72与暴露于保护膜图形98外部的薄膜晶体管80的漏极相连。通过充电的像素电压,像素电极72与上基板(图中未显示)上的公共电极之间产生电压差。通过该电压差,位于薄膜晶体管基板与上基板之间的液晶由于介电各向异性而产生旋转,使光源(图中未显示)的入射光通过像素电极72而穿过上基板。
存储电容78与前一级选通线52、栅绝缘图形90、有源层92和欧姆接触孔94按一定间隔或距离相交叠,并与暴露于保护膜98外部的存储电极66相连。存储电容78使充入像素电极72的像素电压保持恒定,直至向其充入下一像素电压。
数据线52通过栅焊盘80与选通驱动器(图中未显示)相连。栅焊盘部分82包括从选通线52引出的栅焊盘56和连接在栅焊盘56上的栅焊盘保护电极74。
数据线58通过数据焊盘84与数据驱动器(图中未显示)相连。数据焊盘部分84包括从数据线58引出的数据焊盘64和连接在数据焊盘64上的数据焊盘保护电极76。而且,数据焊盘部分84还包括形成于数据焊盘64和下基板88之间的栅绝缘图形90,有源层92以及欧姆接触层94。
栅绝缘图形90和保护膜图形98形成于未形成像素电极72、栅焊盘保护电极74和数据焊盘保护电极76的区域中。
具有此结构的薄膜晶体管阵列基板由3道掩模工艺形成。根据本发明实施例的使用3道掩模工艺的薄膜晶体管阵列基板的制造方法包括:形成栅图形的第一掩模工序,形成半导体图形和源/漏极图形的第二掩模工序,以及形成栅绝缘图形90、保护膜图形98和透明电极图形的第三掩模工序。
图6a到图8d分别循序显示了根据本发明实施例的薄膜晶体管阵列基板的制造方法的平面图和剖视图。
图6a和6b显示了形成在下基板88上的栅图形的平面图和剖视图,这是根据本发明优选实施例的薄膜晶体管阵列基板制造方法中的第一掩模工序。
通过诸如溅镀法的蒸镀方法在下基板88上形成栅极金属层。随后,利用第一掩模,由光刻工艺和蚀刻工艺进行栅极金属层的构图。然后形成包含选通线52、栅极54和栅焊盘56的栅图形。作为栅极金属,可以使用Cr、MoW、Cr/Al、Cu、Al(Nd)、Mo/Al、Mo/Al(Nd)、Cr/Al(Nd)等形成单层结构或双层结构。
图7a到图7c显示了由根据本发明实施例的薄膜晶体管阵列基板制造方法中的第二掩模工序形成的包含源/漏极图形和半导体图形的基板的平面图和剖视图。
更具体来说,在形成有栅图形的下基板88上,通过诸如PECVD、溅镀等的蒸镀方法相继形成栅绝缘层90a、非晶硅层、n+非晶硅层和源/漏极金属层。作为栅绝缘层90a的材料,使用了诸如氧化硅(SiOx)或氮化硅(SiNx)之类的无机绝缘材料。作为源/漏极材料,使用了钼、钛、钽、钼合金等金属。
随后,如图7b所示,利用第二掩模由光刻工艺和蚀刻工艺形成光刻胶图形71b。其中,作为第二掩模,利用在薄膜晶体管的沟道部分内具有衍射曝光部分的衍射曝光掩模,使得沟道部分的光刻胶图形的高度比源/漏极图形部分的更低。
接着,参照图7c,利用光刻胶图形71b,通过湿法蚀刻工艺,对源/漏极金属层进行构图,从而形成包含数据线58、源极60、漏极62和源极60的源/漏极图形,以及存储电极64。
然后利用同一光刻胶图形71b,通过干法蚀刻工艺,同时对n+非晶硅层和非晶硅层进行构图,从而形成欧姆接触层94和有源层92。
在沟道部分中,在通过灰化工艺将具有较低高度的光刻胶图形71a去除之后,通过干法蚀刻工艺来蚀刻沟道部分的源/漏极图形和欧姆接触层94。这样露出了沟道部分的有源层92,并且分隔了源极60和漏极62。
随后,通过剥离工艺将存在于源/漏极图形部分的光刻胶图形去除。
图8a到图8d显示的是由根据本发明实施例的薄膜晶体管阵列基板制造方法中的第三掩模工序形成的包含栅绝缘图形90、保护膜图形98和透明电极图形的基板的平面图和剖视图。
更具体来说,在通过溅镀之类的蒸镀方法形成有源/漏极图形的栅绝缘膜90a上、在整体地蒸镀有诸如SiNx、SiOx或低介电系数的丙稀基有机化合物之类的无机绝缘材料或者诸如BCB或PFCB之类的有机绝缘材料的保护膜98a上,以及在保护膜98a上整体地涂布光刻胶。随后,如图8b所示,利用第三掩模,通过光刻工艺形成光刻胶图形71c。而后,利用光刻胶图形71c作为掩模,对保护膜98a和栅绝缘膜90a进行构图;随后在除形成了透明电极图形的区域之外的剩余区域中形成栅绝缘图形90和保护膜98。随后,如图8c所示,在存在光刻胶图形71c的基板88上,通过诸如溅镀之类的蒸镀方法来蒸镀透明电极材料74a。作为透明电极材料74a,使用了铟锡氧化物(ITO)、锡氧化物(TO)或铟锌氧化物(IZO)。在蒸镀有透明电极材料74a的薄膜晶体管阵列基板中,利用剥落法,通过剥离工艺去除光刻胶图形71c。此时,当去除光刻胶图形71c时,蒸镀于光刻胶图形71c上的透明电极材料74a也被一起去除;并且如图8d所示,形成了包含栅焊盘保护电极74、像素电极72和数据焊盘保护电极76的透明图形。
栅焊盘保护电极74覆盖栅焊盘56,并且像素电极72与薄膜晶体管的漏极62和存储电容78的存储电极66电连接,数据焊盘保护电极76与数据焊盘64电连接。
综上所述,根据本发明的薄膜晶体管阵列基板及其制造方法可以通过简化基板结构以及采用3道掩模工艺的制造工序来进一步降低制造成本,从而可以提高生产效率。
特别是,根据本发明的薄膜晶体管阵列基板及其制造方法通过剥离工艺形成透明电极图形,在栅绝缘膜和保护膜的构图处理中和其上的透明电极的构图处理中使用同一个光刻胶图形,从而可以减少掩模工序的次数。
对于本领域的技术人员,很明显,在不脱离本发明的精神或范围的情况下,能对本发明进行多种改进和变化。因此,如果这些改进和变化落在所附权利要求及其等同物的范围内,则本发明涵盖这些改进和变化。
Claims (7)
1.一种薄膜晶体管阵列基板,包括:
栅图形,包括:
薄膜晶体管的栅极;
与栅极相连的选通线;以及
与选通线相连的栅焊盘;
源/漏极图形,包括:
薄膜晶体管的源极和漏极;
与源极相连的数据线;以及
与数据线相连的数据焊盘;
与选通线交叠的存储电极;
位于基板的对应于源/漏极图形并处于其下方的区域中的半导体图形;
透明电极,其包含与漏极和存储电极相连的像素电极、覆盖栅焊盘的栅焊盘保护电极以及覆盖数据焊盘的数据焊盘保护电极;以及
保护图形和栅绝缘图形,其层叠在除形成有透明电极图形的区域之外的区域中。
2.根据权利要求1所述的薄膜晶体管阵列基板,其特征在于保护图形部分地露出漏极和存储电极,并与像素电极相连。
3.一种薄膜晶体管阵列基板的制造方法,包括:
利用第一掩模工序在基板上形成包括薄膜晶体管的栅极、与栅极相连的选通线以及与选通线相连的栅焊盘在内的栅图形;
在形成有栅图形的基板上形成栅绝缘膜;
利用第二掩模工序在栅绝缘膜上形成包括薄膜晶体管的源极和漏极、与源极相连的数据线以及与数据线相连的数据焊盘在内的源/漏图形、与选通线相交叠的区域中的存储电极,以及对应于源/漏极图形并处于其下方的半导体图形;以及
利用第三掩模工序形成包括与漏极和存储电极相连的像素电极、覆盖栅焊盘的栅焊盘保护电极以及覆盖数据焊盘的数据焊盘保护电极在内的透明电极图形,以及在除形成有透明电极图形的区域之外的区域中层叠的栅绝缘图形和保护膜图形。
4.根据权利要求3所述的薄膜晶体管阵列基板制造方法,其特征在于第二掩模工序采用了在薄膜晶体管的沟道部分中具有衍射曝光部分的衍射曝光掩模。
5.根据权利要求3所述的薄膜晶体管阵列基板制造方法,其特征在于第二掩模工序包括:
在栅绝缘膜上相继形成半导体层和源/漏极金属层;
利用衍射曝光掩模在薄膜晶体管沟道部分的高度低于源/漏极图形部分的地方形成光刻胶图形;
利用光刻胶图形对源/漏极金属层和半导体层进行构图;
灰化光刻胶图形至指定深度;
利用灰化后的光刻胶图形去除薄膜晶体管的沟道部分的源/漏极金属层;以及
通过剥离工艺去除光刻胶图形。
6.根据权利要求3所述的薄膜晶体管阵列基板制造方法,其特征在于第三掩模工序包括:
在形成有源/漏极图形的基板上形成保护膜;
利用第三掩模形成光刻胶图形;
利用保护膜图形形成栅绝缘图形和保护膜图形,并利用光刻胶图形形成绝缘膜;
在存在光刻胶图形的基板上蒸镀透明电极材料;以及
通过剥离工艺去除光刻胶图形并去除透明电极材料来形成透明电极图形。
7.根据权利要求3所述的薄膜晶体管阵列基板制造方法,其特征在于保护膜图形部分地露出漏极和存储电极并与像素电极相连。
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US7411217B2 (en) | 2008-08-12 |
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US20070051955A1 (en) | 2007-03-08 |
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US20040129943A1 (en) | 2004-07-08 |
TW200424639A (en) | 2004-11-16 |
KR100904270B1 (ko) | 2009-06-25 |
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JP2004310043A (ja) | 2004-11-04 |
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