CN1199277C - 深亚微米互补型金属氧化半导体的交指形状多层电容器结构 - Google Patents

深亚微米互补型金属氧化半导体的交指形状多层电容器结构 Download PDF

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CN1199277C
CN1199277C CNB018008445A CN01800844A CN1199277C CN 1199277 C CN1199277 C CN 1199277C CN B018008445 A CNB018008445 A CN B018008445A CN 01800844 A CN01800844 A CN 01800844A CN 1199277 C CN1199277 C CN 1199277C
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T·索拉蒂
V·瓦图亚
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Koninklijke Philips NV
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    • H—ELECTRICITY
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Abstract

电容器包含：第一层面的导电平行线；至少一个第二个层面的导电平行线，放置在第一层面之上，第一和第二层面的线被安排在垂直的排中；放置在第一和第二层面的导线之间的介电层；至少一个连接每排的线的交点，藉此形成垂直的电容器的平行阵列电容器板；和形成电容器的端子的电相反的节点，平行阵列的垂直电容器板以交替的方式电连接到相对节点以便板有交替的电极性。

Description

深亚微米互补型金属氧化半导体的交指形状多层电容器结构
本发明涉及在金属氧化物-半导体(MOS)中的电容器结构，和特别地，涉及深亚微米CMOS(互补型金属氧化半导体)的交指形状多层(IM)电容器结构，该电容器结构通过穿越多个层面中的导线互相连接以构造一个平行阵列的垂直电容器板来形成，和以交替方式互相连接这些板到那相对节点以便板有交替的电极性。
用于深亚微米CMOS的传统电容器结构典型地为用一薄电介质层分开的二个平坦的平行板结构。板由数层导电材料形成，例如金属或多晶硅。电容器结构通常被一个在下面的电介质层来与基体相隔离。为了要在这些装置中达成高电容量密度，附加的板被提供。图1A和1B举例说明一个深亚微米CMOS结构中的代表性的传统多平行板电容器10.电容器结构10包括被介电层13分开的电导线12的垂直堆叠。导线12和电介质层13被构造在一个半导体基体11上。导线12形成电容器10的板或电极。板12被以交替的方式一起电连接以致于所有的″A″板是一个第一极性而所有的″B″板是一个与第一极性相对的第二极性。
与平行板电容器结构有关的主要限制是当在CMOS处理中的几何特征被依比例缩小时，在板之间的最小距离不改变。因此，电容量密度的增长不是在如此依比例缩小的时候下实现的。
各种具有高电容量密度的其他电容器结构，例如双倍多晶硅电容器和栅氧化物电容器，是在现有技术中已知道。双倍多晶硅电容器，然而，不引导它们自己到深亚微米CMOS处理。栅氧化物电容器通常不被在深亚微米CMOS处理中，因为它们有引起生产量和可靠性问题的栅极，它们产生随电压而变化的电容量，和可能经历可以击穿栅氧化物的高电压。
用于动态随机存取储存器(DRAMs)的沟槽电容器结构有高电容量密度。这样的电容器通过在基体蚀刻和用导电的和介电材料填充沟槽来形成垂直的电容量结构。然而，因为它们增加蚀刻和填充处理过程，所以沟槽电容器对制造是昂贵的。
交指形状的电容器结构在微波应用中被用。这些电容器被靠近地放置，交指形状的导线结构在其间上生产边缘和交叉电容以实现电容。然而，在被交指形状电容器所产生的交叉电容量被限制在单个导体的层面上。
因此，需要深亚微米CMOS的一个改良的电容器结构，它利用了收缩半导体处理过程(shrinking semiconductor process)几何特征和能被廉价的制造。
电容器结构包括一个第一层面的导电平行线的组成而且至少有一个第二层面的导电性平行线放置在第一层面中的线，第一个和第二层面的线被安排垂直行中。一个介电层被放置在第一和第二层面的导线之间。一个或更多连接第每行中的一和第二层面线，藉此形成垂直的电容器板的平行阵列。电的相对节点形成电容器的端子。垂直电容器板的平行阵列以交替的方式被电连接到节点以便板有交替的电极性。
现在将会在对示例性的实施例的考虑之上结合附图更完全，清晰地详细地描述本发明的优点，特性和各种不同的附加特征，其中
图1是在一个深亚微米集成电路中的传统的平行板电容器结构的顶视图；
图1B是由图1A的线1B-1B所看的剖视图；
图2A是依照本发明一个实施例的深亚微米CMOS结构中的交指形状多层(IM)电容器的顶视图；
图2B是图2A的IM电容器的部分透视图；
图2C是图2B的IM电容器部分的端面图；和
图3是传统的交指形状的电容器的端面图。
应该被了解附图是为举例说明本发明的目的和是不要依比例所绘制的。
图2A-2C举例说明根据本发明一个实施例的用于在深亚微米CMOS中产生电容量的交指形状多层(IM)电容器结构。IM电容器结构20被结在一个多个导体层面处理过程中(四个电的导体层面L1-L4仅仅被示例性描述)在半导体的一个基体材料21(图2B和2C)被构造。第一导体层面L1包括第一平行阵列的导电性的层面线22，第二个导体层面L2包括第二平行阵列导电性的层面线23，第三个导体层面L3包括第三平行阵列导电性的层面线24，和第四个导体层面L4包括一第四平行阵列的导电性层面线25。一个第一电介质层26填充在基体21和第一导体层面L1之间；一电介质层27填充在第一个和第二之间的导体层面L1，L2之间的空间和在第一导体层面L1的线22之间的空间；一个第三个电介质层28填充在第二个和第三导体层面L2，L3之间的空间，和第二导体层面L2的线23之间的空间；一第四的介电层29填充在第三个和第四个导体层面L3，L4之间空间，和在第三个导体层面L3的线24之间的空间；和一第五的介电层34填充在第四个导体层面L4的线25之间的空间。
四层面的L1-L4导电线23-25在排或堆叠中是相互垂直对准。每排的导电线23-25是经由垂直延伸的导电性交点30-32互相电连接的，该导电交点在第二个，第三和第四个介电层27-29中形成。导电线23-25的排而且交点30-32形成一个平行阵列的垂直延伸板33，该板形成电容器的电极20.垂直的板33通过将A板的顶部和底部电连接到一个第一公共节点A和将B板的顶部和底部电连接到一个第二公共节点B上(图2A)来交指式地电连接到具有相反极性的“A”，“B”板上。第一和第二节点A，B形成IM电容器的端子结构20.
本发明中的IM电容器结构20产生电容量的机制可通过首先检查一个如图3所示的传统单一层面交指形状的电容器结构40来最好地被了解。交指形状的电容器结构40具有所有的在交指形状的导电线41之间的的交叉电容量CC和所有在交指形状的导电线41之间边缘电容量Cf的和的总电容量CTotal。在交指形状的电容器结构40中，边缘电容量Cf在数量上是与交叉电容量Cc可比较的。
本发明的IM电容器结构20也有总电容量CTotal，它是在交指形状的垂直板之间的交叉电容量CC(在在毗连导线之间的交叉电容量和在毗连的交点之间的交叉电容量的总和)上和所有在交指形状的垂直板33之间的边缘电容量Cf的总和。然而，不同于传统的交指形状的电容器结构40，当边缘电容量Cf的量不改变的时候，交叉电容量Cc随着在IM电容器结构20中每个附加的导体层面的增加而增加。因此，IM电容器结构20的边缘电容量对总电容量Ctotal的贡献比较少。如附加的导体层面在IM电容器结构20中被用，交叉电容量CC上的数量在电容器的总电容量CTotal中变成一个主要因素，而边缘电容量Cf的量变得更加不重要的。
在现在的现有技术的深亚微米CMOS技术状态中，大约0.5个微米或更少的导线间隔是通常的。因此，在本发明的IM电容器结构20的垂直板之间的最小距离典型地相等或少於大约0.5个微米。(当堆叠四个导线层面的时候，板的高度典型地比约0.5个微米大)。在本发明的IM电容器结构20的垂直板33之间的亚微米间隔能提供比使用传统的平行板电容器结构所能到达的更大的电容量密度。
电容量密度的改进能被通过比较传统的平行板电容器的电容量看到，类似在图1A和1B中显示的，由五(5)个板被构造和有15微米×39微米的尺寸，依照本发明(图2A)的由用4个导体层面构造的一个电容器和有14.9微米×39微米的尺寸。两个电容器在一个0.25微米CMOS处理工艺中被构造。在平行板电容器的节点A和B之间的平行板电容量被发现是95fF，而与之相比的，在IM电容器的节点A和B之间的电容量被发现是150fF。因此，本发明的IM电容器结构提供电容量密度的约60％的增加。
如半导体处理技术的几何特征继续收缩而且按比例减少，本发明中的IM电容器结构20的电容量密度有利的增加。这是因为在本发明的IM电容器结构20中的MW导电线22-25的最小宽度(图2C)，交点30-32的尺寸，在在相同的垂直板中交点30-32之间的最小的距离Mdv(图2B)，和垂直板33之间的最小距离Md(图2C)将有利地减少。结果，在IM电容器结构20中的交叉电容量CC将会增加。这样的电容量增加不可能在传统的多层平行板电容器中结构，因为导体的高度或厚度和介电层面不会依比例减少。因此，在传统的平行板电容器结构的板之间的距离将会大约保持为1个微米。
本发明的IM电容器结构典型地在正在使用传统的深亚微米CMOS处理技术的硅中被制造。本发明的电容器结构也能在使用传统的深亚微米处理的砷化镓或任何其他的适当半导体系统中被制造。在使用深亚微米CMOS处理的硅中的制造过程，通常包括在硅半导体基体的被选择的部分上上生长或沉积第一层的二氧化硅以形成第一电介质层。二氧化硅层有在约为一个微米的范围内的厚度。第一层金属，例如铝，或高度地导电的多晶硅，被沉积在二氧化硅的第一电介质层上，然後使用公知的掩模和干蚀刻技术被限定为导线以形成第一导体层面。如上所述，导线宽度和间隔被设定成最小的处理尺寸以提高结构的电容量，也就是，线和在线之间的间隔是尽可能狭窄的。
然后第二层的二氧化硅被生长或沉积在导线上以形成第二个电介质层。二氧化硅的第二个电介质层的厚度是在一个微米的范围内。延伸下到第一导体层面的多个孔被定义在二氧化硅的第二个电介质层中然後使用传统的制造技术填充金属或多晶硅以形成在第二个电介质中层垂直地延伸的交点。第二金属层，例如铝或多晶硅，在第二个二氧化硅的电介质层上被沉积然後被限定在第二个导体层面的导线之内。剩余的电介质层，交点，导体层面，而且导线以上述相同方式被制造。
本领域中的一般技术人员应理解特定的电介质材料可以代替二氧化硅(硅系统)或氮化硅(砷化镓系统)用于形成介电层。举例来说铁-电的陶瓷，例如PLZT(镧修正的锆钽酸铅)能用来形成介电层。与二氧化硅的介电常数3.9相反，当PLZT有一个大约4,700的介电常数，PLZT层的使用非常大地提高电容量。
本领域的一般技术人员将会进一步认识本发明的IM电容器结构在许多应用中可能是有用的，例如射频，模拟和数字应用。射频线路应用电容器来进行匹配。每单位面积的电容量愈大，区域也愈小和费用越低。在模拟电路应用中，不受欢迎的噪音能时常被通过使用大的电容器(KT/C)来减少。在数字电路应用中，大的去耦合电容量是非常重要的并且通过能本发明的电容器容易地具有。
虽然本发明已经参照於上述的实施例进行了描述，但是可以不背离本发明的构思而进行附加的修正和变化。因此，所有的这些修正和变化被考虑在附加的权利要求范围里面。

Claims (11)

1.电容器(20)包含：
第一层面(L1)的导电平行线(22)；
至少一个第二个层面(L2)的导电平行线(23)，放置在第一层面(L1)之上，第一和第二层面(L1，L2)的线(22，23)被安排在垂直行中；
放置在第一和第二层面(L1，L2)的导线(22，23)之间的介电层(27)；
连接每行的线(22，23)的多个交点(30)，藉此形成垂直的电容器的平行阵列电容器板(33)；和
形成电容器(20)的端子的电相反的节点(A，B)，平行阵列的垂直电容器板(33)以交替的方式电连接到相对节点(A，B)以便板(33)有交替的电极性。
2.权利要求1的电容器(20)，导线(22，23)包含金属。
3.权利要求1的电容器(20)，导线(22，23)包含多晶硅。
4.权利要求1的电容器(20)，介电层(27)包含二氧化硅。
5.权利要求1的电容器(20)，进一步包含：
以垂直延伸行的方式放置在第二个层面线(23)上的至少一个第三个层面(L3)的导电平行线(24)；
一个放置在第二和第三层面(L2，L3)的导线(23，24)之间的第二电介质层(28)；和
连接在每行中的第二的和第三层面线(23，24)的多个交点(31)，以便第三个层面线(24)垂直延伸平行阵列垂直电容器板(33)。
6.权利要求1的电容器(20)，其中第一和至少第二个多层面(L1，L2)的导电平行线(22，23)包含安排在垂直行中的多个导电平行线(22，23，24，25)，而且介电层包含多个介电层(27，28，29，30)，每层(27，28，29，30)放置在相对导线层面之间。
7.权利要求1的电容器(20)，其中电容器(20)被构造在一个基体(21)上。
8.权利要求7的电容器(20)，其中基体(21)由一个半导体材料制成。
9.权利要求1的电容器(20)，其中电容器(20)包含亚微米MOS结构。
10.权利要求1的电容器(20)，其中电容器(20)包含亚微米CMOS结构。
11.权利要求1的电容器(20)，其中电容器(20)包含一个亚微米结构。
CNB018008445A 2000-04-07 2001-03-29 深亚微米互补型金属氧化半导体的交指形状多层电容器结构 Expired - Lifetime CN1199277C (zh)

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