CN1193418C - 半导体装置及其制造方法、电路衬底以及电子仪器 - Google Patents

半导体装置及其制造方法、电路衬底以及电子仪器 Download PDF

Info

Publication number
CN1193418C
CN1193418C CNB02128296XA CN02128296A CN1193418C CN 1193418 C CN1193418 C CN 1193418C CN B02128296X A CNB02128296X A CN B02128296XA CN 02128296 A CN02128296 A CN 02128296A CN 1193418 C CN1193418 C CN 1193418C
Authority
CN
China
Prior art keywords
semiconductor device
substrate
semiconductor chip
protrusion
conductive member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB02128296XA
Other languages
English (en)
Other versions
CN1402321A (zh
Inventor
宫坂英男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN1402321A publication Critical patent/CN1402321A/zh
Application granted granted Critical
Publication of CN1193418C publication Critical patent/CN1193418C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体装置，在半导体元件(10)的电极(12)上设置导电构件(24)。把导电构件(24)压平到约2/3以下的高度，形成凸出(40)。利用包含绝缘性填充剂(68)的粘合剂(64)使半导体元件(10)和具有布线结构(62)的衬底(60)相对。按压半导体元件(10)和衬底(60)中的至少一方，把凸出(40)电连接到布线结构(62)上。通过使凸出难于变形，使凸出的端面变形所需要的力大于凸出排出粘合剂的力(压出)，故可靠性高、达到均质化。

Description

半导体装置及其制造方法、电路衬底以及电子仪器
技术领域
本发明涉及一种半导体装置及其制造方法、电路衬底以及电子仪器。
背景技术
要把半导体芯片面朝下安装到衬底上时，可用粘合剂把半导体芯片固定在衬底上。这里，因为粘合剂的热膨胀率比半导体元件的热膨胀率大，所以认为会发生半导体元件和粘合剂的剥离。对此，有时是把比粘合剂(树脂)的热膨胀率还小的二氧化硅类填充剂等绝缘性填充剂混入粘合剂中，以降低粘合剂和半导体元件的热膨胀系数之差。
可是，如图11所示，当使用了高度在给定高度以上的高度的凸出时，当把半导体芯片400通过含有绝缘性填充剂412的粘合剂410按压到衬底420上时，凸出402的形状变形，有时在凸出402的端面上形成大的凹状的凹处404。从试验可知其原因在于：因为包含二氧化硅类填充剂等绝缘性填充剂412的粘合剂410的流动性降低，粘度增加，所以从粘合剂410加到凸出402的端面的力变大。因为当凸出402的高度高时(例如，形成中调平时加的负载低时)，容易变形，从与粘合剂410相连到与衬底420的布线结构422电连接之间，开始变形。而且，与衬底420的布线结构422相对的凸出402的端面上能形成凹状的凹处404。
如图11所示，如果凸出402的端面上形成了凹状的凹处404，绝缘性粘合剂(树脂)或绝缘性填充剂412就容易积蓄在凹状的凹处404上，凸出402和布线结构422的电连接就会受绝缘性粘合剂(树脂)或绝缘性填充剂412的影响，但是很难控制绝缘性填充剂412的排出性。
发明内容
本发明的目的在于：提供一种通过使凸出很难变形而使可靠性提高、并被均质化的半导体装置及其制造方法、电路衬底以及电子仪器。
(1)本发明的半导体装置的制造方法，包含：
(a)把导电构件设置在半导体元件的电极上；
(b)把所述导电构件压平，使压平后的导电构件的高度变为压平前的导电构件的高度的约2/3以下，形成凸出；
(c)通过介于含有绝缘性填充剂的粘合剂粘合，使所述半导体元件和具有布线结构的衬底相对；
(d)按压所述半导体元件以及所述衬底的至少一方，使所述凸出电连接到所述布线结构上。
根据本发明，因为凸出不容易变形，所以凸出的端面变形所需要的力比凸出排出(压出)粘合剂所需要的力大。因此，从凸出与粘合剂相连到与衬底的布线结构电连接之间，通过从粘合剂向凸出的端面施加的力，能防止在凸出的端面上形成凹状的凹处。即，即使是在通过粘合剂把半导体元件和衬底固定的场合，在粘合时，也能防止绝缘性粘合剂(树脂)或绝缘性填充剂过剩地积蓄在凸出和布线结构的接合面上。由此，能抑制凸出和布线结构的电连接的电阻值下降，并且因为绝缘性填充剂等的排出的控制性变好，所以能降低每个半导体装置的特性的偏移。因此，能提高半导体装置的可靠性，并且能使半导体装置的质量均质化。
(2)在该半导体装置的制造方法中，在所述工序(a)中，也可以在导线的顶端上形成球，把所述导线的所述球焊接到所述半导体元件的所述电极上，切断所述导线，使所述球留在所述电极上，在所述电极上设置所述由所述导线的一部分和所述球构成的导电构件。
(3)在该半导体装置的制造方法中，所述粘合剂是包含导电性填充剂的各向异性导电材料；
在所述工序(d)中，使所述导电性填充剂存在于所述凸出和所述布线结构之间。
(4)在该半导体装置的制造方法中，所述凸出可以由含金的材料构成。
(5)在该半导体装置的制造方法中，可以对于具有多个所述半导体元件的半导体片实行所述工序(a)和(b)；
在所述工序(c)之前，还包含：把半导体片按每个所述半导体元件切成半导体芯片；
对于所述半导体芯片实行所述工序(c)和(d)。
由此，因为能在晶片水平形成凸出，所以生产效率优越。
(6)在该半导体装置的制造方法中，所述半导体元件也可以是半导体芯片。
(7)本发明的半导体装置的制造方法，包含：
把含有绝缘性填充剂的粘合剂配置在形成了凸出的半导体芯片和形成了比所述凸出宽度窄的布线的衬底之间；
通过介于所述粘合剂向着所述衬底对所述半导体芯片加压，在所述凸出的顶端面上形成凹部，把所述凸出和所述布线电连接起来。
根据本发明，由于布线的宽度窄，所以能减小在凸出上产生的凹部。另外，因为能在凸出的凹部中配置布线，所以能增大布线和凸出的电连接面积。
(8)在该半导体装置的制造方法中，可以通过所述凸出推开所述粘合剂，使所述凸出和所述布线电连接；
所述凹部是在推开所述粘合剂时形成的。
(9)在该半导体装置的制造方法中，所述布线的顶端面的宽度可以比所述凸出的所述顶端面的宽度窄。
(10)在该半导体装置的制造方法中，所述布线的顶端部比下端部小。
(11)本发明的半导体装置的制造方法，包含：把含有绝缘性填充剂的粘合剂配置在形成了凸出的半导体芯片和形成了具有凸部的布线的衬底之间；
在所述半导体芯片和所述衬底之间外加压力，通过来自所述粘合剂的压力，在所述凸出的顶端部形成凹部，所述布线的所述凸部与所述凸出的所述凹部配合，所述凸出和所述布线电连接。
根据本发明，因为布线具有凸部，凸出的凹部与凸部配合，所以能增大布线和凸出的电连接面。因此，很难产生连接不良。
(12)本发明的半导体装置由所述半导体装置的制造方法制造而成。
(13)本发明的电路衬底具有所述半导体装置。
(14)本发明的电子仪器具有所述半导体装置。
附图说明
图1(A)～图1(C)是表示适用了本发明的实施例1的半导体装置的制造方法的图。
图2(A)～图2(C)是表示适用了本发明的实施例1的半导体装置的制造方法的图。
图3是表示本发明的实施例1的的变形例的半导体装置的制造方法的图。
图4是表示本发明的实施例1的半导体装置的制造方法的图。
图5是表示本发明的实施例1的半导体装置的图。
图6是表示适用了本发明的实施例2的半导体装置的制造方法的图。
图7是表示适用了本发明的实施例3的半导体装置的制造方法的图。
图8是表示本发明的实施例的电路衬底的图。
图9是表示本发明的实施例的电子仪器的图。
图10是表示本发明的实施例的电子仪器的图。
图11是表示以往技术中的半导体装置的凸出的剖面的图。
下面简要说明附图符号。
10-半导体芯片；12-电极；20-导线；22-球；24-导电构件；40-凸出；50-半导体片；52-半导体元件；60-衬底；62-布线结构；64-各向异性导电材料；66-导电性填充剂；68-绝缘性填充剂。
具体实施方式
下面，参照附图就本发明的实施例加以说明。但须注意，本发明并不局限于以下的实施例。
(实施例1)
下面，与图1(A)～图5对应，说明本发明的实施例1的半导体装置的制造方法。并且，本实施例的半导体装置的制造方法包含图1(A)～图3所示的凸出的形成方法。
如图1(A)所示，准备形成了一个或多个(一般为多个)电极(垫)12的半导体元件。在图示的例子中，半导体元件是半导体芯片10。或者，如后所述，半导体元件也可以是半导体片50的一部分(参照图3)。
虽然半导体芯片10可以形成球状，但是一般形成长方体。多个电极12在形成了半导体芯片10的集成电路的面(有源面)上形成。各电极12可以在半导体芯片10的任意的边(例如相对的2边或4边)上形成。并且，可以用铝或铜等形成电极12。
常常在半导体芯片10上，避开电极12，形成钝化膜(图中未显示)。例如，可以用SiO2、SiN、聚酰亚胺树脂等形成钝化膜。
在这样的半导体芯片10的形成了电极12的面一侧配置毛细管14。导线20贯穿了毛细管14。导线20的宽度(粗细)可以是约20～30μm，按照顶端上形成的球22的大小，能自由决定。导线20一般用金、铜或铝等构成，但只要是导电性材料即可，并无特别限制。导线20的材料成为构成凸出40的材料。
首先，在导线20的顶端、毛细管14的外侧形成球22。例如用电焊枪(图中未显示)进行高压放电形成球22。球22被几乎形成为球状，它的直径(例如约60μm)由导线20的宽度和放电时间决定。
然后，把毛细管14配置在任意一个电极12的上方，把球22配置在任意一个电极12的上方。打开钳16，使毛细管14下降，把球22压在电极12上。用一定的压力按住球22，在电极12上进行压接时，外加超声波或热等。
这样，如图1(B)所示，导线20的球22被焊接到电极12上。并且，球22通过与电极12接合，其直径(例如约80μm)变大。
然后，关闭钳16，保持导线20，如图1(C)所示，使毛细管14和钳16同时上升。导线20被拉断，把包含球22的部分留在电极12上。这样，能在电极12上设置由导线20的一部分和球22构成的导电构件24。当存在多个有必要形成凸出40的电极12时，对多个电极12重复以上的工序。
因为残留在电极12上的导电构件24是由导线20的切断形成的，所以常会形成凸状，并且它的上端面的面积小，变得不平。另外，导电构件24的轴向的高度A(例如约60～70μm)由焊接前的球22的大小(直径)、基于毛细管14的对球22的负载、连在球22上的剩下的导线20的高度等决定。并且，因为导电构件24是通过导线20的切断而形成的，所以半导体芯片10上的各导电构件24的高度有些参差不齐。
接着，进行图2(A)和图2(B)所示的工序，如图2(C)所示，在半导体芯片10上形成给定高度的凸出40。
如图2(A)所示，把设置了导电构件24的半导体芯片10放到台30之上后，如图2(B)所示，用按压样板32压平了象这样用钉头方式设置的导电构件24。即对于半导体芯片10上的导电构件24进行调平。当存在多个设置了导电构件24的电极1 2时，可以把多个导电构件24一次压平。由此，能消除各导电构件24的高度的偏差(或减小)。
在压平导电构件24的工序中，通过增加调平时外加的负载，进行压平，使压平后的导电构件24的高度(凸出40的高度)变为压平前的导电构件24的高度的约2/3以下，得到凸出40。即如果用图1(C)和图2(C)中的符号说明，则进行压平，使压平后的导电构件的高度(向衬底安装前的凸出40的高度)B变为压平前的导电构件的高度A的约2/3以下(B≤2A/3)。这里，导电构件的高度或凸出的高度是指从导电构件或凸出的底面到导电构件或凸出中最高的部分的距离。
由此，在其后的工序，具体而言是在“使具有半导体芯片10的凸出40的面与设置了包含绝缘性填充剂68的粘合剂(包含粘合板)的衬底60的表面相对的工序后，通过按压，把半导体芯片10安装在衬底60上，使凸出40与布线结构62电连接的工序”中，能防止向凸出40的高度方向(轴向)的变形即图11的凸出402的端面变成凹状。这里，绝缘性填充剂68是二氧化硅填充剂，可以用最大粒径约为1μm左右的，另外，粘合剂是35μm左右的厚度，并且设置在衬底上或半导体芯片10上，粘合剂的材料可以是环氧树脂。
在压平导电构件24的工序中，例如，当压平前的导电构件24的高度A约为60～70μm时，压平后的导电构件24的高度B可以大约在40μm以下。虽然可尽可能降低导电构件24的高度B，但是，在安装半导体芯片10时，为了确保能实现凸出40和衬底60的布线结构62的电连接的程度的高度，应满足0＜B。因此，如果用图1(C)和图2(C)中的符号说明，则凸出40高度B可以满足以下关系：0＜B≤2A/3。另外，如果压平导电构件24，它的直径就增大，但是，考虑到半导体芯片10的各电极12之间的间隔，它的直径可以是使相邻的凸出40不短路程度的大小。
这样，如图2(C)所示，在各电极12上形成了凸出40。可将切断的导线20的一部分压平，使凸出40的端面41几乎变得平坦。例如，凸出40的端面41的直径可以是40μm～50μm。另外，凸出40可以由含Au的材料构成。或者即使在进行了调平后，也可以通过切断的导线40的一部分变为凸状。
如图3所示，作为本实施例的变形例，可以在半导体片50上形成多个凸出40。半导体片50具有多个半导体元件52。半导体元件52是指在形成了凸出40后的工序中被切断，成为半导体芯片的部分。对于设置在半导体片50上的多个导电构件，可以通过按压样板，可以对各半导体元件52逐一进行压平，也可以对包含多个半导体元件52的领域一次压平。这样，因为能在晶片水平形成凸出40，所以生产效率高。并且，在形成了凸出40后，半导体片50被按照各半导体元件52切削或切断。
如图4和图5所示，把半导体芯片10安装在衬底60上，制造半导体装置1。即如图4所示，在台34上配置衬底60，通过包含绝缘性填充剂68的粘合剂把半导体芯片10面朝下安装到衬底60上。使形成了凸出40的面向着衬底60，搭载半导体芯片10。
衬底60可以用有机类或无机类的材料形成。衬底60通常形成与半导体芯片10相似的形状。如图4所示，既可以在一个衬底60上搭载一个半导体芯片10，也可以在一个衬底60上搭载多个半导体芯片10。后者的情况下，可以把半导体芯片10配置为多列(矩阵状)。当在一个衬底60上搭载多个半导体芯片10时，其后，要按半导体芯片10来切削或切断衬底60。
在衬底60上形成有布线结构62。布线结构62的结构为：由多条布线盘绕为给定形状。多条布线中的任意一条具有与凸出40的电连接部(例如凸台)。
在本实施例中，使用各向异性导电材料64作粘合剂。各向异性导电材料64是使绝缘性粘合剂中只包含所定量的导电性填充剂66。各向异性导电材料64可以是板状的各向异性导电膜，也可以是糊状的各向异性导电胶。也可以使用热硬化性的树脂(例如环氧类)作为各向异性导电材料64的粘合剂。
在各向异性导电材料64中包含了二氧化硅类填充剂等绝缘性填充剂68。绝缘性填充剂68几乎均匀地分布在粘合剂中，由此，例如能减小各向异性导电材料64和半导体芯片10的热膨胀系数的差、提高半导体装置的可靠性。在本实施例中，各向异性导电材料64在单位面积中导电性填充剂66的含量为45000个/mm2，和包含50％～60％的绝缘性填充剂68。另外，在本实施例中，导电性填充剂66以树脂球作为核心材料，在该核心材料的周围可以设置Ni和Au等的金属镀层。
可以把这样的各向异性导电材料64如图4所示那样设置在衬底60的面上。或者，也可以把各向异性导电材料64设置在半导体芯片10的面上。当把半导体芯片10安装在衬底60上时，把各向异性导电材料64设置在凸出40和布线结构62之间。另外，当在一个衬底60上安装多个半导体芯片10时，也可以在衬底60上包含多个半导体芯片10的搭载领域的领域中一体设置各向异性导电材料64。
如图4所示，用按压样板36把半导体芯片10压向衬底60。换言之，用半导体芯片10和衬底60双方给各向异性导电材料64加压。这时，在给各向异性导电材料64加压的同时，还外加了该粘合剂的粘接力产生的能量(例如热能或光能等)。这时，通过半导体芯片10的凸出40，各向异性导电材料64被分开，凸出40和布线结构62被电连接。这时，当通过凸出40推开各向异性导电材料64时，在和布线结构62的接合面相对的凸出40的表面上设置了凹部。
这里，通过提高调平时外加的负载，进行压平，形成了凸出40，使其变为压平(调平)前的导电构件24的高度的约2/3以下。即当面朝下安装具有凸出40的半导体芯片10时，从凸出40相接于各向异性导电材料64到其与衬底60的布线结构62电连接之间，通过来自各向异性导电材料64加到凸出40的端面上的力，能使凸出40不变形。由此，能尽可能地减小在凸出40和布线结构62的接合面上形成的凹部，从而能容易地从接合面排出绝缘性填充剂68或绝缘性粘合剂。因此，能防止绝缘性粘合剂或绝缘性填充剂68对凸出40和布线结构62的电连接造成阻碍，并且，能减小具有该接合的各半导体装置的电特性上的偏差。
另外，通过把半导体芯片10按压在衬底60上，凸出40可被进一步压平(例如约10μm左右)。例如如果按压前的凸出40的高度(导电构件24被压平后的高度B)约为40μm，则通过按压样板36，凸出40可以约被压平到30μm。
这样，如图5所示，可制造出半导体装置1。半导体装置1包含形成了凸出40的半导体芯片10、形成了布线结构62的衬底60。在图5所示的例子中，在衬底60上，在与半导体芯片10相反的一侧，设置了多个外部端子70。外部端子70通过图中未显示的通孔等与布线结构62电连接。各外部端子70可以是焊锡球，例如可以印刷焊锡等，经过回流工序形成的。
根据本发明的半导体装置，能实现绝缘性填充剂68或绝缘性粘合剂被排出，不存在于凸出40和布线结构62之间的结构。因此，能提供两者间的电连接的可靠性高的半导体装置。
并且，在所述实施例中，使用了包含二氧化硅类填充剂的粘合剂，但是此外，也能使用不含二氧化硅类填充剂的粘合剂。进一步，虽然在所述实施例中，使用的是各向异性导电材料，但是也能使用不含导电填充剂的绝缘性粘合剂或粘合板。
(实施例2)
图6是说明本发明的实施例2的半导体装置的制造方法的图。在本实施例中，把半导体芯片100安装到衬底110(面朝下接合)。在半导体芯片100的电极(垫)102上形成了凸出104。在衬底110上形成了布线112。布线112的上端部(例如顶端面)的宽度(例如直径或一边的长度)d1比它的下端部(例如底面)的宽度(例如直径或一边的长度)d2小。另外，布线112的顶端面的宽度d1比凸出104的顶端面的宽度D窄。
在本实施例中，在半导体芯片100和衬底110之间配置包含绝缘性填充剂122的粘合剂120。然后，在半导体芯片100和衬底110之间外加压力，通过来自粘合剂120的压力，在凸出104的顶端面上形成了凹部106后，凸出104和布线112电连接。
须指出的是，在本来没有凹部106的状态下设置凸出104，在接合工序中，形成凹部106。可是，在本实施例中，因为关系式d1＜D成立，所以从粘合剂120加到凸出104的上端面上的力变小，能减小凸出104的凹部106。另外，因为在凹部106内设置了布线112，所以提高了两者的电连接面积。还因为d1＜d2的关系成立，所以可维持布线112的强度、减小它的上端面，上述的效果增强。在本实施例中，能适用实施例1中说明的内容。
(实施例3)
图7是说明本发明的实施例3的半导体装置的制造方法的图。本实施例在布线130具有凸部134这一点上与实施例2不同。可以形成凸部134，使布线110的中央部变厚。也可以导电层132和其上的凸出134形成布线130。这时可以用焊锡形成凸部134。或者用一种材料一体形成凸部134和它之下的层。
在本实施例中，使布线130的凸部134与凸出104的凹部106配合，凸出104和布线130电连接。这样，能增大凸出104和布线130的电连接面积。因此，很难产生连接不良。关于本实施例，其它内容如实施例2中所述。
图8表示安装了适用了本发明的半导体装置的电路衬底1000。电路衬底1000一般使用例如玻璃环氧衬底等有机类衬底。在电路衬底1000上，例如由铜构成的布线结构形成所希望的电路，这些布线结构和半导体装置的外部端子通过机械连接，实现电导通。
而且，作为具有适用了本发明的半导体装置的电子仪器或具有所述电路衬底1000的电子仪器，在图9给出了笔记本型个人计算机2000，在图10中给出了移动电话3000。

Claims (6)

1.一种半导体装置的制造方法，包含下述工序：
(a)把导电构件设置在半导体元件的电极上；
(b)把所述导电构件压平，使压平后的导电构件的高度变为压平前的导电构件的高度的2/3以下，形成凸出；
(c)通过介于含有绝缘性填充剂的粘合剂粘合，使所述半导体元件和具有布线结构的衬底相对；
(d)按压所述半导体元件以及所述衬底的至少一方，使所述凸出电连接到所述布线结构上。
2.根据权利要求1所述的半导体装置的制造方法，在所述工序(a)中，在导线的顶端上形成球，把所述导线的所述球焊接到所述半导体元件的所述电极上，切断所述导线，使所述球留在所述电极上，在所述电极上设置由所述导线的一部分和所述球构成的所述导电构件。
3.根据权利要求1所述的半导体装置的制造方法，所述粘合剂是包含导电性填充剂的各向异性导电材料；
在所述工序(d)中，使所述导电性填充剂存在于所述凸出和所述布线结构之间。
4.根据权利要求1～3中任意一项所述的半导体装置的制造方法，所述凸出由含金的材料构成。
5.根据权利要求1～3中任意一项所述的半导体装置的制造方法，对于具有多个所述半导体元件的半导体片实行所述工序(a)和(b)；
在所述工序(c)之前，还包含：把半导体片按每个所述半导体元件切成半导体芯片；
对于所述半导体芯片实行所述工序(c)和(d)。
6.根据权利要求1～3中任意一项所述的半导体装置的制造方法，所述半导体元件是半导体芯片。
CNB02128296XA 2001-08-08 2002-08-08 半导体装置及其制造方法、电路衬底以及电子仪器 Expired - Fee Related CN1193418C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2001240666 2001-08-08
JP2001240666 2001-08-08
JP2002185789 2002-06-26
JP2002185789A JP3981817B2 (ja) 2001-08-08 2002-06-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN1402321A CN1402321A (zh) 2003-03-12
CN1193418C true CN1193418C (zh) 2005-03-16

Family

ID=26620180

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB02128296XA Expired - Fee Related CN1193418C (zh) 2001-08-08 2002-08-08 半导体装置及其制造方法、电路衬底以及电子仪器

Country Status (3)

Country Link
US (1) US6881612B2 (zh)
JP (1) JP3981817B2 (zh)
CN (1) CN1193418C (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050208749A1 (en) * 2004-03-17 2005-09-22 Beckman Michael W Methods for forming electrical connections and resulting devices
US7524698B2 (en) * 2004-12-02 2009-04-28 International Business Machines Corporation Handling and positioning of metallic plated balls for socket application in ball grid array packages
US7600667B2 (en) * 2006-09-29 2009-10-13 Intel Corporation Method of assembling carbon nanotube reinforced solder caps
JP2008192984A (ja) * 2007-02-07 2008-08-21 Elpida Memory Inc 半導体装置及びその製造方法
JP2009065183A (ja) * 2008-10-14 2009-03-26 Nec Electronics Corp 電子装置及びその電子装置の製造方法
CN101937858A (zh) * 2010-08-03 2011-01-05 清华大学 一种倒装芯片凸点结构的圆片级制造方法
JP5252007B2 (ja) * 2011-03-08 2013-07-31 株式会社村田製作所 電子部品の製造方法
JP5965185B2 (ja) * 2012-03-30 2016-08-03 デクセリアルズ株式会社 回路接続材料、及びこれを用いた半導体装置の製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
TW337033B (en) * 1996-02-08 1998-07-21 Matsushita Electric Ind Co Ltd Bump forming method and its forming apparatus
EP0791960A3 (en) * 1996-02-23 1998-02-18 Matsushita Electric Industrial Co., Ltd. Semiconductor devices having protruding contacts and method for making the same
JPH1032224A (ja) 1996-07-15 1998-02-03 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US5976964A (en) * 1997-04-22 1999-11-02 Micron Technology, Inc. Method of improving interconnect of semiconductor device by utilizing a flattened ball bond
JPH1140522A (ja) * 1997-07-17 1999-02-12 Rohm Co Ltd 半導体ウエハの製造方法、この方法により作製された半導体ウエハ、半導体チップの製造方法、およびこの方法により製造された半導体チップ、ならびにこの半導体チップを備えたｉｃカード
US6267650B1 (en) * 1999-08-09 2001-07-31 Micron Technology, Inc. Apparatus and methods for substantial planarization of solder bumps
US6468832B1 (en) * 2000-07-19 2002-10-22 National Semiconductor Corporation Method to encapsulate bumped integrated circuit to create chip scale package

Also Published As

Publication number Publication date
JP2003124257A (ja) 2003-04-25
US20030032277A1 (en) 2003-02-13
JP3981817B2 (ja) 2007-09-26
CN1402321A (zh) 2003-03-12
US6881612B2 (en) 2005-04-19

Similar Documents

Publication Publication Date Title
CN1235286C (zh) 一种电子装置与制作此装置的方法
CN1208820C (zh) 半导体晶片、半导体装置及其制造方法
CN1665027A (zh) 半导体器件
CN1154178C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN100337327C (zh) 半导体器件及其制造方法
CN1266764C (zh) 半导体器件及其制造方法
CN1229863C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1123067C (zh) 具有与布线基板电连接的半导体芯片的半导体器件
CN1283004C (zh) 半导体装置及其制造方法、线路基板及电子机器
CN1411045A (zh) 半导体装置
CN1193426C (zh) 半导体器件
CN1229330A (zh) 混合模块及其制造方法与其安装方法
CN1577813A (zh) 电路模块及其制造方法
CN1452245A (zh) 半导体器件及其制造方法
CN1239831A (zh) 半导体器件及其制造方法
CN1136220A (zh) 载片及其制造方法和安装方法
CN1531069A (zh) 电子装置及其制造方法
CN1512580A (zh) 半导体装置及其制造方法
CN1340851A (zh) 电子器件及其制造方法
CN1575096A (zh) 电子电路装置及其制造方法
CN1812081A (zh) 半导体装置及其安装体
CN1193418C (zh) 半导体装置及其制造方法、电路衬底以及电子仪器
CN1705099A (zh) 半导体器件
CN1175480C (zh) 半导体装置及其制造方法
CN1906761A (zh) 驱动器芯片和显示设备

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20050316

Termination date: 20160808

CF01 Termination of patent right due to non-payment of annual fee