CN1175488C - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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CN1175488C
CN1175488C CNB991229576A CN99122957A CN1175488C CN 1175488 C CN1175488 C CN 1175488C CN B991229576 A CNB991229576 A CN B991229576A CN 99122957 A CN99122957 A CN 99122957A CN 1175488 C CN1175488 C CN 1175488C
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semiconductor chip
metal line
pad
semiconductor
evaporation
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CN1260591A (zh
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朴相昱
许民
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Abstract

本发明提供结构简单并且可以强化抵抗异物侵入的能力和机械强度的半导体封装及其制造方法。本发明包括：以焊盘朝向上部方式配置的半导体芯片；蒸镀在所述半导体芯片的焊盘、两侧壁和下表面的一部分上的金属线；以形成使所述半导体芯片的下表面上蒸镀的金属线部分露出的球形焊区的方式、模压整个制成物的密封剂；和固定在所述球形焊区上的焊球。

Description

半导体封装及其制造方法
技术领域
本发明涉及半导体封装及其制造方法。
背景技术
近年来，由于作为半导体封装的一种的芯片尺寸封装具有可以把封装的大小设定成芯片大小的优点，所以一直在进行开展在轻薄短小的封装方向的研究。这种芯片尺寸封装有采用不弯曲的刚体基板，或采用图形带等方式。
上述方式中采用基板的方式由于难以制作基板，所以目前主要采用使用图形带的方式。参照图1示意性地说明采用图形带(pattern tape)的现有的芯片尺寸封装。
如上所述，图形带1具有从下部依次层叠焊接保护层(solder resist)1a、金属布线1b、粘接剂1c和弹性体(elastomer)1d的结构。半导体芯片2附着在弹性体1d上。半导体芯片2的焊盘2a通过铜带(Cu ribbon)3与图形带1的金属布线1b电连接。另一方面，在焊接保护层1a上形成球形焊区，用密封剂4模压整个制成物，露出该球形焊区，并且露出半导体芯片2的表面。在露出的球形焊区上形成安装基板的焊球5。
但是，由于使用上述那种图形带的芯片尺寸封装存在图形带结构复杂的缺点，所以提出了图2所示的封装。
如图所述，其结构为在半导体芯片10的下表面上附着带有金属布线层的绝缘层11，在绝缘层11的下表面上直接安装焊球12。
但是，图1所示的芯片尺寸封装存在以下缺点。
首先，如上所述，由于图形带的结构由四层构成，所以结构复杂，制造工艺也复杂。因此，存在图形带的成本升高，同时在物质特性上强度弱的缺点。
此外，用铜带连接图形带和半导体芯片的焊盘，但在高温工艺下铜带往往容易被切断。而且，如果为了确保耐水性，作为密封剂，使用环氧系材料，那么铜带断线故障会成为更严重的问题。
另一方面，图2所示的封装由于未使用图形带，所以虽具有结构简单，电气连接路径也短的长处，但存在以下缺点。
发明内容
首先，由于半导体芯片的两侧面处于露出状态，所以在抵抗异物侵入和机械性外部冲击方面能力非常低。
此外，由于焊球直接附着在绝缘层上，所以焊料接合力完全取决于焊球。因此，在强化焊球的接合力中，存在焊球的尺寸变大的缺点，即封装的厚度变厚的缺点。而且，在封装电气测试中由模具支撑的焊球有损伤的危险，在防止这种损伤中，存在焊球的材料必须为高价铜的缺点。
因此，本发明的目的在于消除现有的芯片尺寸封装方面存在的各种问题，提供结构简单并且可以强化对异物侵入的抵抗和机械强度的半导体封装及其制造方法。
本发明的另一目的在于通过使电信号传送路径变得非常短来提高电气特性。
本发明的另一目的在于通过强化焊球的接合强度来防止在各种测试中损伤焊球。
为了实现上述目的，本发明的封装以焊盘朝向上部的方式配置的半导体芯片；蒸镀在所述半导体芯片的焊盘、两侧壁和下表面的一部分上的金属线；模压整个制成物的密封剂，形成使所述半导体芯片的下表面上蒸镀的金属线部分露出的球形焊区；和安装在所述球形焊区上的焊球，所述金属线被分为蒸镀在半导体芯片的焊盘和两侧壁上的上部金属线，以及与所述上部金属线连接同时蒸镀在半导体芯片的下表面上的下部金属线，在上部金属线和密封剂之间设置上部绝缘膜，在所述下部金属线和半导体芯片的下表面之间设置下部绝缘膜。
为了实现上述目的，本发明的封装以焊盘朝向上部的方式配置的上部半导体芯片；与所述上部半导体芯片的下表面接合，配置得使从所述上部半导体芯片露出的焊盘朝向上部的下部半导体芯片；从所述上部半导体芯片的焊盘至下部半导体芯片的两侧壁延长的、电连接所述上下部半导体芯片的各焊盘的上部金属线；以露出所述上部金属线的下端和下部半导体芯片的下表面的方式模压整个制成物的上部密封剂；形成在所述下部半导体芯片的下表面上的绝缘膜；蒸镀在所述绝缘膜上的、一端与所述上部金属线的下端电连接的下部金属线；以露出所述下部金属线的一部分的方式模压整个制成物下部的下部密封剂；形成在从所述下部密封剂露出的下部金属线部分上的接合辅助层；和安装在所述接合辅助层上的焊球。
为了实现上述目的，本发明的封装以焊盘朝向上部的方式配置的上部半导体芯片；与所述上部半导体芯片的下表面接合，配置得使从上述上部半导体芯片露出的焊盘朝向上部的下部半导体芯片；蒸镀在所述下部半导体芯片的焊盘上和两侧壁上的上部金属线；电连接所述上部金属线和上部半导体芯片的焊盘的金属丝；以露出所述上部金属线的下端和半导体芯片的下表面的方式模压整个制成物的上部密封剂；形成在所述半导体芯片的下表面上的绝缘膜；蒸镀在所述绝缘膜上的、一端与所述上部金属线的下端电连接的下部金属线；以露出所述下部金属线的一部分的方式模压整个制成物下部的下部密封剂；形成在从所述下部密封剂露出的下部金属线部分上的接合辅助层；和安装在所述接合辅助层上的焊球。
为了实现上述目的，本发明的封装以焊盘朝向上部的方式配置的半导体芯片；一端与所述半导体芯片的焊盘电连接的金属丝；蒸镀在所述半导体芯片的下表面上的、一端与所述金属丝电连接的金属线；以露出所述金属线形成球形焊区的方式模压整个制成物的密封剂；和安装在所述球形焊区上的焊球。
为了实现上述目的，本发明的封装在晶片上构成的各半导体芯片之间的部分上形成沟槽，在所述沟槽的内壁和半导体芯片的焊盘上蒸镀上部金属线的步骤；用上部密封剂模压整个制成物上部的步骤；以露出所述沟槽的底面和上部金属线的方式把所述晶片研磨除去预定厚度的步骤；在所述半导体芯片的一部分下表面上蒸镀下部金属线，使所述上下部金属线电连接的步骤；以形成所述下部金属线露出的球形焊区的方式，用下部密封剂模压整个制成物下部的步骤；在所述球形焊区上安装焊球的步骤；和切断在所述晶片上形成的各沟槽部分，分离成各个半导体芯片的步骤，在上部金属线和密封剂之间设置上部绝缘膜的步骤，在所述下部金属线和半导体芯片的下表面之间设置下部绝缘膜步骤。
为了实现上述目的，本发明的封装按焊盘朝向上部的方式配置半导体芯片。沿半导体芯片的表面、两侧壁和下表面蒸镀金属线，使其上端与焊盘电连接。以仅露出金属线的下端的方式用密封剂模压整个制成物。在自密封剂露出的金属线的下端上安装焊球。
作为其它方案，为了露出半导体芯片的下表面和金属线的下端，密封剂仅模压整个制成物的上部。在除了金属线的下端外的半导体芯片的下表面上形成绝缘层。一端与金属线的下端连接的下部金属线蒸镀在绝缘层上。以露出下部金属线的一部分的方式用下部密封剂模压整个制成物的下部。在自下部密封剂露出的下部金属线上安装焊球。
另一方面，如果上下部金属线有铝(Al)、铜(Cu)、镍(Ni)、铬(Cr)、钛(Ti)、金(Au)、铂(Pt)、钯(Pd)、铅(Pb)和锡(Sn)中的任何一个的断层结构，那么因金属线与焊球反应形成金属间化合物可靠性会下降，为了防止这种现象，最好在自各密封剂露出的金属线部分即在球形焊区上形成接合辅助层(Under Bump Metallurgy；UBM)。
接合辅助层既有金属线材料那样的断层结构，或者也有自铜/镍/金、铜/镍/金/铬、铜/镍/金/钴、铜/镍/金/锡、铜/镍/金/铬/锡、铜/镍/金/钴/锡或铜/镍/铅中选择的多层结构。另一方面，如果由上述材料构成的多层结构的接合防止层那样的多层结构构成金属线，那么不必另外形成接合辅助层。
上述结构构成的封装的制造方法如下。
腐蚀在晶片上构成的各半导体芯片之间的部分，形成沟槽。此时，各半导体芯片的焊盘处于接近沟槽两侧的位置。在沟槽的内壁和焊盘上蒸镀金属线，在整个制成物上形成绝缘膜。作为绝缘膜的材料，可以采用氮化膜、氧化膜或聚合物。在绝缘膜的上部涂敷密封剂。
接着，为了露出沟槽的底面，研磨晶片的下表面，除去预定厚度。在晶片的整个下表面上形成绝缘膜，为了露出金属线，腐蚀该部分，除去绝缘膜。把和露出的金属线的下端电连接的其它金属线蒸镀在绝缘膜的上部。在整个制成物的下表面上涂敷其它密封剂，为了露出蒸镀在绝缘膜上部的金属线，腐蚀该部位，形成球形焊区。在露出的球形焊区上形成接合辅助层，在接合辅助层上安装焊球。最后，切断沟槽部分，分离成各个半导体芯片。
按照上述本发明的结构，由于沿半导体芯片的表面、两侧面和下表面蒸镀金属线，该金属线成为电信号传送路径，所以信号传送路径变得非常短，电气特性提高，此外，由于金属线可以非常薄地蒸镀，所以封装的厚度可以降低。
附图说明
图1和图2是表示现有封装的剖面图；
图3是表示本发明封装的图；
图4至图15是依次表示本发明实施例1的封装的制造工艺的图；
图16是表示本发明实施例2的层叠型封装的图；
图17和图18是表示本发明实施例3的层叠型封装的图；
图19和图20是按制造工艺顺序表示本发明实施例4的封装的图。
图21是表示按照本发明的实施例5构成多芯片封装的图。
具体实施方式
(实施例1)
如图3所示，半导体芯片20以焊盘21朝向上部的方式配置。上部金属线30被分别蒸镀在半导体芯片20的两侧上表面和两侧面上，与半导体芯片20的焊接盘21电连接。为使上部金属线30绝缘，在整个制成物的上部和侧面上形成上部绝缘膜40。由此，穿过上部绝缘膜40和半导体芯片20的侧面之间被延长的上部金属线30的下端在下部露出。把上部密封剂50涂敷在上部绝缘膜40的上部。
下部绝缘膜41形成在半导体芯片20的下表面上。由此，上部金属线30的下端仍然处于露出状态。与露出的上部金属线30电连接的下部金属线31被蒸镀在下部绝缘膜41的下表面的一部分上。下部密封剂51涂敷在整个制成物的下部，但以使下部金属线31露出的方式涂敷。下部金属线31被蒸镀在下部绝缘膜41的下表面的一部分上。下部密封剂51涂敷在整个制成物的下部，但以使下部金属线31露出的方式涂敷。下部金属线31露出的区域为球形焊区，在该球形焊区上安装焊球60。
另一方面，上下部金属线30、31为铝、铜、镍、铬、钛、金、铂、钯、铅和锡的其中任何一个的断层结构，或多个层叠的多层结构。
但是，在下部金属线31与焊球60被接合时，下部金属线31的金属原子被扩散到铅-锡材料的焊球60上，在彼此之间的界面上有时会形成金属间化合物。由于该金属间化合物使下部金属线31与焊球60之间的接合力变弱，所以最好在球形焊区上形成接合辅助层70。
接合辅助层70为金属线30、31的材料那样的断层结构，或为铜/镍/金、铜/镍/金/铬、铜/镍/金/钴、铜/镍/金/锡、铜/镍/金/铬/锡、铜/镍/金/钴/锡或铜/镍/铅其中任何一种多层结构。另一方面，如果金属线30、31为按在接合辅助层70材料所述的材料中选择的多层结构，那么由于金属线30、31本身发挥防止扩散功能，所以不必另外形成接合辅助层70。
以下，根据图4至图15详细说明具有上述结构的封装的制造方法。
首先，如图4所示，在晶片W上构成多个半导体芯片20，各半导体芯片20由在晶片W表面上形成的划线来划分。半导体芯片20的焊盘21被配置在晶片W表面上。按照该状态，把各划线部分腐蚀至8至12μm的深度，形成沟槽22。
接着，如图5所示，在半导体芯片20的整个表面和沟槽22的内壁上按PVD、CVD或电子电镀方法蒸镀上部金属线30，但其宽度蒸镀至10至1000μm、厚度为0.5至5μm左右。腐蚀除去在各焊盘21之间的半导体芯片20表面上蒸镀的上部金属线30部分。由此，使上部金属线30仅残留在沟槽22内壁和与该沟槽22的两侧相邻配置的两个焊盘21表面上。
然后，为了使上部金属线30电绝缘，把上部绝缘膜40涂敷在整个制成物的上部。作为上部绝缘膜40的材料，可以采用氮化膜或氧化膜，作为压力缓冲用，也可以采用聚合物。
接着，为了使整个晶片W电绝缘，防止外部冲击和吸湿等，用上部密封剂50模压整个晶片W的上部，该模压方法有以下两种。
第一种方法，如图7A所示，使晶片W处于旋转板80上，如图7B所示，如果一边旋转旋转板80一边在晶片W上旋转涂敷上部密封剂50，那么如图7C所示，在晶片W的整个上部形成上部密封剂50。
第二种方法，如图8A所示，在下部模具91上配置晶片W，使非树脂形的上部密封剂50位于晶片W上，然后，如图8B所示，可以用上部模具90压挤形成上部密封剂50。
图9表示采用上述方法的其中之一把上部密封剂50形成于整体结构上部的结构。接着，如图10所示，在把晶片W翻过来使上部密封剂50朝向下部后，按化学机械研磨法研磨晶片W表面，除去一定厚度以露出沟槽22。于是，上部金属线30的下端穿过晶片W露出。接着，在晶片W上形成下部绝缘膜41。然后，为了露出埋入沟槽22的上部绝缘膜40部分和上部金属线30，腐蚀除去下部绝缘膜41的该部位。
而且，如图11所示，在整个制成物的上部蒸镀下部金属线31后，为了露出沟槽22区域和半导体芯片20的中央，腐蚀除去下部金属线31的该部位。于是，下部金属线31形成一端连接在上部金属线30上的线形态的图形。
接着，如图12所示，在整个制成物的上部涂敷下部密封剂51后，为了露出蒸镀在下部绝缘膜41上的下部金属线31部分，腐蚀下部密封剂51的该部位。通过该工艺，形成使下部金属线31露出的球形焊区61。
接着，如图13所示，把接合辅助层70蒸镀在球形焊区61上。其中，如果按所述多层结构形成下部金属线31，那么可以省略形成接合辅助层70的工序。
而且，如图14所示，把焊球60安装在接合辅助层70上。就是说，在本发明的封装的制造方法中，在晶片状态下优先实施安装焊球60的工序。
最后，如图15所示，如果切断沟槽区域部位，把晶片W分离为各个半导体芯片20，则完成图3所示的本发明实施例1的封装。
另一方面，在本实施例1中，金属线被分成上下部分，此外，还把绝缘膜和密封剂分为上下部分来使用，但也可以不必这样。就是说，可以把图3所示的上下部分金属线形成一个线，在未形成绝缘膜的状态下以仅露出处于半导体芯片下表面的金属线部分的方式用一种密封剂模压整个制成物。
(实施例2)
图16是表示本发明实施例2的层叠构成实施例1提示的封装的图。
如图所示，上下层叠图3所示的封装。只是，为了露出在焊盘21上部蒸镀的上部金属线30部分，腐蚀上部绝缘膜40和密封剂50的该部位，形成通孔62。把上部配置的其它封装的接合辅助层70配置在通孔62的上部，利用焊球或导电性凸缘把接合辅助层70和露出的上部金属线30电连接，从而实现叠层封装。
(实施例3)
图17和图18表示本发明实施例3的层叠型封装，图17采用上部金属线32，而图18采用金属丝90。
首先，如图17所示，通过把比图3所示的半导体芯片20宽度窄的上部半导体芯片23按使其焊盘24朝向上部的方式通过粘合剂80粘接在下部半导体芯片20的表面上。特别是上部半导体芯片23具有使下部半导体芯片20的焊盘21露出的宽度。上部金属线32不仅蒸镀在下部半导体芯片20的焊盘21上，而且还蒸镀在上部半导体芯片23的两侧壁和其焊盘24上。因此，各半导体芯片20、23的焊盘21、24通过一个上部金属线32电连接。
另一方面，图17所示的封装结构的一个限制是层叠的半导体芯片20、23较薄，其厚度在可金属蒸镀的范围内。
因此，如图18所示，如果层叠的半导体芯片20a、23a的厚度厚于可金属蒸镀的厚度，则要与上部金属线30一起使用金属丝90。就是说，上部金属线30与图3所示的结构同样形成，不同的是可使上部半导体芯片23a的焊盘24a通过金属丝90与上部金属线30电连接，实现叠层封装。
(实施例4)
图19至图20是表示本发明实施例4的封装的图。
首先，如图19所示，在使焊盘21朝向上部把半导体芯片20放置在模板100上后，利用金属丝90把焊盘21与模板100连接。就是说，在实施例1中使用上部金属线，而在本实施例4中未使用。
接着，用上部密封剂50模压整个制成物的上部，除去模板100。于是，金属丝90的下端从上部密封剂50中露出。在半导体芯片20的下表面上蒸镀下部金属线31使其与露出的金属丝90部分电连接。接着，以露出下部金属线31的方式用下部密封剂51模压整个制成物的下部。在从下部密封剂51中露出的下部金属线31部分即球形焊区上蒸镀接合辅助层70，当把焊球安装在接合辅助层70上后，则完成图20所示形状的封装。
就是说，如果比较本实施例4与实施例1的封装结构，则，首先在实施例4中代替上部金属线使用了金属丝，此外，由于实施例4的半导体芯片的厚度比实施例1的半导体芯片厚许多，所以不使用下部绝缘膜。
(实施例5)
图21是表示本发明实施例5的封装的图，具体地说，表示多芯片封装。
如图所示，是由在未用密封剂模压的状态下将实施例1的图3所示的封装配置在陶瓷容器110内部的结构构成的。陶瓷容器110被直接安装在基板上，但一般使用焊球。
如上所述，按照本发明，由于从焊盘至焊球的电信号传送路径不依赖于金属丝，而利用可以形成非常短长度的金属线来进行，所以可以把电信号传送路径非常短地构成，提高电气特性。
此外，由于金属线可以非常薄地形成，所以可实现封装厚度的轻薄化。
尤其在把整个半导体芯片进行封装，焊球安装工序结束后，由于被分离成各个半导体芯片，所以可以在晶片状态下实施整体制造工序，使封装工序变得容易。
再有，本发明不限于本实施例。在不脱离本发明精神的范围内，可以进行各种各样的变更。

Claims (11)

1.一种半导体封装，其特征在于，包括：
以焊盘朝向上部的方式配置的半导体芯片；
蒸镀在所述半导体芯片的焊盘、两侧壁和下表面的一部分上的金属线；
模压整个制成物的密封剂，形成使所述半导体芯片的下表面上蒸镀的金属线部分露出的球形焊区；和
安装在所述球形焊区上的焊球，
所述金属线被分为蒸镀在半导体芯片的焊盘和两侧壁上的上部金属线，以及与所述上部金属线连接同时蒸镀在半导体芯片的下表面上的下部金属线，
在上部金属线和密封剂之间设置上部绝缘膜，在所述下部金属线和半导体芯片的下表面之间设置下部绝缘膜。
2.如权利要求1所述的半导体封装，其特征在于，所述密封剂被分成配置在半导体芯片上下部的上下部密封剂。
3.如权利要求1所述的半导体封装，其特征在于，所述金属线为由铝、铜、镍、铬、钛、金、铂、钯、铅和锡组成的组中选择的断层结构，或由两个以上组成的多层结构。
4.如权利要求1所述的半导体封装，其特征在于，在所述球形焊区上形成有接合辅助层。
5.如权利要求4所述的半导体封装，其特征在于，所述接合辅助层由铜/镍/金、铜/镍/金/铬、铜/镍/金/钴、铜/镍/金/锡、铜/镍/金/铬/锡、铜/镍/金/钴/锡和铜/镍/铅组成的组中选择。
6.如权利要求1所述的半导体封装，其特征在于，为了露出处于所述半导体芯片的焊盘上的金属线部分，腐蚀所述密封剂的该部分而形成通孔，通过所述通孔，露出的金属线部分与其它封装的焊球电连接，构成层叠型。
7.一种半导体封装，其特征在于，包括：
以焊盘朝向上部的方式配置的上部半导体芯片；
与所述上部半导体芯片的下表面接合，配置得使从所述上部半导体芯片露出的焊盘朝向上部的下部半导体芯片；
从所述上部半导体芯片的焊盘至下部半导体芯片的两侧壁延长的、电连接所述上下部半导体芯片的各焊盘的上部金属线；
以露出所述上部金属线的下端和下部半导体芯片的下表面的方式模压整个制成物的上部密封剂；
形成在所述下部半导体芯片的下表面上的绝缘膜；
蒸镀在所述绝缘膜上的、一端与所述上部金属线的下端电连接的下部金属线；
以露出所述下部金属线的一部分的方式模压整个制成物下部的下部密封剂；
形成在从所述下部密封剂露出的下部金属线部分上的接合辅助层；和
安装在所述接合辅助层上的焊球。
8.一种半导体封装，其特征在于，包括：
以焊盘朝向上部的方式配置的上部半导体芯片；
与所述上部半导体芯片的下表面接合，配置得使从上述上部半导体芯片露出的焊盘朝向上部的下部半导体芯片；
蒸镀在所述下部半导体芯片的焊盘上和两侧壁上的上部金属线；
电连接所述上部金属线和上部半导体芯片的焊盘的金属丝；
以露出所述上部金属线的下端和半导体芯片的下表面的方式模压整个制成物的上部密封剂；
形成在所述半导体芯片的下表面上的绝缘膜；
蒸镀在所述绝缘膜上的、一端与所述上部金属线的下端电连接的下部金属线；
以露出所述下部金属线的一部分的方式模压整个制成物下部的下部密封剂；
形成在从所述下部密封剂露出的下部金属线部分上的接合辅助层；和
安装在所述接合辅助层上的焊球。
9.一种半导体封装，其特征在于，包括：
以焊盘朝向上部的方式配置的半导体芯片；
一端与所述半导体芯片的焊盘电连接的金属丝；
蒸镀在所述半导体芯片的下表面上的、一端与所述金属丝电连接的金属线；
以露出所述金属线形成球形焊区的方式模压整个制成物的密封剂；和
安装在所述球形焊区上的焊球。
10.一种半导体封装的制造方法，其特征在于，该方法包括：
在晶片上构成的各半导体芯片之间的部分上形成沟槽，在所述沟槽的内壁和半导体芯片的焊盘上蒸镀上部金属线的步骤；
用上部密封剂模压整个制成物上部的步骤；
以露出所述沟槽的底面和上部金属线的方式把所述晶片研磨除去预定厚度的步骤；
在所述半导体芯片的一部分下表面上蒸镀下部金属线，使所述上下部金属线电连接的步骤；
以形成所述下部金属线露出的球形焊区的方式，用下部密封剂模压整个制成物下部的步骤；
在所述球形焊区上安装焊球的步骤；和
切断在所述晶片上形成的各沟槽部分，分离成各个半导体芯片的步骤，
在上部金属线和密封剂之间设置上部绝缘膜的步骤，在所述下部金属线和半导体芯片的下表面之间设置下部绝缘膜步骤。
11.如权利要求10所述的半导体封装的制造方法，其特征在于，还包括在所述球形焊区上形成接合辅助层的步骤，该步骤是在利用所述下部密封剂模压整个制成物的步骤之后和在把焊球安装在所述球形焊区上的步骤之前。
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