CN115699302A - 一种芯片封装结构、电子设备 - Google Patents

一种芯片封装结构、电子设备 Download PDF

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Publication number
CN115699302A
CN115699302A CN202080101723.4A CN202080101723A CN115699302A CN 115699302 A CN115699302 A CN 115699302A CN 202080101723 A CN202080101723 A CN 202080101723A CN 115699302 A CN115699302 A CN 115699302A
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China
Prior art keywords
chip
substrate
metal
micro
metal layer
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Pending
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CN202080101723.4A
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English (en)
Inventor
朱靖华
张宏英
路鹏
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN115699302A publication Critical patent/CN115699302A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers

Abstract

本申请实施例提供一种芯片封装结构、电子设备，涉及芯片封装技术领域，用于在提高电子设备中集成的芯片数量的同时，改善部分芯片之间互连路径较长的问题。该芯片封装结构包括互连基板、至少一个芯片堆叠结构。芯片堆叠结构包括垂直互连的第一芯片和第二芯片。第一芯片包括第一金属层，该第一金属层包括模拟电路。第二芯片包括第二金属层，第二金属层包括数字电路。可以采用先进工艺制作具有数字电路的第二芯片，以获得尺寸较小，且性能较高的第二芯片。采用次先进工艺制作具有模拟电路的第一芯片，以保证第一芯片的性能和良率。

Description

PCT国内申请，说明书已公开。

Claims (15)

  1. PCT国内申请，权利要求书已公开。
CN202080101723.4A 2020-07-23 2020-07-23 一种芯片封装结构、电子设备 Pending CN115699302A (zh)

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PCT/CN2020/103886 WO2022016470A1 (zh) 2020-07-23 2020-07-23 一种芯片封装结构、电子设备

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CN115699302A true CN115699302A (zh) 2023-02-03

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WO (1) WO2022016470A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN115513159A (zh) * 2022-09-30 2022-12-23 维沃移动通信有限公司 芯片组件、电子设备以及芯片组件的制备方法
CN116314055B (zh) * 2023-02-10 2024-01-05 宜确半导体（苏州）有限公司 一种半导体封装结构及射频前端模块产品
CN116613154B (zh) * 2023-07-20 2023-09-19 盛合晶微半导体(江阴)有限公司 改善电源信号传输的2.5d封装结构及其制备方法
CN116721957B (zh) * 2023-08-10 2023-10-13 四川明泰微电子科技股份有限公司 一种封装芯片推料机构及芯片成型装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091638A (ja) * 2006-10-02 2008-04-17 Nec Electronics Corp 電子装置およびその製造方法
US9620455B2 (en) * 2010-06-24 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure
JP2013045863A (ja) * 2011-08-24 2013-03-04 Elpida Memory Inc 半導体装置およびその製造方法
US9583460B2 (en) * 2014-02-14 2017-02-28 Qualcomm Incorporated Integrated device comprising stacked dies on redistribution layers
KR20190092392A (ko) * 2016-12-27 2019-08-07 인텔 코포레이션 스택형 다이 캐비티 패키지
KR102530763B1 (ko) * 2018-09-21 2023-05-11 삼성전자주식회사 반도체 패키지의 제조방법

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