CN113990843A - 芯片组及其制造方法 - Google Patents

芯片组及其制造方法 Download PDF

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Publication number
CN113990843A
CN113990843A CN202111243000.0A CN202111243000A CN113990843A CN 113990843 A CN113990843 A CN 113990843A CN 202111243000 A CN202111243000 A CN 202111243000A CN 113990843 A CN113990843 A CN 113990843A
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chip
bonding
interposer
device layer
logic chip
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CN202111243000.0A
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CN113990843B (zh
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不公告发明人
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Shanghai Bi Ren Technology Co ltd
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Shanghai Biren Intelligent Technology Co Ltd
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Priority to CN202111243000.0A priority Critical patent/CN113990843B/zh
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Priority to US17/958,456 priority patent/US20230130460A1/en
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Abstract

本发明提供一种芯片组及其制造方法。芯片组包括逻辑芯片、输入输出芯片以及中介板。逻辑芯片包括多个第一键合组件设置在第一装置层。输入输出芯片包括多个第二键合组件设置在第二装置层。中介板包括多个第三键合组件设置在第三装置层。逻辑芯片通过多个第一键合组件的第一部分与中介板的多个第三键合组件的第一部分以接垫对接垫的方式直接接合，并且输入输出芯片通过多个第二键合组件与中介板的多个第三键合组件的第二部分以接垫对接垫的方式直接接合。多个第三键合组件的第一部分的至少一部分通过第一金属走线连接至多个第三键合组件的第二部分的至少一部分。因此，本发明的芯片组及其制造方法可有效地降低功耗以及缩小芯片面积。

Description

芯片组及其制造方法
技术领域
本发明涉及一种半导体装置，尤其是指一种芯片组及其制造方法。
背景技术
对于传统的芯片组(Chiplet)而言，传统的芯片组中所设置的逻辑芯片以及输入输出芯片之间通常需要设置连接介面电路，例如例如裸片对裸片(Die to Die，D2D)介面电路、高频宽存储器(High Bandwidth Memory，HBM)实体介面电路，因此随着目前芯片设计朝向高频宽及高密度芯片的趋势发展，传统的芯片组的芯片面积(或芯片体积)也往往会因设置这些连接介面电路的数量增加的影响，而使得传统的芯片组的芯片面积过大且具有高功耗的问题。
发明内容
根据本发明的实施例，本发明的芯片组包括逻辑芯片、输入输出芯片以及中介板。逻辑芯片具有第一装置层以及第一基板层，并且包括多个第一键合组件设置在第一装置层。输入输出芯片具有第二装置层以及第二基板层，并且包括多个第二键合组件设置在第二装置层。中介板具有第三装置层以及第三基板层，并且包括多个第三键合组件设置在第三装置层。逻辑芯片通过多个第一键合组件的第一部分与中介板的多个第三键合组件的第一部分以接垫对接垫的方式直接接合，并且输入输出芯片通过多个第二键合组件与中介板的多个第三键合组件的第二部分以接垫对接垫的方式直接接合。多个第三键合组件的第一部分的至少一部分通过第一金属走线连接至多个第三键合组件的第二部分的至少一部分。
根据本发明的实施例，本发明的芯片组的制造方法包括以下步骤：形成多个第一键合组件在逻辑芯片的第一装置层；形成多个第二键合组件在输入输出芯片的第二装置层；形成多个第三键合组件在中介板的第三装置层；将多个第三键合组件的第一部分的至少一部分通过第一金属走线连接至多个第三键合组件的第二部分的至少一部分；将逻辑芯片的多个第一键合组件的第一部分与中介板的多个第三键合组件的第一部分以接垫对接垫的方式直接接合；以及将输入输出芯片的多个第二键合组件与中介板的多个第三键合组件的第二部分以接垫对接垫的方式直接接合。
基于上述，本发明的芯片组及其制造方法，可有效地降低功耗以及缩小芯片面积。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
附图说明
图1是本发明的一实施例的芯片组的侧视结构图；
图2是本发明的一实施例的芯片组的等效电路图；
图3是本发明的一实施例的混合键合结构的示意图；
图4是本发明的一实施例的芯片组的制造方法的流程图；
图5A至图5I是本发明的一实施例的芯片组的制造流程示意图；
图6是本发明的一实施例的芯片组的俯视结构图。
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在图式和描述中用来表示相同或相似部分。
图1是本发明的一实施例的芯片组的侧视结构图。参考图1，逻辑芯片100包括逻辑芯片110、120、输入输出(Input/Output)芯片130、140以及中介板(interposer)150。逻辑芯片110、120、输入输出芯片130、140以及中介板150分别沿着方向D1以及方向D2延伸，并且逻辑芯片110、120以及输入输出芯片130、140沿着方向D3形成在中介板150上，其中方向D1～D3彼此垂直。在本实施例中，逻辑芯片110、120可分別例如是系统级芯片(System on Chip，SoC)。
在本实施例中，逻辑芯片110具有基板层111以及装置层112，其中装置层112中可形成相关逻辑电路，而本发明并不加以限制。逻辑芯片110的基板层111可为硅(Si)基板，并且装置层112的材料可为二氧化硅(SiO2)。逻辑芯片110包括多个键合组件113形成在装置层112的表面(远离基板层111的一侧)，并且逻辑芯片110的装置层112在邻近于基板层111的一侧可形成多个驱动电路115。多个驱动电路115通过多个金属走线114与多个键合组件113的至少一部分连接(电性连接)。
在本实施例中，输入输出芯片130具有基板层131以及装置层132，其中装置层132中可形成相关输入输出电路，而本发明并不加以限制。输入输出芯片130包括多个键合组件133形成在装置层132的表面(远离基板层131的一侧)，并且输入输出芯片130的装置层132在邻近于基板层131的一侧可形成驱动电路135。驱动电路135通过金属走线134与多个键合组件133连接。
在本实施例中，中介板150具有基板层151以及装置层152。中介板150的基板层151可为硅(Si)基板，并且装置层152的材料可为二氧化硅(SiO2)。中介板150包括多个键合组件153形成在装置层152的表面(远离基板层151的一侧)。在本实施例中，逻辑芯片110通过多个键合组件113的第一部分与中介板150的多个键合组件153的第一部分以接垫对接垫(Pad to Pad)的方式直接接合，并且输入输出芯片130通过多个键合组件133与中介板150的多个键合组件153的第二部分以接垫对接垫的方式直接接合。中介板150的多个键合组件153的第一部分的至少一部分通过金属走线154连接至多个键合组件153的第二部分的至少一部分。对此，逻辑芯片110可与输入输出芯片130通过键合组件113、键合组件153、金属走线154以及键合组件133传输数据信号。
在本实施例中，逻辑芯片120具有基板层121以及装置层122，其中装置层122中可形成相关逻辑电路，而本发明并不加以限制。逻辑芯片120的基板层121可为硅(Si)基板，并且装置层122的材料可为二氧化硅(SiO2)。逻辑芯片120包括多个键合组件123形成在装置层122的表面(远离基板层121的一侧)，并且逻辑芯片120的装置层122在邻近于基板层121的一侧可形成多个驱动电路125。多个驱动电路125通过多个金属走线124与多个键合组件123的第一部分连接。在本实施例中，逻辑芯片120可通过多个键合组件123与中介板150的多个键合组件153的第三部分以接垫对接垫的方式直接接合，并且中介板150的多个键合组件153的第一部分的至少另一部分通过金属走线154连接至多个键合组件153的第三部分。对此，逻辑芯片110可与逻辑芯片120通过键合组件113、键合组件153、金属走线154以及键合组件123传输数据信号。
在本实施例中，输入输出芯片140具有基板层141以及装置层142，其中装置层142中可形成相关输入输出电路，而本发明并不加以限制。输入输出芯片140包括多个键合组件143形成在装置层142的表面(远离基板层141的一侧)，并且输入输出芯片140的装置层142在邻近于基板层141的一侧可形成驱动电路145。驱动电路145通过金属走线144与多个键合组件143的的至少一部分连接。
在本实施例中，逻辑芯片120通过多个键合组件123的另一第一部分与中介板150的多个键合组件153的另一第一部分以接垫对接垫的方式直接接合，并且输入输出芯片140通过多个键合组件143与中介板150的多个键合组件153的另一第二部分以接垫对接垫的方式直接接合。中介板150的多个键合组件153的另一第一部分的至少一部分通过金属走线154连接至键合组件153的另一第二部分。对此，逻辑芯片120可与输入输出芯片140通过键合组件123、键合组件153、金属走线154以及键合组件143来进行通信，并可传输数据信号。
在本实施例中，中介板150的基板层151的邻近于装置层152的一侧还可形成多个深沟槽电容(deep trench capacitor，DTC)155。逻辑芯片110、120通过多个键合组件113、123的第二部分分别与中介板150的装置层152中的多个键合组件153的第四部份以接垫对接垫的方式直接接合，并且中介板150的装置层152中的多个键合组件153的所述第四部份通过金属走线154与多个深沟槽电容155连接。在本实施例中，中介板150的基板层151的邻近于装置层152的一侧可形成深沟槽电容155。逻辑芯片110、120可通过键合组件113、123的第二部分与中介板150的装置层152中的多个键合组件153的第四部份以接垫对接垫的方式直接接合，并且中介板150的装置层152中的多个键合组件的第四部份通过金属走线154与深沟槽电容155连接。对此，逻辑芯片110、120可通过键合组件113、123、153以及金属走线154与深沟槽电容155电性连接，以减少逻辑芯片110、120之间的IR压降(IR-drop)的情形。并且，中介板150还可形成多个硅通孔(Through Silicon Via，TSV)156贯通中介板150的基板层151并且伸入至少部分中介板150的装置层152，并且中介板150的装置层152中的多个键合组件153的第四部份还通过金属走线154与多个硅通孔156连接。对此，逻辑芯片110、120可通过键合组件113、123、153、金属走线154以及多个硅通孔156与外部电路电性连接，以传输电源信号和/或数据信号。另外，输入输出芯片130也可通过键合组件133、153、金属走线154以及多个硅通孔156与外部电路电性连接，以传输电源信号和/或数据信号。
因此，本实施例的芯片组100的逻辑芯片110、120以及输入输出芯片130、140可与中介板150以接垫对接垫(Pad to Pad)的方式直接接合，并且通过中介板150中的金属走线来进行电性连接，以传输电源信号和/或数据信号。换言之，本发明的芯片组100的逻辑芯片110、120以及输入输出芯片130、140之间无须额外的连接介面电路，例如裸片对裸片(Dieto Die,D2D)介面电路、高频宽存储器(High Bandwidth Memory，HBM)实体介面电路及其所需的凸块(bump)等。如此一来，本实施例的芯片组100因D2D介面电路所造成电路面积损失以及所造成的损耗可被有效地降低。
另外，值得注意的是，图1用于表示各芯片经由中介板进行电性连接的连接关系。本发明的逻辑芯片以及输入输出芯片在中介板上的设置位置以及数量并不限于图1所示，并且图1所示的各键合组件、驱动电路、金属走线、深沟槽电容以及硅通孔的设置位置以及数量也不限于图1所示。
图2是本发明的一实施例的芯片组的等效电路图。参考图1以及图2，以逻辑芯片110与输入输出芯片130之间的等效电路为例。图1中所示的任一个键合组件113与输入输出芯片130中对应的一个接合的键合组件153的等效电路可如图2所示。在本实施例中，逻辑芯片110可包括控制电路116、多个驱动电路115_1～115_8以及多个键合接垫115_1～115_8。输入输出芯片130可包括多个驱动电路135_1～135_8以及多个键合接垫135_1～135_8。键合接垫115_1～115_8以及键合接垫135_1～135_8之间可通过中介板150的多个键合接垫以及金属走线来连接。对此，控制电路116可例如接收多条信号线的多个数据信号a1～a8，并且控制电路116可将数据信号a1～a8直接提供至驱动电路115_1～115_8，以增强数据信号的信号强度后，通过键合接垫115_1～115_8以及中介板150中的对应的多个键合接垫以及金属走线来传输至输入输出芯片130的键合接垫135_1～135_8，其中中介板150中的金属走线可从逻辑芯片110与输入输出芯片130之间的芯片边缘200的一侧延伸至芯片边缘200的另一侧。键合接垫135_1～135_8可将接收的数据信号a1～a8再经由驱动电路135_1～135_8增强数据信号的信号强度后，传输至输入输出芯片130中的其他输入输出电路。换言之，本实施例的逻辑芯片110与输入输出芯片130之间的信号传输，无须透过额外连接电路来实现，特别是无须使用多路复用器(Mux)。因此，以此类推其他芯片之间的连接方式，图1的驱动电路115、125、135、145可为一种无多路复用器电路。并且，由于逻辑芯片110与输入输出芯片130之间与中介板150之间以混合键合的方式接合，因此无高静电放电(ElectrostaticDischarge，ESD)保护需求，而可无须设置额外的静电放电保护电路。
图3是本发明的一实施例的混合键合结构的示意图。参考图1以及图3，逻辑芯片110、120以及输入输出芯片130、140的键合组件113、123、133、143与中介板150的键合组件153之间可以是以混合键合(hybrid bonding)的方式接合。以逻辑芯片110的键合组件113与中介板150的键合组件153的接合方式为例。图1中所示的任一个键合组件113及其对应一个接合的键合组件153可实现如图3所示的多个键合组件，但本发明并不限于此。图1中所示的任一个键合组件113及其对应一个接合的键合组件153可由多个键合组件所形成的组件阵列(例如30×60个键合组件)来实现之。如图3所示，键合组件113设置在装置层112，并且键合组件153设置在装置层152。键合组件113以及键合组件153可包括键合接垫1131、1531、支柱(pillar)1132、1532以及金属接垫1133、1533。键合组件153的键合面1534与装置层152的表面S1为等高，并且键合组件113的键合面1134与装置层112的表面S2为等高。键合组件113的键合面1134与键合组件153的键合面1534直接接合。键合组件113和键合组件153的材料包括但不限于铜(Cu)或铝(Al)。因此，逻辑芯片110与中介板150之间可通过键合组件113以及键合组件153进行信号传输，并且本发明的其他芯片的键合组件与中介板150的键合组件的接合方式可以此类推。
图4是本发明的一实施例的芯片组的制造方法的流程图，参考图4以及图1，芯片组100可依照以下步骤S410～S450来制造之。在步骤S410，形成多个键合组件113在逻辑芯片110的装置层112。详细而言，逻辑芯片110的基板层111上可先分别形成金属走线114、驱动电路115以及相关逻辑电路，并形成氧化物钝化层(Oxide Passivation Layer)覆盖金属走线114、驱动电路115以及相关逻辑电路，以形成装置层112。接着，可形成多个键合组件113在装置层112的远离基板层111的一侧的表面上，并且再次形成氧化物钝化层覆盖多个键合组件113，其中多个键合组件113的键合面分别与装置层112的表面同高且裸露。
在步骤S420，形成多个键合组件133在输入输出芯片130的装置层132。详细而言，输入输出芯片130的基板层131上可先分别形成金属走线134、驱动电路135以及相关输入输出电路，并形成氧化物钝化层覆盖金属走线134、驱动电路135以及相关逻辑电路，以形成装置层132。接着，可形成多个键合组件133在装置层132的远离基板层131的一侧的表面上，并且再次形成氧化物钝化层覆盖多个键合组件133，其中多个键合组件133的键合面分别与装置层132的表面同高且裸露。
在步骤S430，形成多个键合组件153在中介板150的装置层152，并且将多个键合组件153的第一部分的至少一部分通过金属走线154连接至多个键合组件153的第二部分。在本实施例中，中介板150可为硅中介板(Silicon Interposer)，因此基板层151可为硅基板。详细而言，中介板150的基板层151上可先形成多个硅通孔156贯通中介板150的基板层151，并且形成多个深沟槽电容155在中介板150的基板层151的邻近于装置层152的一侧。接着，可形成金属走线154，以连接多个深沟槽电容155以及多个硅通孔156，并且形成氧化物钝化层覆盖金属走线154、多个深沟槽电容155以及多个硅通孔156，以形成装置层152。接着，可形成多个键合组件153在装置层152的远离基板层151的一侧的表面上，并且再次形成氧化物钝化层覆盖多个键合组件153，其中多个键合组件153的键合面与装置层152的表面同高且裸露。
在步骤S440，将逻辑芯片110的多个键合组件113的第一部分与中介板150的多个键合组件153的第一部分以接垫对接垫的方式直接接合。在步骤S450，将输入输出芯片130的多个键合组件133与中介板150的多个键合组件153的第二部分以接垫对接垫的方式直接接合。
对此，逻辑芯片120以及输入输出芯片140的形成方式可以此类推。并且，基于前述制造流程中，本实施例的芯片组100无需形成额外的连接电路或连接介面的架构，因此本实施例的制造方法可有效地制造具有较小芯片面积或较高芯片密度的芯片组100。
图5A至图5I是本发明的一实施例的芯片组的制造流程示意图，参考图1、图5A至图5I，本实施例可对于上述图1实施例的芯片组100进行进一步的制造流程，以与存储器芯片整合。如图5A所示，图1的芯片组100的逻辑芯片110、120以及输入输出芯片130、140之间可形成有机钝化(organic passivation)层161，并且形成临时载板162在逻辑芯片110、120以及输入输出芯片130、140的基板层111、121、131、141的一侧表面。接着，如图5B所示，可翻转芯片组，并且切割中介板150的基板层151，以使中介板150的的基板层151中的多个硅通孔156可裸露。接着，如图5C所示，可形成多个凸块163连接多个硅通孔156，并且移除临时载板162后再翻转芯片组。接着，如图5D所示，可形成存储器芯片170，其中存储器芯片170包括裸露的多个金属走线171以及多个凸块172。接着，如图5E所示，可于临时载板181上形成重分布层(Redistribution Layer)182，其中重分布层182包括多个金属走线183，并且裸露于重分布层182的表面。接着，如图5F所示，可将重分布层182的多个金属走线183通过多个凸块163与中介板150的多个硅通孔156连接，并且可通过存储器芯片170的多个凸块172与存储器芯片170的多个金属走线171连接。因此，芯片组100可与存储器芯片170通过重分布层182来进行数据信号的传输，并且芯片组100还可通过重分布层182与外部其他功能电路电性连接。接着，如图5G所示，可将底部填充(underfill)材料191填充至芯片组100、存储器芯片170与重分布层182之间，并且可将封胶(molding)材料192填充至芯片组100以及存储器芯片170之间。详细而言，封胶材料192可填充至逻辑芯片110与逻辑芯片120之间、逻辑芯片110与输入输出芯片130之间，逻辑芯片120与输入输出芯片140之间以及输入输出芯片130与存储器芯片170之间，其中封胶材料192为有机材料。接着，如图5H所示，可移除临时载板181，并且形成临时载板193在逻辑芯片110、120、输入输出芯片130、140的基板层111、121、131、141以及存储器芯片170的一侧表面。接着，如图5I所示，可于重分布层182的一侧表面形成铜柱194以及凸块195，以用于使重分布层182的多个金属走线183可通过铜柱194以及凸块195与外部其他功能电路电性连接。最后，可移除临时载板193，以完成芯片组500的制造流程。因此，图1实施例的芯片组100可与存储器芯片170整合，以形成芯片组500。
图6是本发明的一实施例的芯片组的俯视结构图。参考图6，本实施例为本发明的一个芯片组的俯视结构范例。图6的芯片组600包括形成在重分布层652(如同上述的重分布层182)上的芯片组630以及多个存储器芯片641～644。芯片组630与多个存储器芯片641～644的整合方式可如上述图5A至图5I实施例的说明。在本实施例中，芯片组630可包括多个逻辑芯片611～618以及多个输入输出芯片621～628，并且多个逻辑芯片611～618以及多个输入输出芯片621～628可形成在中介板651(如同上述的中介板150)上。逻辑芯片611～618位于芯片组600的中心位置，输入输出芯片621～628环绕设置于逻辑芯片611～618的外侧。存储器芯片641～644位于输入输出芯片621～628的外侧。对此，由于多个逻辑芯片611～618以及多个输入输出芯片621～628之间的连接方式以及通信手段可如上述图1至图3实施例的说明，而无需于中介板651上额外形成相关连接介面电路于逻辑芯片与输入输出芯片之间，以使逻辑芯片与输入输出芯片进行通信，因此芯片组630可具有较小芯片面积或较高芯片密度的优点。
综上所述，本发明的芯片组及其制造方法，可通过将逻辑芯片以及输入输出芯片以接垫对接垫的方式直接接合至中介板上，并通过中介面内的金属走线来形成信号传输路径，以减少设置其他连接介面电路的空间。特别是应用在人工智慧芯片的芯片组或为了符合高性能运算需求而设置多逻辑核心以及高密度存储器的芯片组，本发明的芯片组设计可有效地降低功耗以及缩小芯片面积。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (26)

1.一种芯片组，其特征在于，包括：
逻辑芯片，具有第一装置层以及第一基板层，并且包括多个第一键合组件设置在所述第一装置层；
输入输出芯片，具有第二装置层以及第二基板层，并且包括多个第二键合组件设置在所述第二装置层；以及
中介板，具有第三装置层以及第三基板层，并且包括多个第三键合组件设置在所述第三装置层，
其中所述逻辑芯片通过所述多个第一键合组件的第一部分与所述中介板的所述多个第三键合组件的第一部分以接垫对接垫的方式直接接合，并且所述输入输出芯片通过所述多个第二键合组件与所述中介板的所述多个第三键合组件的第二部分以接垫对接垫的方式直接接合，
其中所述多个第三键合组件的所述第一部分的至少一部分通过第一金属走线连接至所述多个第三键合组件的所述第二部分的至少一部分。
2.根据权利要求1所述的芯片组，其特征在于，所述逻辑芯片通过所述多个第一键合组件的所述第一部分与所述中介板的所述多个第三键合组件的所述第一部分以混合键合的方式接合，并且所述输入输出芯片通过所述多个第二键合组件与所述中介板的所述多个第三键合组件的所述第二部分以混合键合的方式接合，
其中所述多个第一键合组件、所述多个第二键合组件以及所述多个第三键合组件分别包括：
键合接垫，具有键合面；
支柱，所述支柱的一端连接所述键合接垫；以及
金属接垫，与所述支柱的另一端连接。
3.根据权利要求1所述的芯片组，其特征在于，所述中介板的所述第三基板层的邻近于所述第三装置层的一侧包括深沟槽电容，并且所述逻辑芯片通过所述多个第一键合组件的第二部分与所述中介板的所述第三装置层中的所述多个第三键合组件的第四部份以接垫对接垫的方式直接接合，并且所述中介板的所述第三装置层中的所述多个第三键合组件的所述第四部份通过第三金属走线与所述深沟槽电容连接。
4.根据权利要求1所述的芯片组，其特征在于，还包括：
另一逻辑芯片，具有第四装置层以及第四基板层，并且包括多个第四键合组件设置在所述第四装置层，
其中所述另一逻辑芯片通过所述多个第四键合组件与所述中介板的所述多个第三键合组件的第三部分以接垫对接垫的方式直接接合，并且所述多个第三键合组件的所述第一部分的至少另一部分通过第二金属走线连接至所述多个第三键合组件的所述第三部分的至少一部分。
5.根据权利要求4所述的芯片组，其特征在于，所述中介板包括多个硅通孔贯通所述中介板的所述第三基板层并且伸入至少部分所述中介板的所述第三装置层，并且所述中介板的所述第三装置层中的所述多个第三键合组件的所述第四部份通过第三金属走线与所述多个硅通孔连接。
6.根据权利要求5所述的芯片组，其特征在于，还包括：
重分布层，其中所述重分布层通过多个凸块与所述中介板的所述多个硅通孔连接。
7.根据权利要求6所述的芯片组，其特征在于，还包括：
存储器芯片，通过另多个凸块连接于所述重分布层。
8.根据权利要求7所述的芯片组，其特征在于，还包括：
封胶，填充于所述逻辑芯片与所述另一逻辑芯片之间、所述逻辑芯片与所述输入输出芯片之间以及所述输入输出芯片与所述存储器芯片之间，其中所述封胶为有机材料。
9.根据权利要求7所述的芯片组，其特征在于，所述逻辑芯片和所述另一逻辑芯片位于所述芯片组的中心位置，所述输入输出芯片环绕设置于所述逻辑芯片和所述另一逻辑芯片的外侧，所述存储器芯片位于所述输入输出芯片的外侧。
10.根据权利要求4所述的芯片组，其特征在于，所述逻辑芯片与所述输入输出芯片通过所述第一走线传输数据信号，且所述逻辑芯片与所述另一逻辑芯片通过所述第二走线传输数据信号。
11.根据权利要求1所述的芯片组，其特征在于，所述逻辑芯片的所述第一装置层在邻近于所述第一基板层的一侧包括第一驱动电路，并且所述第一驱动电路通过第四金属走线与所述多个第一键合组件的所述第一部分连接。
12.根据权利要求11所述的芯片组，其特征在于，所述输入输出芯片的所述第二装置层在邻近于所述第二基板层的一侧包括第二驱动电路，并且所述第二驱动电路通过第五金属走线与所述多个第二键合组件的至少一部分连接。
13.根据权利要求12所述的芯片组，其特征在于，所述第一驱动电路以及所述第二驱动电路分别为无多路复用器电路。
14.一种芯片组的制造方法，其特征在于，包括：
形成多个第一键合组件在逻辑芯片的第一装置层；
形成多个第二键合组件在输入输出芯片的第二装置层；
形成多个第三键合组件在中介板的第三装置层，并且将所述多个第三键合组件的第一部分的至少一部分通过第一金属走线连接至所述多个第三键合组件的第二部分的至少一部分；
将所述逻辑芯片的所述多个第一键合组件的第一部分与所述中介板的所述多个第三键合组件的所述第一部分以接垫对接垫的方式直接接合；以及
将所述输入输出芯片的所述多个第二键合组件与所述中介板的所述多个第三键合组件的所述第二部分以接垫对接垫的方式直接接合。
15.根据权利要求14所述的制造方法，其特征在于，所述逻辑芯片通过所述多个第一键合组件的所述第一部分与所述中介板的所述多个第三键合组件的所述第一部分以混合键合的方式接合，并且所述输入输出芯片通过所述多个第二键合组件与所述中介板的所述多个第三键合组件的所述第二部分以混合键合的方式接合，
其中所述多个第一键合组件、所述多个第二键合组件以及所述多个第三键合组件分别包括：
键合接垫，具有键合面；
支柱，所述支柱的一端连接所述键合接垫；以及
金属接垫，与所述支柱的另一端连接。
16.根据权利要求14所述的制造方法，其特征在于，还包括：
形成深沟槽电容在所述中介板的第三基板层的邻近于所述第三装置层的一侧；
将所述逻辑芯片的所述多个第一键合组件的第二部分与所述中介板的所述第三装置层中的所述多个第三键合组件的第四部份以接垫对接垫的方式直接接合；以及
将所述中介板的所述第三装置层中的所述多个第三键合组件的所述第四部份通过第三金属走线与所述深沟槽电容连接。
17.根据权利要求14所述的制造方法，其特征在于，还包括：
形成多个第四键合组件在另一逻辑芯片的第四装置层；以及
将所述另一逻辑芯片的所述多个第四键合组件与所述中介板的所述多个第三键合组件的第三部分以接垫对接垫的方式直接接合，
其中所述多个第三键合组件的所述第一部分的至少另一部分通过第二金属走线连接至所述多个第三键合组件的所述第三部分的至少一部分。
18.根据权利要求17所述的制造方法，其特征在于，还包括：
形成多个硅通孔贯通所述中介板的所述第三基板层并且伸入至少部分所述中介板的所述第三装置层；以及
将所述中介板的所述第三装置层中的所述多个第三键合组件的所述第四部份通过第三金属走线与所述多个硅通孔连接。
19.根据权利要求18所述的制造方法，其特征在于，还包括：
将重分布层通过多个凸块与所述中介板的所述多个硅通孔连接。
20.根据权利要求19所述的制造方法，其特征在于，还包括：
将存储器芯片通过另多个凸块连接于所述重分布层。
21.根据权利要求20所述的芯片组，其特征在于，还包括：
形成填充于所述逻辑芯片与所述另一逻辑芯片之间、所述逻辑芯片与所述输入输出芯片之间以及所述输入输出芯片与所述存储器芯片之间的封胶，其中所述封胶为有机材料。
22.根据权利要求20所述的芯片组，其特征在于，所述逻辑芯片和所述另一逻辑芯片位于所述芯片组的中心位置，所述输入输出芯片环绕设置于所述逻辑芯片和所述另一逻辑芯片的外侧，所述存储器芯片位于所述输入输出芯片的外侧。
23.根据权利要求17所述的芯片组，其特征在于，所述逻辑芯片与所述输入输出芯片通过所述第一走线传输数据信号，且所述逻辑芯片与所述另一逻辑芯片通过所述第二走线传输数据信号。
24.根据权利要求14所述的制造方法，其特征在于，还包括：
形成第一驱动电路在所述逻辑芯片的所述第一装置层在邻近于所述第一基板层的一侧；以及
将所述第一驱动电路通过第四金属走线与所述多个第一键合组件的至少一部分连接。
25.根据权利要求24所述的制造方法，其特征在于，还包括：
形成第二驱动电路在所述输入输出芯片的所述第二装置层在邻近于所述第二基板层的一侧；以及
将所述第二驱动电路通过第五金属走线与所述多个第二键合组件的至少一部分连接。
26.根据权利要求25所述的制造方法，其特征在于，所述第一驱动电路以及所述第二驱动电路分别为无多路复用器电路。
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CN111812483A (zh) * 2019-04-10 2020-10-23 联发科技股份有限公司 用于测试芯片或管芯的设备
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