CN1156902A - 制造具有互补金属氧化物半导体结构半导体器件的方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 51
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 51
- 239000010703 silicon Substances 0.000 claims abstract description 51
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000002844 melting Methods 0.000 claims abstract description 14
- 230000008018 melting Effects 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 239000003870 refractory metal Substances 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 239000010941 cobalt Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 6
- 229910052750 molybdenum Inorganic materials 0.000 claims 6
- 239000011733 molybdenum Substances 0.000 claims 6
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 claims 3
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 230000002265 prevention Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 46
- 238000010438 heat treatment Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 235000016768 molybdenum Nutrition 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
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Abstract
制造在源/漏区中有低电阻率硅化物层的CMOS结构的半导体器件。为了减小n-型源/漏区(112)的电阻率要形成硅化物层,在形成高熔点金属硅化物层(117)前,在其上形成未掺杂硅层(113)。通过硅层离子注入,形成n-型源/漏区。这样便可获得浅结p型源/漏区(115),防止离子注入时间增加,且可以不减小离子注入能量地快速生产。
Description
本发明涉及制造半导体器件的方法,特别是涉及制造具有CMOS结构和源/漏区具有低电阻率硅化物层,能使MOS晶体管结构小型化的半导体器件的制造方法。
由于最近趋于使半导体器件小型化,因此要减少源/漏区的面积,增加和源/漏区相连的互连电阻。为了增加工作速度,建议半导体器件具有低电阻率的MOS晶体管,并使晶体管的源/漏区具有高熔点金属硅化物层。并且使半导体器件成为具有包括P-沟道MOS晶体管和n-沟道MOS晶体管的CMOS结构半导体器件,已采用如图1A和图1B所示的工艺。
如图1A所示,在P-型硅衬底101的表面区中形成n-型阱102,在衬底101的表面部分形成元件隔离绝缘膜103,栅绝缘膜104,和栅电极105。然后,在n-型阱102中,通过掺入p-型杂质,形成p-型LDD109和源/漏区115。同样,在p型衬底101中,通过掺入n-型杂质,形成n-型LDD107和n-型源/漏区112。在整个表面上淀积诸如钛或钴的高熔点金属116后,热处理该结构,使高熔点金属116和硅进行反应,然后腐蚀掉没进行反应的高熔点金属。如图1B所示,由这种工艺,在源/漏区112和115选择地形成低电阻率的硅化物层117。
但是,发现,对于上述制造方法,因图形宽度变窄,在源/漏区112中形成的硅化物层117的电阻增加。这是因为在硅表面存在形成n-型源/漏区112的高浓度杂质,例如砷和磷,阻止了高熔点金属和硅的反应,影响了较低电阻率的性能。
具有CMOS结构的现有技术中的半导体器件的另一个问题是,难于制造精细结构的p-型MOS晶体管。为了制造p-型MOS晶体管源/漏区115,需要把诸如硼或者BF2的1×1015到1×1016cm-2的p-型杂质注入到n-型阱102中来制造n-型阱102的有源区。这意味着p-型MOS晶体管结构小型化需要减少离子注入能量,这样减少杂质层的结深。对于目前的离子注入技术,离子注入能量的较低限量是大约10kev。此外,对于30kev及以下的离子注入能量,不可避免的减少离子注入电流量,这导致离子注入的时间大量地增加,增加了制造半导体器件的时间和成本。
例如在1994 IEDM Technical Digest,pp.687-690中提出了解决这个问题的方法,特别是解决在n-型源/漏区112中硅化物层117电阻增加的问题的方法。如图2所示,在提出的这种方法中,在形成n-型源/漏区112后,在n-型源/漏区112上外延生长硅形成的没掺杂硅层113的整个表面上淀积高熔点金属,然后对该结构进行热处理,使高熔点金属和没掺杂的硅层发生反应,于是形成硅化物层。用这种方法,的确能抑制n-型源/漏区硅化物层的电阻率的增加,但是难以满足快速形成浅结p-型源/漏区的要求。
本发明的目的是克服现有技术中存在的问题,并且提供制造具有CMOS结构半导体器件的方法,它能使n-型源/漏区硅化物层的电阻率减少,还能够快速地形成浅结p-型源/漏区,这样便可实现结构小型化和提高工作速度。
按照本发明的一个方案,提供制造半导体器件的方法,该器件具有p-型MOS晶体管和n-型MOS晶体管,还具有至少在每个MOS晶体管的源/漏区上形成的高熔点金属硅化物层,该方法包括下列步骤:
在形成位于硅衬底上面的每个MOS晶体管的栅绝缘膜和栅电极以后,通过掺杂形成n-型MOS晶体管的源/漏区;
在n-型和p-型MOS晶体管的每一个源/漏区上形成硅层;
通过硅层形成p-型MOS晶体管的源/漏区;
通过在整个表面上淀积高熔点金属,使高熔点金属和硅层反应形成高熔点金属硅化物层。
在按照本发明形成的半导体器件的n-型MOS晶体管中,在源/漏区上形成未掺杂的硅层后,形成高熔点金属的硅化物层。这样便可减少n-型源/漏区的电阻率。此外,在p-型MOS晶体管的源/漏区中也可形成高熔点金属的硅化物层。这样便不需要减少离子注入能量,于是,能够形成浅p-型晶体管源/漏区,防止离子注入时间增长,可快速和低成本地制造半导体器件。
通过下面结合附图对优选实施例的说明,本发明的上述和其它目的,特征和优点将显而易见。
图1A和图1B是常规半导体器件的剖视图,用于说明该器件制造方法的各步骤;
图2是另一种常规半导体器件的剖视图,用于说明该器件制造方法的各步骤;
图3A到图3J是用于说明按照本发明第1实施例制造方法的半导体器件的剖视图;
图4A到图4E是用于说明按照本发明第2实施例的制造方法的半导体器件的剖视图;
图5A和图5B是用于说明按照本发明第3实施例的制造方法的半导体器件的剖视图。
下面结合附图说明本发明的优选实施例。
图3A到图3J是表示按照本发明第1实施例制造半导体器件方法各连续步骤的剖视图。如图3A所示,在p-型硅衬底101内形成n-型阱102后,在p-型硅衬底101表面部分,连续地形成元件隔离膜103,栅绝缘膜104和栅电极105。在该实施例中,栅电极105是单层多晶硅膜,但是它也可以是硅化物/多晶硅叠层。
接着,如图3B所示,用光致抗蚀剂层106覆盖p-MOS晶体管区,并且,利用30kev能量,注入2×1013cm-2浓度的n-型杂质,在n型MOS晶体管区形成低杂质浓度的源/漏区,即n-型LDD区107。如图3C所示,用光致抗蚀剂层108覆盖n-型MOS晶体管区,利用10kev能量,2×1013cm-2浓度(剂量),离子注入p-型杂质,在p-型MOS晶体管中形成p-型LDD区109。在1000℃热处理10秒钟,活化LDD区107和109。
在整个表面上淀积氧化硅膜,然后各向异性的腐蚀,在栅极105的侧面形成侧壁氧化层110,如图3D所示。如图3E所示,用光致抗蚀剂层111覆盖P-型MOS晶体管区,通过以3×1015cm-2浓度,30kev能量,离子注入诸如As的n-型杂质,并且在1000℃热处理10秒进行活化,在n-型MOS晶体管的源/漏形成区中形成高杂质浓度的n-型源/漏区112。
如图3F所示,在露出硅的区域,在Si2H6气氛中,在1013Pa(Pascal)和600-700℃条件下,外延生长外延硅层113。对于选择外延生长工艺,参考1995 Symposium on Technology Digest ofTechnical papers,pp,21-22所表示的技术。如图3G所示,用光致抗蚀剂114覆盖n-型MOS晶体管区,并且用3×1015cm-2浓度,30kev能量,离子注入诸如BF2的p-型杂质,在1000℃热处理10秒进行活化,在p-型MOS晶体管区中形成高杂质浓度的p-型源/漏区115。这样形成的源/漏区115和没有外延生长而只离子注入的情况相比,由于有外延硅层113的厚度,在衬底101表面下面有较小的结深。例如,当硅层113是30nm厚时,和没有外延生长只进行离子注入情况相比,沟道长度减少大约0.1μm。
如图3H所示,例如在整个表面淀积30nm厚的钛116,然后在氮气氛中在640℃把该结构热处理20秒,在n-型MOS晶体管中没掺杂的外延硅层113和钛116之间,和p-型MOS晶体管中含BF2的外延硅层113和钛116之间产生硅化反应。如图3I所示,在硅层113的表面部分形成大约厚30nm的硅化钛层117,而在硅化钛层117上面形成氮化钛层118。在侧壁110上面没有形成硅化钛。它只是由氮化钛构成。这样形成的硅化钛层117由称为“C49结构”的高电阻率硅化钛组成。
以后,用包含氨和过氧化氢的混合溶液选择地除掉氮化钛层118,在源/漏区112和115及栅电极105上选择地留下氮化钛层118以代替硅化钛层117。把该结构在氮气氛中在850℃热处理10秒钟,由此,把具有高电阻率C49结构的硅化钛层转相到低电阻率的C56结构,以使硅化钛层117具有7Ω/口的电阻率。如图3J所示,利用众所周知的方法,形成层间绝缘膜119和金属互连层120,这样制成具有CMOS结构的半导体器件。
在本实施例中,在形成高熔点金属的硅化物层117之前,在n-型MOS晶体管的源/漏区112上面形成没掺杂的外延硅层113层。这便可使n-型源/漏区112的电阻率降低。此外,利用外延生长硅层113进行离子注入,形成p-型MOS晶体管的源/漏区115。这样形成的源/漏区115可以具有浅结深度。于是不必减少离子注入能量,就可以防止离子注入时间增加,且可以快速低成本地制造半导体器件。
图4A到图4E表示本发明第2实施例。在第1实施例中,形成p-型MOS晶体管的p-型LDD109,但是,在窄宽度的侧壁110处不需要形成上述的LDD结构。如图4A所示,形成n-型MOS晶体管的n-型LDD107,如图4B所示,形成侧壁110,而没有形成p-型晶体管的任一p型LDD。然后,如图4C所示,形成n-型MOS晶体管的n-型源/漏区112,如图4D所示,通过选择外延生长,形成硅层113。如图4E所示,形成p-型MOS晶体管的p-型源/漏区115。当侧壁10的宽度为大约50nm时,p-型MOS晶体管的源/漏区115的结达到栅电极,于是不需要LDD。其后续各步骤类似于图3H所示步骤及其后面相同步骤。
图5A和图5B表示本发明第3实施例。在前面的第1实施例中,通过选择外延生长硅,在栅电极105上形成硅层。但是,通过选择外延生长形成硅层113后,把离子注入到p-型MOS晶体管的源/漏区115中。这意味着在栅电极105上没有形成硅层。如图5A所示,在形成栅电极105时,例如,在栅电极上,形成厚度大约为100nm的氧化硅绝缘膜121。如图5B所示,象第1实施例那样,在形成n-型MOS晶体管的n-型LDD107及p-型MOS晶体管的p-型LDD109后,形成侧壁10。于是,只在源/漏区暴露出硅衬底101。其后续步骤和图3E所示的步骤及其后续步骤相同。
上述说明涉及把钛用作高熔点金属的情况。但是,按照本发明,它也能利用诸如钴、钼等其它高熔点金属。
上面利用优选实施例说明了本发明,但是应该了解,上述实施例只是说明本发明而不是进行限制,在不脱离权利要求限定的本发明的实际范围的情况下,可在附带权利要求的范围内进行各种变化。
Claims (15)
1.一种制造半导体器件的方法,该器件具有p-型MOS晶体管和n-型MOS晶体管,至少在每个MOS晶体管的源/漏区(112、115)上形成高熔点金属硅化物层(117),所述方法包括下列步骤:
在形成位于硅衬底(101)上面的每个MOS晶体管的栅绝缘膜(104)和栅电极(105)后,通过掺杂,形成所述n-型MOS晶体管的源/漏区(112);
在所述n-型和p-型MOS晶体管的每个源/漏区(112、115)上面,形成硅层(113);
通过所述硅层,形成所述p-型MOS晶体管的源/漏区(115);
通过在整个表面淀积高熔点金属(116),使所述高熔点金属和所述硅层发生反应,形成所述高熔点金属硅化物层。
2.一种制造半导体器件的方法,该器件具有p-型MOS晶体管和n-型MOS晶体管,且至少在每个MOS晶体管的源/漏区(112、115)上形成高熔点金属硅化物层(117),所述方法包括下列步骤:
在形成位于硅衬底(101)上面的每个所述MOS晶体管的栅绝缘膜(104)和栅电极(105)后,通过掺杂形成所述p-型MOS晶体管和所述n-型MOS晶体管中至一个作为低杂质浓度区(107,109)的源/漏区(112、115);
在每个MOS晶体管所述栅电极的侧面,形成侧壁(110);
通过离子注入杂质,形成所述n-型MOS晶体管的作为高杂浓度区的源/漏区(112);
在n-型和p-型MOS晶体管的每个源/漏区(112、115)上,通过选择外延生长工艺,形成硅层(113);
通过所述硅层,利用离子注入p-型杂质,形成所述p-型MOS晶体管的作为高杂质浓度区的源/漏区(115);
通过在整个表面上淀积高熔点金属层(116),使所述高熔点金属和所述硅层进行反应,形成高熔点金属硅化物层(117);以及除掉没硅化反应的残留的高熔点金属。
3.按照权利要求2的制造半导体器件的方法,其特征是,只在所述n-型MOS晶体管的源/漏区(115),形成低杂质浓度区。
4.按照权利要求1的制造半导体器件的方法,其特征是,在源/漏区(112、115)上形成的所述硅层是没掺杂的硅层。
5.按照权利要求2的制造半导体器件的方法,其特征是,在源/漏区(112、115)上形成的所述硅层是没掺杂的硅层。
6.按照权利要求3的制造半导体器件的方法,其特征是,在源/漏区(112、115)上形成的所述硅层是没掺杂的硅层。
7.按照权利要求1的制造半导体器件的方法,其特征是,从由钛、钴、钼组成的组中选择所说高熔点的金属,从由硅化钛层、硅化钴层、硅化钼层组成的组中选择所述高熔点金属硅化物层。
8.按照权利要求2的制造半导体器件的方法,其特征是,从由钛、钴、钼组成的组中选择所说高熔点的金属,从由硅化钛层,硅化钴层、硅化钼层组成的组中选择所述高熔点金属硅化物层。
9.按照权利要求3的制造半导体器件的方法,其特征是,从由钛、钴、钼组成的组中选择所述高熔点的金属,从由硅化钛层、硅化钴层、硅化钼层中选择所述高熔点金属的硅化物层。
10.按照权利要求1的制造半导体器件的方法,其特征是,在源/漏区(112、115)上面形成的所述硅层的厚度至少为30nm。
11.按照权利要求2的制造半导体器件的方法,其特征是,在源/漏区(112、115)上面形成的所述硅层的厚度至少为30nm。
12.按照权利要求3的制造半导体器件的方法,其特征是,在源/漏区(112、115)上面形成的所述硅层的厚度至少为30nm。
13.按照权利要求4的制造半导体器件的方法,其特征是,在源/漏区(112、115)上面形成的所述硅层的厚度至少为30nm。
14.按照权利要求5的制造半导体器件的方法,其特征是,在源/漏区(112、115)上面形成的所述硅层的厚度至少为30nm。
15.按照权利要求6的制造半导体器件的方法,其特征是,在源/漏区(112、115)上面形成的所述硅层的厚度至少为30nm。
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JP308355/95 | 1995-10-31 | ||
JP308355/1995 | 1995-10-31 | ||
JP7308355A JP2751895B2 (ja) | 1995-10-31 | 1995-10-31 | 半導体装置の製造方法 |
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CN1156902A true CN1156902A (zh) | 1997-08-13 |
CN1060588C CN1060588C (zh) | 2001-01-10 |
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US (1) | US5691225A (zh) |
JP (1) | JP2751895B2 (zh) |
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CN1327511C (zh) * | 2002-08-28 | 2007-07-18 | 精工电子有限公司 | 半导体器件的制造方法 |
CN102683207A (zh) * | 2011-03-07 | 2012-09-19 | 北大方正集团有限公司 | 一种mos管的制作方法及mos管器件 |
CN103871967A (zh) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管的形成方法 |
CN107994064A (zh) * | 2016-10-26 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
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US5956591A (en) * | 1997-02-25 | 1999-09-21 | Advanced Micro Devices, Inc. | Method of making NMOS and PMOS devices having LDD structures using separate drive-in steps |
US6858484B2 (en) | 2000-02-04 | 2005-02-22 | Hitachi, Ltd. | Method of fabricating semiconductor integrated circuit device |
US6693001B2 (en) * | 1997-03-14 | 2004-02-17 | Renesas Technology Corporation | Process for producing semiconductor integrated circuit device |
JP3199015B2 (ja) * | 1998-02-04 | 2001-08-13 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP3554483B2 (ja) | 1998-04-22 | 2004-08-18 | シャープ株式会社 | Cmos型固体撮像装置 |
US5904517A (en) * | 1998-07-08 | 1999-05-18 | Advanced Micro Devices, Inc. | Ultra thin high K spacer material for use in transistor fabrication |
US6235630B1 (en) | 1998-08-19 | 2001-05-22 | Micron Technology, Inc. | Silicide pattern structures and methods of fabricating the same |
JP5070189B2 (ja) * | 1998-08-25 | 2012-11-07 | シャープ株式会社 | 半導体集積回路の静電気保護装置、その製造方法および静電気保護装置を用いた静電気保護回路 |
US6150243A (en) * | 1998-11-05 | 2000-11-21 | Advanced Micro Devices, Inc. | Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer |
KR20000066155A (ko) * | 1999-04-13 | 2000-11-15 | 황인길 | 반도체 소자의 얕은 접합 및 실리사이드 형성 방법 |
WO2000079586A1 (fr) * | 1999-06-24 | 2000-12-28 | Hitachi, Ltd. | Procede de production de dispositif a circuit integre semi-conducteur et dispositif a circuit integre semi-conducteur |
TW439299B (en) * | 2000-01-11 | 2001-06-07 | United Microelectronics Corp | Manufacturing method of metal oxide semiconductor having selective silicon epitaxial growth |
JP2002359293A (ja) * | 2001-05-31 | 2002-12-13 | Toshiba Corp | 半導体装置 |
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US7002208B2 (en) * | 2001-07-02 | 2006-02-21 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method of the same |
JP2003158195A (ja) * | 2001-11-20 | 2003-05-30 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6900091B2 (en) * | 2002-08-14 | 2005-05-31 | Advanced Analogic Technologies, Inc. | Isolated complementary MOS devices in epi-less substrate |
US7112483B2 (en) * | 2003-08-29 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a device having multiple silicide types |
US7384853B2 (en) * | 2005-08-25 | 2008-06-10 | United Microelectronics Corp. | Method of performing salicide processes on MOS transistors |
KR101337319B1 (ko) | 2006-10-04 | 2013-12-06 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 디바이스 및 이의 제작 방법 |
JP6407651B2 (ja) * | 2014-10-01 | 2018-10-17 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
FR3097076B1 (fr) * | 2019-06-05 | 2023-08-18 | St Microelectronics Crolles 2 Sas | Prises de contact pour composant électronique |
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JPH0745821A (ja) * | 1993-07-28 | 1995-02-14 | Ricoh Co Ltd | 半導体装置の製造方法 |
-
1995
- 1995-10-31 JP JP7308355A patent/JP2751895B2/ja not_active Expired - Fee Related
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1996
- 1996-10-21 TW TW085112859A patent/TW313697B/zh active
- 1996-10-30 KR KR1019960049914A patent/KR100237276B1/ko not_active IP Right Cessation
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1327511C (zh) * | 2002-08-28 | 2007-07-18 | 精工电子有限公司 | 半导体器件的制造方法 |
CN102683207A (zh) * | 2011-03-07 | 2012-09-19 | 北大方正集团有限公司 | 一种mos管的制作方法及mos管器件 |
CN103871967A (zh) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管的形成方法 |
CN107994064A (zh) * | 2016-10-26 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
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JP2751895B2 (ja) | 1998-05-18 |
US5691225A (en) | 1997-11-25 |
TW313697B (zh) | 1997-08-21 |
JPH09129749A (ja) | 1997-05-16 |
CN1060588C (zh) | 2001-01-10 |
KR100237276B1 (ko) | 2000-01-15 |
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