CN115152032B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN115152032B
CN115152032B CN202180008223.0A CN202180008223A CN115152032B CN 115152032 B CN115152032 B CN 115152032B CN 202180008223 A CN202180008223 A CN 202180008223A CN 115152032 B CN115152032 B CN 115152032B
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CN115152032A (zh
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中村浩尚
大河亮介
井上翼
木村晃
安田英司
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Nuvoton Technology Corp Japan
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    • HELECTRICITY
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    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/63Vertical IGFETs
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/665Vertical DMOS [VDMOS] FETs having edge termination structures
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    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
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    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126Top-view geometrical layouts of the regions or the junctions
    • H10D62/127Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D62/149Source or drain regions of field-effect devices
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    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
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    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
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    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN202180008223.0A 2021-09-17 2021-09-17 半导体装置 Active CN115152032B (zh)

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PCT/JP2021/034220 WO2023042359A1 (ja) 2021-09-17 2021-09-17 半導体装置

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CN115152032B true CN115152032B (zh) 2023-03-14

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US (1) US11637176B2 (https=)
JP (1) JP7114824B1 (https=)
KR (1) KR102434890B1 (https=)
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WO (1) WO2023042359A1 (https=)

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
JP7566609B2 (ja) * 2020-12-11 2024-10-15 株式会社東芝 半導体装置

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CN101645459A (zh) * 2008-08-08 2010-02-10 索尼株式会社 半导体器件及其制造方法
CN103489864A (zh) * 2012-06-13 2014-01-01 株式会社东芝 功率用半导体装置
JP2016171341A (ja) * 2016-05-26 2016-09-23 ローム株式会社 半導体装置
WO2018123799A1 (ja) * 2016-12-27 2018-07-05 パナソニックIpマネジメント株式会社 半導体装置
JP2018152504A (ja) * 2017-03-14 2018-09-27 エイブリック株式会社 半導体装置
JP2019201217A (ja) * 2014-04-15 2019-11-21 ローム株式会社 半導体装置および半導体装置の製造方法
CN111133588A (zh) * 2017-09-18 2020-05-08 株式会社电装 半导体装置及其制造方法
JP2020141130A (ja) * 2019-02-27 2020-09-03 株式会社デンソー 炭化珪素半導体装置およびその製造方法

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JP6566512B2 (ja) 2014-04-15 2019-08-28 ローム株式会社 半導体装置および半導体装置の製造方法
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JP6639365B2 (ja) 2016-09-16 2020-02-05 株式会社東芝 半導体装置
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JP2008159601A (ja) * 2005-11-28 2008-07-10 Fuji Electric Device Technology Co Ltd 半導体装置および半導体装置の製造方法
CN101645459A (zh) * 2008-08-08 2010-02-10 索尼株式会社 半导体器件及其制造方法
CN103489864A (zh) * 2012-06-13 2014-01-01 株式会社东芝 功率用半导体装置
JP2019201217A (ja) * 2014-04-15 2019-11-21 ローム株式会社 半導体装置および半導体装置の製造方法
JP2016171341A (ja) * 2016-05-26 2016-09-23 ローム株式会社 半導体装置
WO2018123799A1 (ja) * 2016-12-27 2018-07-05 パナソニックIpマネジメント株式会社 半導体装置
JP2018152504A (ja) * 2017-03-14 2018-09-27 エイブリック株式会社 半導体装置
CN111133588A (zh) * 2017-09-18 2020-05-08 株式会社电装 半导体装置及其制造方法
JP2020141130A (ja) * 2019-02-27 2020-09-03 株式会社デンソー 炭化珪素半導体装置およびその製造方法

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JPWO2023042359A1 (https=) 2023-03-23
JP7114824B1 (ja) 2022-08-08
WO2023042359A1 (ja) 2023-03-23
US11637176B2 (en) 2023-04-25
US20230101684A1 (en) 2023-03-30
KR102434890B1 (ko) 2022-08-22
CN115152032A (zh) 2022-10-04

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