CN114710253A - 多线路时偏的测量和校正方法及装置 - Google Patents
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Abstract
本发明公开多线路时偏的测量和校正方法及装置。该方法包括:接收码字序列,其中每个码字作为一组线路信号被接收;采用一组多输入比较器(MIC)为每个码字生成一组MIC输出信号,根据正交矩阵的行所表示的一组解码器系数形成一组线路信号的相互正交的组合来生成每一组MIC输出信号;在接收码字序列期间,检测一特定码字序列,并且响应地确定与特定码字序列相关联的线路特定跃迁;在特定码字序列期间,生成一组MIC输出信号中的至少一个跃迁的时偏测量结果;以及基于时偏测量结果和与特定码字序列相关联的线路特定跃迁,更新各线路的线路特定时偏值。
Description
本申请是申请号为201880056545.0,申请日为2018年7月3日,发明名称 为“多线路时偏的测量和校正方法”的专利申请的分案申请。
相关申请的交叉引用
本申请要求申请号为15/641,313,申请日为2017年7月4日,发明人为RogerUlrich,Armin Tajalli,Ali Hormati和Richard Simpson,名称为“多线路时 偏的测量和校正方法”的美国专利申请的权益,并通过引用将其内容整体并入本 文,以供所有目的之用。
参考文献
以下在先申请通过引用整体并入本文,以供所有目的之用:
公开号为2011/0268225,申请号为12/784,414,申请日为2010年5月20日, 发明人为Harm Cronie和Amin Shokrollahi,名称为“正交差分向量信令”的美国 专利申请,下称《Cronie1》;
申请号为13/842,740,申请日为2013年3月15日,发明人为Brian Holden, AminShokrollahi和Anant Singh,名称为“芯片间通信用向量信令码时偏耐受方 法和系统以及芯片间通信用向量信令码高级检测器”的美国专利申请,下称 《Holden 1》;
申请号为14/926,958,申请日为2015年10月29日,发明人为Richard Simpson,Andrew Stewart及Ali Hormati,名称为“用于向量信令码通信链路的时 钟数据对齐系统”的美国专利申请,下称《Simpson 1》;
申请号为14/717,717,申请日为2015年5月20日,发明人为Richard Simpson 和Roger Ulrich,名称为“针对向量信令码通信链路的控制回路管理及差分时延 检测和校正”的美国专利申请,下称《Simpson 2》;
申请号为14/253,584,申请日为2014年4月15日,发明人为John Fox,BrianHolden,Ali Hormati,Peter Hunt,John D Keay,Amin Shokrollahi,Anant Singh,AndrewKevin John Stewart,Giuseppe Surace和Roger Ulrich,名称为“高带宽通 信接口方法和系统”的美国专利申请,下称《Fox 1》;
申请号为14/315,306,申请日为2014年6月25日,发明人为Roger Ulrich, 名称为“高速芯片间通信用的多电平驱动器”的美国专利申请,下称《Ulrich 1》;
申请号为13/895,206,申请日为2013年5月15日,发明人为Roger Ulrich 和PeterHunt,名称为“以差和高效检测芯片间通信用向量信令码的电路”的美国 专利申请,下称《Ulrich 2》;
申请号为15/582,545,申请日为2017年4月28日,发明人为Ali Hormati 和Richard Simpson,名称为“采用判定反馈均衡的时钟数据恢复”的美国专利申 请,下称《Hormati 1》;
申请号为62/464,597,申请日为2017年2月28日,发明人为Ali Hormati 和Kiarash Gharibdoust,名称为“多线路时偏的测量和校正方法”的美国临时专利 申请;
申请号为62/509,714,申请日为2017年5月22日,发明人为Armin Tajalli 和AliHormati,名称为“多模式数据驱动型时钟恢复电路”的美国临时专利申请, 下称《Tajalli1》;
专利号为9100232,申请日为2015年8月4日,发明人为Amin Shokrollahi, AliHormati和Roger Ulrich,名称为“低符号间干扰比低功率芯片间通信方法和 装置”的美国专利,下称《Shokrollahi 1》。
技术领域
本发明实施方式总体涉及通信系统电路,尤其涉及对经芯片间通信所用高 速多线路接口传输的接收通信信号的差分信号到达时间的测量和缩减。
背景技术
在现代数字系统中,数字信号必须得到高效可靠的处理。在这一背景下, 数字信息应理解为含于离散值(即非连续值)内的信息。数字信息不但可由比 特和比特集合表示,而且还可由有限集合内的数字表示。
为了提高总带宽,大多数芯片间或装置间通信系统采用多条线路进行通信。 这些线路当中的每一条或每一对均可称为信道或链路,而且多个信道组成电子 器件之间的通信总线。在物理电路层级上,芯片间通信系统内的总线通常由芯 片与主板之间的封装电导体、印刷电路板(PCB)上的封装电导体、或PCB间 线缆和连接器内的封装电导体构成。此外,在高频应用中,还可采用微带或带 状PCB线路。
常用总线线路信号传输方法包括单端信令法和差分信令法。在需要高速通 信的应用中,这些方法还可以在功耗和引脚利用率方面(尤其高速通信中的这 些方面)被进一步优化。最近提出的向量信令方法可在芯片间通信系统的功耗、 引脚利用率及噪声稳健性方面实现更加优化的权衡取舍。此类向量信令系统将 发射器端的数字信息转换为向量码字形式这一不同表示空间,并且根据传输信 道的特性和通信系统的设计约束选择不同的向量码字,以在功耗、引脚利用率 及速度之间做出更优的权衡取舍。这一过程在本申请中称为“编码”。编码后的码 字以一组信号的形式从发射器发送至一个或多个接收器(通常以并行的方式经 多条线路或通信信道传输)。接收器将所接收的与码字对应的信号反转为最初的 数字信息表示空间。这一过程在本申请中称为“解码”。
无论采取何种编码方法,均须对接收装置所接收的信号进行间隔采样(或 者以其他方式记录其信号值),而且无论传输信道的延迟、干扰及噪声条件如何, 该采样间隔均须使得采样值能够以最佳方式表示最初的发送值。这一采样(或 称切片)操作的时间安排由相应的时钟数据对准(CDA)定时系统控制,并由 该系统确定合适的采样时间。当一组信号以基本并行的方式经多条线路或通信 信道传输时,该多条线路或信道中发生的传播延时之间的差异可导致含有该组 信号的元素(或码字字元)的接收时间彼此不同。这一现象称为“时偏”。当时偏 未得到纠正时,其可使得接收码字失去内部关联性,因此难以解码。
发明内容
为了对经通信系统发送的数据值进行可靠检测,接收器须要在精心选择的 时间点上精确测量所接收的信号值的幅度。对于基本并行传输的向量信令码而 言,上述时间选择由以下两个环节组成:对从各条线路或通信信道接收的各个 码字字元进行准确采样;无论整个接收码字的组成码元之间在接收时存在何等 差异,均能准确解读整个接收码字。
向量信令码码字内的传播时间差可由传输路径长度或传播速度差异造成, 而且既可为恒定值,也可随时间变化。这一到达时间差,即“时偏”的识别和校正 能够增大允许正确接收的时间窗口,从而提高接收信号质量。因此,接收器能 否准确测量时偏对后续的时偏校正至关重要。时偏校正的一例为在码字解码前, 在各条线路或符号数据路径中引入可变时延。
附图说明
图1所示为发送器110经信道120向接收器130发送信息的系统,所述信 道包含有具有多条线路125的多线路总线。
图2所示为用于ENRZ码的一种接收器实施方式,该ENRZ码使用从接收 数据跃迁中所获得的接收时钟。
图3所示为图2接收器所使用的时钟恢复子系统的一种实施方式。
图4为根据一些实施方式的时偏检测系统框图。
图5所示为图2接收器所用多线路总线中线路的可调节式延时元件的一种 实施方式。
图6为根据一些实施方式的可用于提供数据判定结果和早晚指示信息的例 示采样器框图。
图7为根据一些实施方式的可用于提供数据判定结果和早晚指示信息的另 一采样器框图。
图8为根据一些实施方式的代码序列检测电路框图。
图9为根据一些实施方式的用于生成线路延时调节使能信号的逻辑电路框 图。
图10为根据一些实施方式的用于对线路延时进行组合的电路框图。
图11为在眼图中心进行采样的接收器眼图。
图12为表示具体代码跃迁与线路跃迁之间关系的状态图。
图13为根据一些实施方式的方法框图。
具体实施方式
如《Cronie 1》中所述,向量信令码可用于例如在系统内的两个集成电路装 置之间形成极高带宽的数据通信链路。其中,多条数据通信信道通过分别传输 向量信令码的各个符号而共同传输该向量信令码的码字。根据所使用的具体向 量信令码的不同,组成通信链路的信道数目少至两条,多至八条或八条以上。 此外,各个符号(例如在任何单条通信信道中传输的各符号)可使用多个(通 常为三个或三个以上)信号电平。
本申请中描述的实施方式还可应用于任何需要通过多条信道或信道单元的 相互协调而生成连贯一致的总结果的通信或存储方法中。
输入采样电路
高速集成电路接收器的传统做法包括,在采样装置内完成每一数据线路的 端接(该线路之前已经过放大和频率均衡等所有相关前端处理)。其中,该采样 装置同时在时间和幅度两个维度上的约束条件下实施测量。在一种例示实施方 式中,所述采样装置由采样保持电路和下游的阈值检测器或数字比较器构成。 所述采样保持电路用于对约束测量时间间隔。所述阈值检测器或数字比较器用 于确定该测量时间间隔内的信号是否高于或低于参考值(或者,在一些实施方 式中,是否处于参考值所设定的上下限值范围内)。在另一实施方式中,所述采 样装置可类似于边沿触发式触发器,即响应时钟信号的跃迁而对输入信号的状 态进行采样。在下文中,以“采样装置”或更为精简的“采样器”两词,而非本领域中作为同义词使用但意义不太直观的等同词“切片器”表示接收器的上述输入测 量功能部件。其中,上述两词使用时,暗含同时在时间和幅度两个维度上的约 束条件下实施测量之意。
图11所示的示意性接收“眼图”分别示出了能够和不能通过上述测量产生准 确可靠检测结果(即处于采样器时间和幅度测量窗口的上下允许限值范围内) 的输入信号值。
上述采样测量中采用时钟数据对准(CDA)电路,其中,该CDA电路从上 述数据线路本身或专用的时钟输入信号中提取时间信息,并利用所提取的信息 生成对数据线路采样装置所使用的时间间隔进行控制的时钟信号。在实际应用 中,可由锁相环(PLL)或延迟锁定环(DLL)等众所周知的电路实施上述时钟 提取操作,其中,该电路在其操作过程中还可生成高频内部时钟、多个时钟相 位等物,以为接收器的操作提供支持。通常,CDA设置为在待采样信号处于稳 定状态时,即在图11中A和D表示的所谓“眼图中心”时间间隔内进行采样,以 使得采样时钟与待采样数据“对准”,从而实现采样结果的质量和准确度的优化。
系统环境
图1所示为根据一些实施方式的例示系统。如图所示,图1包括:发送器 110,该发送器接收源数据S0~S2 100和Clk 105;以及编码器112,该编码器编 码所述信息,以经线路驱动器118将该信息在包含有具有多条线路125的多线 路总线的信道120中传输。图1还包括接收器130,该接收器包括检测器132, 如有需要,在一些实施方式中还包括解码器138,以用来生成接收数据R0~R2 140 和接收时钟Rclk 145。
出于描述而非限制目的,以下各例假设了一种包含有由路径长度基本相同 且具有相同传输线路特性的四条线路彼此连接的一个发送集成电路装置和一个 接收集成电路装置的通信系统环境,信令速率为25Gb/秒/线路,相应单位传输 时间间隔为40皮秒。其中,使用《Cronie 1》中的阿达玛(Hadamard)4×4向 量信令码(该码在《Fox 1》中也称增强型NRZ(ENRZ)码),在四条线路上传 输三个数据值(如下所述,每一数据值均由所述向量信令码的一个子信道承载), 而且接收时钟从接收数据值的跃迁中获得。其他实施方式可包括经路径长度基 本相同且具有相同传输线路特性的六条线路彼此连接的一个发送集成电路装置 和一个接收集成电路装置,信令速率为25Gb/秒/线路,相应单位传输时间间隔 为40皮秒。其中,使用《Shokrollahi I》中的透翅(Glasswing)向量信令码(也 称5b6w码或和弦型NRZ(CNRZ)码),在六条线路上传输五个数据值(如下 所述,每一数据值均由所述向量信令码的一个子信道承载),而且接收时钟从接 收数据值的跃迁中获得。
为了使接收器实现足够高的信号质量,其中还假设采用有限脉冲响应滤波 以及接收器处的连续时间线性均衡、判定反馈均衡(DFE)等预先增强传输性能 的已知方法。
通信信道可例如包含有可能因印刷电路板的构成方式或迹线走线方式的差 异导致的时偏,但是处于描述目的,此类时偏的大小假设为小于一个单位时间 间隔。各时偏量校正实施方式所要解决的总体问题为如何使系统内已部分张开 的眼图实现最大程度的水平眼开度。然而,本发明不限于此,信道时偏量更大 的其他实施方式可通过《Hormati 2》中描述的训练序列和方法实现眼图的“张 开”,而时偏量远远大于上述时偏量的其他实施方式可在相应的环境中结合使用 上述时偏校正方法和其他已知时偏校正方法。
图2所示为向量信令码通信接收器的一种例示实施方式。在该框图中,来 自多线路总线的四个数据线路输入W0~W3均由延迟元件200处理,所得信号 随后进入连续时间线性均衡器(CTLE)210,以供其进行选择性放大和/或频率 补偿处理。此外,CTLE电路还通常用于提供额外的高频增益(也称高频“峰化”), 以补偿与频率相关的传输介质损耗。所得已处理的线路信号提供给多输入比较 器(MIC)220,以供其对向量信令码MIC0~MIC2的子信道进行解码。这些子 信道输出信号由采样电路230以时钟恢复(CDA)子系统300确定的时间间隔 进行采样,以产生子信道1~子信道3的数据输出。如图2所示,所述接收器可 在多个相位上操作,并且可包括用于依次输出每一相位的采样数据的多路复用 器240。在一种替代方案中,由设于CTLE 210下游和MIC 220上游的延时元件 200进行上述处理。
在一些实施方式中,部分或全部的子信道输出端还设有额外的采样器,以 促进时序的分析和/或管理。作为一例,此类额外采样器可在时钟早到或晚到时 触发,以对信号跃迁进行检测,从而优化CDA的操作。作为另一例,此类额外 采样器可设有用于促进垂直眼开度测量的可调节偏移切片电压。如《Hormati I》 中所述和图6所示,所述偏移切片电压可进一步含有用于同时提供数据信息和 时钟边沿信息的DFE校正因子。图6包括至少一个由两个数据采样器支持的推 测式DFE处理级650,所述两个数据采样器以两个不同的幅度阈值同时实施时 间采样操作。如图所示,所述数据采样器分别包括比较器620,这些比较器生成对接收自CTLE 210的信号进行切片的比较器输出,并根据采样时钟对所述比较 器输出进行采样。其中,根据最近的数据判定结果,其中一个比较器的输出选 为数据值D,而另一比较器的输出选为早晚指示信息形式的误差信号。该信号 在本申请中为信号时偏的特性信号。利用以往的数据值640,模式检测模块670 能够识别出含有跃迁的模式,并随即利用时偏测量信号(图示为早晚指示信息 E/L)判断出相应跃迁所涉及的线路,进而随即使相应特定线路的计数器递增或 递减。上述数据信号和早晚时偏测量信号的选择操作可由多路复用器630和660 完成。《Tajalli 1》中还进一步描述了如何将来自两条或更多条子信道的时钟边沿 信息相互组合,以及如何从此类组合结果中滤除来自未发生跃迁的子信道的时 偏测量信息,以在时间安排方面向CDA子系统提供更佳反馈。
图7所示为可在一些实施方式中使用的另一采样机制。如图所示,MIC0 610 的输出由CTLE 210按照上述方法处理,而CTLE 210的输出由数据采样器702 和跃迁采样器704采样。在此类实施方式中,来自CTLE 210的数据信号可在双 倍速率下采样。在至少一种实施方式中,可根据采样时钟模块706提供的采样 时钟ck_000和ck_180,对上述数据进行两次采样。在一些实施方式中,可利用 相位相差180度的时钟获得作为时偏测量信号的早晚指示信息,其中,一个时 钟对“眼图中心”进行采样(见图11),而另一个时钟对跃迁区域进行采样。作 为一种替代方案,也可在使用全速时钟的同时,将数据发送两次,从而有效地将数据速率减半。在此类实施方式中,可仅使用一个采样器,并将该采样器的 输出在数据采样操作和边沿采样操作之间交替切换。在此类实施方式中,可在 半速时偏训练时段完成后,开启或恢复全速数据传输。随后,便可利用本申请 所述的全速方法和电路进行后续测量和调节。
各线路信号到达时间之间的差异(即“时偏”)可延迟或干扰向量信令码的正 确检测时间。该时偏可因传输路径元件的长度或传播速度差异造成,而且既可 恒定不变,也可随时间变化。因此,接收器对时偏的准确测量度有助于后续的 时偏校正。时偏校正的一例为在码字解码前,在各条线路或符号数据路径中引 入可变时延。在另一例中,也可将所测量的时偏值反馈给发送器,并由发送器 实施针对具体线路的时间调节,从而使得接收器所接收的信号为已预先经过时 偏补偿的信号。
时偏调节和补偿
时偏的消除涉及使各条线路的信号在时间上渐进式偏移,以实现对到达时 间差异的补偿。某些时偏测量方法,如《Hormati II》所述方法,还在测试和分 析过程中进行交互式的线路延时调节。
在接收器处,线路延时实施方式可包括采用可变延时元件、时间可调式采 样保持元件、可调FIFO缓冲器等元件的模拟域或数字域中的现有技术方法。
《Hormati 2》中描述了一种在接收的每一线路信号中插入低插损电阻/电容 滤波处理的方法。实施该处理的电阻/电容滤波器可用于在引入较小的可调节延 时量的同时,最大程度地降低对信号幅度的影响。图5所示为一种此类延时元 件200的实施方式。虽然图中仅示出针对单条线路的可控延时电路,但是所述 多线路总线中的每条线路均可设有用于实现可调节信号时偏量的类似电路200。 其中,晶体管501,502,503可分别由时偏控制输入B0,B1,B2导通,从而将 线路输入节点的对地电容分别提升由电容器C0,C1,C2决定的量。该节点电容 的提升量与输入传输线路的源阻抗和终端阻抗共同作用,从而在线路信号中引入更大的延时量。在一种替代实施方式中,延迟元件200设置于线路信号路径 的其他位置,例如但不限于每一CTLE处理级的输出端,而非接收机的线路输 入端。
在一种具体实施方式中,当C0、C1、C2值分别为5fF、10fF、20fF时,可 实现以二进制时偏控制码字使电容以二进制方式递增,最大总电容提升量为35 飞法(FemtoFarad),相当于约5皮秒的延时增大量。在另一实施方式中,也可 使用具有相同电容值的电容器,此时相应的控制字为温度计码字,而非二进制 码字。作为电容提升的一种副作用,高频响应性能将会发生轻微下降。在上述 实施方式中,当所引入的延迟量为最大的5皮秒时,将使得12.5GHz下的回波 损耗(也常称为S11)将发生1.5dB的下降。
在用于校正更大时偏的另一实施方式中,以作为延时元件200的模拟跟踪 保持电路或模拟采样保持电路在各线路信号均保持稳定的时偏修正时刻对各线 路信号进行采样,而且对所得MIC子信道输出进行的采样操作140中使用的采 样时钟由时钟恢复电路150至少延迟至所述时偏修正时刻当中的最晚时刻。为 了增加延迟时间或降低采样信号伪影,一些实施方式可在每一线路上均设置一 系列此类采样后延时元件。
如《Ulrich 1》中所述,时偏也可通过调节各线路传输时间的方式消除。在 此类方式中,接收器将其收集的各线路相对接收时间等信息发送给发送器,从 而使得发送器能够相应地调节其线路传输时间。在一些实施方式中,通过发送 其他信息而允许对待识别和校正的包括转置和逆序在内的通信线路映射关系进 行调节。这一通信操作既可由接收器驱动,也可由另外的命令/控制处理器进行 分配。在此两情形中的每一种情形中,均可利用本文范围之外的本领域已知协 议和方法,经返回数据信道、带外命令/控制信道或其他通信信道进行通信。
接收器数据检测
如《Holden 1》中所述,通过以多输入比较器或混频器(MIC)对多组输入 信号进行线性组合的方式,可实现向量信令码的有效检测。其中,通过以三个 此类多输入比较器电路对同一组四个输入信号的各种排列组合形式进行操作, 便足以检测出所有的ENRZ码字。也就是说,如果假设一种实施如下操作的多 输入比较器:
R=(J+L)-(K+M) (式1)
其中,J、K、L、M为代表所述四个输入信号值的变量,则作为一种非限制 性的示例,根据以下各等式生成三个结果值R0、R1、R2的输入信号的排列组合 形式:
R0=(W+Y)-(X+Z) (式2)
R1=(Y+Z)-(W+X) (式3)
R2=(Y+X)-(Z+W) (式4)
足以明确无误地表示出由接收信号输入值W、X、Y、Z所代表的每一种ENRZ 码码字。其中,结果值R0、R1、R2通常称为ENRZ子信道,在本例中,每一ENRZ 子信道均由一个比特的数据调制。
如《Ulrich 2》中所述,通过将式1~式4重构为使得其均表示两个差值的和, 可以获得功能上等效的相应MIC构造。
本申请所述的各种方法和系统从总数据信号中获取早晚指示信息等时偏测 量结果,所述总数据信号为多线路总线的各线路数据信号进行线性组合而形成 的信号。所述总数据信号在本申请中称为子信道数据信号,并由一种多输入比 较器电路(MIC)220,610形成。此类MIC通过根据正交矩阵的行所表示的解 码器系数或解码器权重值进行输入信号的组合而实现上述线性组合,所述正交 矩阵例如为阿达玛矩阵或本申请所述的其他正交矩阵。由此可见,所述正交矩 阵的每一行均定义了子信道码字的码元,这些码元随后通过求和而获得正交码 字,该正交码字中的每一码元均为子信道码字的相应码元之和。根据所使用的 代码的不同(ENRZ码、CNRZ码或具有多条正交子信道的其他正交码),每一 子信道数据信号既可使用所有的线路(如ENRZ码的情形),也可使用部分线路 形成的线路子集。在一些实施方式中,部分子信道数据信号可使用所有线路, 而其他子信道数据信号仅使用部分线路形成的线路子集(如CNRZ码的情形)。
在通过对线路信号进行组合而实现子信道解码的每种MIC中,受关注的特 定子信道数据信号的线路中存在的任何信号时偏均呈现为组合子信道数据信号 本身的一定程度的时偏。对于给定的MIC子信道输出,受特定线路时偏的影响 程度取决于若干因素,这些因素至少包括相应线路发生的信号电平跃迁以及施 加于该线路信号上的相对幅度(由矩阵的子信道行决定,因此最终取决于MIC 电路的结构)。虽然MIC为电压域的线性组合器,但是当其用于提取时间信息时, 其作用相当于相位插值器。MIC子信道输出的时偏测量结果的初始形式通常为 相对于从CDR子系统接收的时钟是“过早”还是“过晚”的判定结果,并可随后转换成与跃迁所涉及的线路相对应的时偏测量信号,而且甚至可根据每一线 路的相对贡献在各条线路中分配,其中,判断线路相对贡献时的考量因素为各 条线路的电平跃迁以及MIC的相应子信道解码器系数。随后,可对多个时偏指 示信号的结果进行累计,以生成各具体线路时偏补偿值。在一些实施方式中, 可通过判断累计时偏测量信号是否超出阈值的方式,或者根据在给定时间长度 内被超出的特定阈值,生成具体线路时偏补偿值。
由于时偏测量值源于特定线路的信号电平变化量以及针对具体线路的MIC 系数,因此要么需要发送含有已知线路中已知信号电平跃迁类型的训练模式, 要么可在接收器中设置用于判断信号电平跃迁类型以及判断识别出的码字跃迁 所涉及的相应线路的码字检测电路。其中,模式检测电路670可用于判断具体 发生的跃迁类型以及识别出的相应跃迁所涉及的线路。如此,模式检测电路670 还能够判断特定线路上信号电平跃迁的幅度(根据所识别出的代码类型),并且 可相应调节计数器的递增量,以反映相应线路对时偏量的相对贡献。
在一些实施方式中,一种方法包括:在第一和第二信令时间间隔内,通过 对从多线路总线的线路中并行接收的线路信号进行线性组合而生成总数据信 号,其中,至少部分所述线路信号在所述第一和第二信令时间间隔内发生信号 电平跃迁;测量所述总数据信号的信号时偏;以及生成针对具体线路的时偏补 偿值,每一个针对具体线路的时偏补偿值均是基于所述信号时偏测量结果生成 的。也就是说,如果所述信号时偏测量结果的形式为“过早”指示信息,则可 使所述跃迁所涉及的线路的计数器递减,从而减小相应线路的时偏补偿值;如 果所述信号时偏测量结果的形式为“过晚”指示信息,则可使所述计数器递增。其中,可将最终计数值用作针对具体线路的时偏补偿值,或者将计数值超出阈 值的次数用作针对具体线路的时偏补偿值。在一些实施方式中,通过在接收器 处调节相应线路的电容性负载,所述针对具体线路的时偏补偿值可直接用作延 时调节控制信号。在其他实施方式中,也可将所述各时偏补偿值经反向信道发 送至发送器,从而使得发送器能够进行时偏预补偿。在一些实施方式中,也可 在仅当接收器的时偏校正能力达到极限时,才向发送器发送时偏补偿值。也就 是说,当接收器处的电容性负载或其他延时机制能力耗尽时,接收器可将特定 线路的时偏校正值发送至发送器。接收器可对来自发送器的已调节信号进行补偿,从而将线路时偏调回接收器能够补偿的范围。接收器既可发送具体线路时 偏控制信号具体值,也可仅发送针对具体线路的指示渐进式校正量的上调和下 调指示信息。
对于具有m个MIC(MICi,i=0,…,m-1)的实体多线路总线系统而言,在 通过对该系统的线路信号进行线性组合而确定的时偏的通用表征法中,每一 MIC可表示为:
MICi={aij,ri},j=0,...,n-1 (式5)
其中,n表示线路数目,aij表示相应解码器系数,ri表示比较参考电平(为 了简单起见,通常设置为零)。这一表达式可转换为:
其中,VMIC表示对输入信号进行线性组合的MIC电压域运算,aij为表示 MIC系数的实数,wj为与每一线路上的瞬时信号值对应的实数。其中,相对于 任意参考时间,如果每一输入线路均具有特定时偏Δtw(j),则MICi输出信号s(i) 的时偏可计算为:
其中,线路j的信号电平跃迁表示为Δwj=wj[当前]-wj[以往],并且在一些实 施方式中,-1<Δwj<+1表示对线路j上的信号wj的跃迁幅度进行的归一化运算 (如无跃迁,则wj=0)。此外,还可根据电压最大值,对电压摆幅进行归一化。 可以看出,MIC输出的时偏取决于数据模式。也就是说,随输入数据模式的不 同,该时偏可能在max(tj)和min(tj)之间变动。由于每一子信道输出的时偏取决 于具体数据,因此即使是无任何符号间干扰(ISI)的理想系统,其眼图也会因 时偏的存在而发生max(tj)-min(tj)的闭眼量。NRZ或ENRZ等线性编码/解码方 案定义的MIC不会发生随时偏变化的闭眼现象。但是,CNRZ等部分编码方案会因对确定性或随机共模(CM)噪声的敏感性而发生时偏导致MIC输出“闭 眼”的现象。
其中,假设|tj|<<T(T表示数据周期,即信令时间间隔,对应于一个单位时 间间隔),则在跃迁时刻附近,每一线路在t<<T时的信号值可近似表示为:
Wj=bj(t+tj) (式8)
根据式8和式6,在子信道输出端处的跃迁时刻可由式7近似表示。
从式7可以看出,每一MIC的作用实际上为时域内的相位插值器。也就是 说,在MIC处理级输出端处的跃迁时刻为输入信号跃迁时刻的加权插值结果。 因此,如果多线路接收器可表示为[aij,ri],则在MIC输出端处的交叉时刻可表 示为[aij bij]。如果该矩阵为可逆矩阵,可以精确计算出在接收器输入端处的时 偏。相反地,如果[aij bij]不可逆,则无法计算所述输入时偏值。此时,如仍想 实现时偏计算,必须使用其他算法。
在使用透翅码的一些实施方式中,一些发送器实施方式的时偏模式为T=[0, 0,t1,t1,t2,t2],对应线路为W=[w0,…,w5]。这一时偏模式源于发送器的结构。利 用式7,在接收器子信道输出端处的时偏可计算为:
Tsubch=[(t1+t2)/3,t1/2,0,t1/2+t2/2,t2], (式9)
从该式可以看出,子信道5的输出具有最大时偏,而在子信道2输出端处 发生跃迁的时间最早。式9计算结果与实验数据极其吻合。因此,式9可用于 计算线路(t1和t2)之间的时偏。
在一种实施方式中,一种使用透翅码的系统的时偏补偿算法可包括:
(1)根据子信道4(仅涉及线路4和线路5)的开眼情况,测量能够确定 子信道交叉点的相位插值代码(或者其他能够用于衡量子信道间时偏的信号);
(2)对其他子信道进行类似测量;
(3)按照式9计算每条线路的相应时偏。
在一些实施方式中,所述测量算法包括:测量每一接收子信道输出端处的 零交叉点。接收器包括五条子信道(五个MIC)。每一MIC的输出由与接收器 的四分之一速率架构相对应的四个切片器采样(即每一切片器以四分之一速率 运行,以对给定MIC的全速总数据信号进行轮流处理)。一些实施方式的测量过 程如下:
(1)在发送器的其中一个相位(也就是说,假设该发送器具有多个相位) 上产生一组周期性数据(如16个单位时间间隔数据,其中,8个为高电平,8 个为低电平);
(2)对所述5个MIC输出端处的交叉点进行测量,其中,每一输出由4 个切片器取样,因此产生20个独立的测量值;
(3)返回步骤1,并在发送器的另一相位上发送新的一组周期性数据。这 一流程一直重复,直至获得发送器所有四个相位的数据。
假设M0为接收器的切片器对发送器针对子信道0发送的周期性数据序列进 行测量后获得的测量结果。所接收的信号在接收MIC输出端处的交叉点可通过 以相位插值器对采样时钟进行旋转的方式测量,所述相位插值器由连接于每一 MIC的四个切片器构成。
其中,各列为接收时钟的不同相位的测量值。例如,列0为源自子信道0 切片器的四个独立测量值,而且该切片器受接收时钟相位000(0度)的控制。 与此同时,各行表示由发送器发送出的四组不同数据。例如,行0为发送相位 000产生的周期性数据。
此外,其中:
x:表示接收采样时钟的误差或时偏;
y:表示用于产生输出信号的发送时钟的误差或时偏。例如,y0表示发送时 钟相位000的定时误差。
z:表示源自相位插值器(PI)的非线性效应。
可以看出,与子信道0相应的MIC的输出端处获得的16个测量值可用于计 算(或估算)出12个独立参数。
当考虑所有子信道时,则五个MIC存在五组测量值,每组均包括16个测量 值,因此共有80个独立测量值。对测量值M0、M1、M2、M3的比较有助于线 路之间的时偏测量。在一些实施方式中,可使用最大似然法提取以下项:
(a)五个线路间时偏数值
(b)接收端的相位间时钟时偏数值
(c)发送端的相位间时钟时偏数值
(d)表示相位插值器非线性度的四个数值。需要注意的是,相位插值器的 非线性度数值仅能够在少数的几个数据点上进行测量。
ENRZ编码:在ENRZ方案的一些实施方式中,对于所有的i和j值,|aij|=0.25。 在一些实施方式中,相应电路被构造为通过选择特定模式而进行线路时偏测量, 而其他一些实施方式采用ENRZ收发器中的跃迁子集,下文中将对此进行进一 步描述。
ENRZ中线路和代码之间的关系
从上文及检测表达式2~4可知,接收子信道信号的测量以及该信息向接收 线路信号变动量的反向映射本质上难以实现。由于每一子信道与所有的四个接 收线路信号均相关,因此目前还未有能够分割、解析或以其他方式确定各线路 信号信息的公认数学方法。
代码 | 线路0 | 线路1 | 线路2 | 线路3 | R<sub>0</sub> | R<sub>1</sub> | R<sub>2</sub> |
7 | +1 | -1/3 | -1/3 | -1/3 | 1 | 1 | 1 |
1 | -1/3 | +1 | -1/3 | -1/3 | 0 | 0 | 1 |
2 | -1/3 | -1/3 | +1 | -1/3 | 0 | 1 | 0 |
4 | -1/3 | -1/3 | -1/3 | +1 | 1 | 0 | 0 |
0 | -1 | +1/3 | +1/3 | +1/3 | 0 | 0 | 0 |
6 | +1/3 | -1 | +1/3 | +1/3 | 1 | 1 | 0 |
5 | +1/3 | +1/3 | -1 | +1/3 | 1 | 0 | 0 |
3 | +1/3 | +1/3 | +1/3 | -1 | 0 | 1 | 1 |
表1
如表1所示,用于编码代码7,1,2,4的线路信号使用一个“+1”信号值 和三个“-1/3”信号值(ENRZ为均衡向量信令码,给定码字的所有信号值之和 均为零)。类似地,用于编码代码0,6,5,3的线路信号使用一个“-1”信号值 和三个“+1/3”信号值。更为重要的一点是,代码7,1,2,4或代码0,6,5, 3当中任何代码之间的跃迁仅改变两条线路上的信号。因此,举例而言,对于代 码7,1,2,4而言,如果在接收其中的任何一个代码后又接收到该组内的另一 不同代码,则此两代码之间的跃迁必然伴随着两条线路上的变化,而且发生变 化的此两条线路可根据表1确定。这一情形同样适用于从0,6,5,3这一组代 码中相继接收的两个代码。
此类已明确的双线路跃迁必然伴随接收数据“字”R0,R1,R2当中两个值的 变化。然而,这一规则本身并不足以用于判断发生变化的两条线路,这是因为, 举例而言,虽然代码7和代码1之间或者代码0和代码6之间因线路0和线路1 的变化而发生的跃迁仅使得R0,R1发生变化,但是仅R0,R1发生变化的原因也 可能在于代码2和代码4之间或代码3和代码5之间因线路2和线路3的变化 而发生的跃迁。因此,需要使用算法或电路来甄别与能够确定特定一组代码序 列的子信道跃迁相对应的线路对。本例中选用的具体线路顺序和码字值均出于 方便描述的目的,绝不构成任何限制。
跃迁时刻的确定方法
如上所述,本说明书的系统环境根据检测出的子信道数据的跃迁进行接收 器的时钟恢复。为了最大程度地获得可用于保持时钟正确对齐的信息量,通常 做法为对所有接收子信道进行监测。《Tajalli 1》描述了一种此类时钟恢复系统, 其中,先由能够感测相应子信道内发生的跃迁的各个鉴相器生成相位误差结果, 然后通过将这些相位误差结果相加而生成用于更新时钟PLL相位的总误差信 号。在一种此类实施方式中,仅将目标时间间隔内发生有效跃迁的子信道的结 果相加;在另一实施方式中,仅利用简单的二进制(Bang-Bang)相位比较器进 行加法运算,并不设置上述跃迁过滤功能,并且同时将未发生跃迁的子信道产 生的任何异常误差结果按时间均摊。此外,也可使用采用波特率(Baud)时钟 边沿检测法或双倍速率时钟边沿采样法的本领域已知实现方式。
图3所示为一些实施方式中使用的时钟恢复电路300。如图所示,该电路包 括多个部分相位比较器310,每一该部分相位比较器均接收一个相应子信道的输 出。在此类实施方式中,当相应子信道发生跃迁时,每一部分相位比较器仅输 出部分相位误差结果。每一部分相位误差信号均由求和电路320接收,以生成 复合相位误差信号。该复合相位误差信号由环路滤波器330(该滤波器可以为生 成低频误差信号的低通滤波器(LPF))滤波后,提供给压控振荡器(VCO)340。 时钟恢复电路300还可进一步包括分频器350,该分频器将VCO340的输出分 频后将所得信号提供给相位插值器360,以供其向相位比较器310提供插值后的 信号。如图所示,所述相位插值器还从时钟/数据相位控制逻辑370接收相位偏 差校正信号。该校正信号可用于补偿系统处理过程中产生的波动。VCO 340的 输出可用作多相位系统内的采样时钟,该系统的其中一个相位示于图4。
在本申请所关注的双线路跃迁情形中,除发生电路的随机波动之外,两条 子信道的结果基本上同时变化。因此,当发生此类跃迁时,两个基本上完全相 同的相位误差结果合成总误差信号。下述算法通过获得总误差信号的总体“过 早”或“过晚”状态而实现线路时偏的校正。
时偏校正算法
该算法的输入包括所接收的数据,即检测出的子信道结果R0,R1,R2。出 于说明目的,在本申请中,所述数据被称为标识“代码”,即以上结合表1所述的 具体线路/结果组合。其中,在至少两个前后相继的单位时间间隔(此处称为代 码(N)和代码(N+1))内接收的信息带有与该时间间隔相对应的时钟相位误 差形式的时偏检测值或时偏测量值,该值既可为具有正负属性的值,用于表示 所接收的跃迁早于或晚于目标时钟时间的量,或者也可为仅仅表示“过早/过晚” 的简单二进制符号。
所述信息通过如下任一方式获得:持续监测所接收的数据流(例如,通过 有限状态机);按统计学方式对数据流进行有效采样(例如,通过运行于控制或 管理处理器上的软件进程进行采样,其中,所述处理器周期性地请求并接收所 接收的数据序列以及相应的时钟相位误差信息,此类采样操作至少跨越两个前 后相继的接收单位时间间隔)。
该算法的输出为所述四个线路信号相对到达时间的动态估计结果,该估计 结果可用于即时或周期性地调节线路信号延时元件,或者用于请求或指示待由 发送器对每条线路执行的类似时间调整。在一种实施方式中,所述动态估计结 果用于即时调节接收器线路延时。在另一实施方式中,所述动态估计结果作为 变量保持于存储器中,而且在当该变量的绝对正值或负值超出预设阈值时启动 调整,从而滤除小幅波动。
以Verilog语言表示的该算法的另一实施方式见附录I。
其中的“if”语句正好与图12状态图中所示的跃迁状况一一对应,其中, 前后相继的代码7(前)和1(后)或1(前)和7(后)与线路0和线路1相 对应,代码0和6同样如此。
由于无法确定发生跃迁的两条线路中的哪条线路造成了时间上的“过早”或 “过晚”,因此其中同时将两条线路的代表时偏偏移量度值的变量按同一方式更 新。如此,举例而言,如果与代码0和5对应的后续跃迁也将线路0和线路2 朝同一方向更新,则说明两个测量值共同涉及的线路0可能为所述时间误差的 来源。因此,通过以该算法对若干不同采样结果进行处理,可以实现对各线路 时间误差的合理估计。如上所述,在至少一种实施方式中,通过在累计时间误 差值导致实际发生时间改动之前引入绝对幅度阈值,能够减少因测量伪影发生 的随机时间调整。在其他实施方式中,出于即使在相反方向上引入较小的调节量,也不会导致较大的误差,而且持续进行同一方向的调节实际上能够实现开 眼度的优化这一假设,线路时间采用即时调节方案。
图4为可用于执行上述时偏检测算法的接收器框图。如图4所示,该接收 器包括如上所述用于接收各线路中的信号并随之生成代表子信道输出R0~R2的 总数据信号的MIC220。采样器通过对子信道的输出进行采样430而提供各子信 道数据输出D0~D2以及各子信道的早晚指示信号E/L0~2。在一些实施方式中,采 样器430可采取上述图6或图7所示采样器的形式。图4包括用于检测各组依 次接收的有效比特(每一组均表示上述代码0~7)的代码序列检测模块440。这 些序列如图12状态图所示。在一些实施方式中,代码序列检测模块440可提供 DFE功能,以例如供采用图6所示采样器的实施方式中的采样器430使用。
图8为根据一些实施方式的代码序列检测模块框图。在一些实施方式中, 所述代码序列检测模块可通过D触发器805和810实现,其中,该D触发器由 延迟815后的采样时钟采样,以为缓冲操作创造时间。逻辑电路820通过对当 前检测到的比特b0~b2和之前检测到的比特prev_b0~b2进行分析而判断所检测 的代码序列是否为有效序列。当所检测的代码序列为有效序列时,将向图4所 示的总线路延时模块460提供线路延时调节使能信号w0~w3_enable。如上所述, 在H4代码实施方式中,逻辑电路820检测出的任何有效代码序列均涉及两条线 路。在此类实施方式中,其中仅两个线路延时调节使能信号w0~w3_enable为“1”, 而剩余两个为“0”(因此不会导致总线路延时模块460中的延时值更新)。
在替代方案中,在仅涉及两条线路的序列的基础上或其之外,也可使用其 他序列。举例而言,代码序列检测电路670可用于识别每一线路发生正负倒置 但仍维持原有幅值的跃迁,如[-1,1/3,1/3,1/3]至[1,-1/3,-1/3,-1/3]的码字跃迁或 [-1/3,1,-1/3,-1/3]至[1/3,-1,1/3,1/3]的码字跃迁等。该组跃迁包括8组码字序列。 在此类跃迁中,通过审视特定线路的跃迁幅度而相应更新时偏度量值。具体而 言,对于[-1,1/3,1/3,1/3]至[1,-1/3,-1/3,-1/3]这一码字跃迁,可按照以下跃迁幅 度计算式对MIC输出端处的时偏监测值或测量值进行加权:|((线路(代码1,i)- 线路(代码2,i)×MIC(线路(i))|(在该情形中,即[2,2/3,2/3,2/3])。可以看出,线 路W0的时偏对所监测的MIC输出时偏的影响为其他线路时偏影响的三倍。根 据识别出的跃迁幅度,可以对计数器进行渐进式调节,以使其正确反映每条线 路的相对时偏贡献。
图9为根据一些实施方式的逻辑电路820的框图。图9示例所示为从表1 代码“1”跃迁为代码“7”的有效代码序列。这一逻辑电路可实施为与(AND) 门905,其中,当比特b0~b2对应于代码“1”=“001”并且前一组所接收到的 比特prev_b0-b2对应于代码“7”=“111”时,与门905的输出为高电平。控制 电路910可对所有此类检测逻辑门的输出进行分析,并可向总线路延时模块460 输出线路延时调节使能信号w0~w3_enable。该使能信号表示应该对哪一计数器 进行调节(根据所述信号的时偏特性信号,既可以为递增,也可以为递减)。另 外,还可根据线路信号电平跃迁的相对幅度,按照本申请所述方式对计数递增 变量进行加权。在一些实施例中,控制电路910可采用执行下表2的控制逻辑:
表2
图4还包括矩阵误差组合器450,该矩阵误差组合器用于从所述多条子信道 接收早晚指示信号E/L0~2,并在生成最终早晚判定结果后将其提供给总线路延时 模块460,以供其相应地使预存延时值递增或递减。如上文和表1所示,在一些 实施方式中,由于任何给定的有效代码序列仅有两条子信道R0~R2发生变化, 因此不发生变化的子信道产生的E/L信号为无用指示信息,所以可以引入相应 的逻辑,以忽略此类无用指示信息的作用。虽然如此,由于发生变化的所述两 条子信道均提供指示过早或过晚的早晚指示信息,因此此两早晚指示信息的组 合将盖过未发生跃迁的子信道的早晚指示信息,因此即使不引入所述逻辑,矩 阵误差组合器450所提供的最终早晚指示信息仍为有效信息。
图10为根据一些实施方式的总线路延时模块460的例示框图。如图所示, 总线路延时模块包括四个模块1005,1010,1015,1020。每一模块均针对多线 路总线的其中一条线路。在一些实施方式中,每一模块对应于可根据接收的线 路延时调节使能信号w0~w3_enable相应启动的计数器。此外,每一计数器可用 于从矩阵误差组合器450接收早晚指示信号,该信号可用作控制相应计数器上 调或下调(U/D)的依据。每一计数器均可根据延迟470后的采样时钟进行递变。 在一些实施方式中,例如如图5所示,每一计数器内的存储值均可提供给(例 如作为二进制比特)相应的线路延时调节电路。
图13为根据一些实施方式的方法1300的流程图。如图所示,方法1300包 括:获得前后相继接收的数据值1302。根据对所述接收数据值的分析,相应数 据是否对应于一组单对线路跃迁1304。如果判断结果为“否”,则返回方法的开 始步骤,以获得下一组接收数据;如果判断结果为“是”,则例如通过以上结合 表2所述的控制逻辑910,识别出与所述代码跃迁对应的线路1306。在识别出 所述线路后,根据所接收的早晚信息,更新表示总延时值的动态线路计数值 1308。当所述动态误差计数值达到动作阈值时1310,根据存储的误差计数值, 调节线路延时1312。
附录I
Claims (15)
1.一种方法,其特征在于,包括:
接收码字序列,其中每一个码字均作为多线路总线的相应一组线路信号被接收;
采用一组多输入比较器为所接收的所述码字序列中的每一个码字生成一组多输入比较器输出信号,其中,根据正交矩阵的行所表示的相应一组解码器系数形成所述一组线路信号的相互正交的组合来生成每一组所述多输入比较器输出信号;
在接收所述码字序列的期间,检测一特定码字序列,并且响应地确定与所述特定码字序列相关联的线路特定跃迁;
在所述特定码字序列期间,生成所述一组多输入比较器输出信号中的至少一个跃迁的时偏测量结果;以及
基于所述时偏测量结果和与所述特定码字序列相关联的线路特定跃迁,更新所述多线路总线中各线路的线路特定时偏值。
2.根据权利要求1所述的方法,其特征在于,生成所述一组多输入比较器输出信号中的至少一个跃迁的时偏测量结果包括生成所述跃迁的边沿采样结果,以及基于先前数据采样结果生成早晚相位误差指示信息。
3.根据权利要求1所述的方法,其特征在于,生成所述一组多输入比较器输出信号中的至少一个跃迁的时偏测量结果包括生成发生跃迁的给定多输入比较器输出信号的一对采样结果,所述一对采样结果在采样时刻根据相应的推测判定反馈均衡因子同时生成,并且根据先前数据采样结果,选择所述一对采样结果中的一个作为数据判定结果,另一个作为早晚相位误差指示信息。
4.根据权利要求1所述的方法,其特征在于,每个线路特定时偏值由相应的加权时偏测量结果更新,每个加权时偏测量结果通过根据特定码字序列期间的线路特定跃迁对时偏测量结果加权而生成。
5.根据权利要求4所述的方法,其特征在于,所述线路特定时偏值存储于计数器中,对时偏测量结果加权包括使所述计数器递增或递减由线路特定跃迁确定的量。
6.根据权利要求1所述的方法,其特征在于,更新所述多线路总线中各线路的线路特定时偏值包括将多线路总线的每一条线路的线路特定时偏控制信号传送至发射器。
7.根据权利要求1所述的方法,其特征在于,所述正交矩阵是大小为4的阿达玛矩阵。
8.根据权利要求1所述的方法,其特征在于,在所述特定码字序列期间有至少两个多输入比较器输出信号跃迁,所述方法还包括对所述至少两个多输入比较器输出信号生成的时偏测量结果进行组合。
9.一种装置,其特征在于,包括:
多个多输入比较器,用于接收码字序列,其中每一个码字均作为多线路总线的相应一组线路信号被接收,所述多个多输入比较器用于为所接收的所述码字序列中的每一个码字生成一组多输入比较器输出信号,其中,根据正交矩阵的行所表示的相应一组解码器系数形成所述一组线路信号的相互正交的组合来生成每一组所述多输入比较器输出信号;
码字序列检测电路,用于在接收所述码字序列的期间,检测一特定码字序列,并且响应地确定与所述特定码字序列相关联的线路特定跃迁;
采样电路,用于在所述特定码字序列期间,生成所述一组多输入比较器输出信号中的至少一个跃迁的时偏测量结果;以及
时偏校正电路,用于基于所述时偏测量结果和与所述特定码字序列相关联的线路特定跃迁,更新所述多线路总线中各线路的线路特定时偏值。
10.根据权利要求9所述的装置,其特征在于,所述采样电路包括:用于生成所述跃迁的边沿采样结果的边沿采样器,用于生成先前数据采样结果的数据采样器,以及比较器,所述比较器用于比较边沿采样结果和先前数据采样结果以生成时偏测量结果作为早晚相位误差指示信息。
11.根据权利要求9所述的装置,其特征在于,所述采样电路包括:
一对比较器,用于生成发生跃迁的给定多输入比较器输出信号的一对采样结果,所述一对采样结果在采样时刻根据相应的推测判定反馈均衡因子同时生成;以及
选择电路,用于根据先前数据采样结果,选择所述一对采样结果中的一个作为数据判定结果,另一个作为早晚相位误差指示信息。
12.根据权利要求9所述的装置,其特征在于,每个线路特定时偏值由相应的加权时偏测量结果更新,所述时偏校正电路用于根据特定码字序列期间的线路特定跃迁对时偏测量结果进行加权来生成每个加权时偏测量结果。
13.根据权利要求12所述的装置,其特征在于,所述时偏校正电路用于将所述线路特定时偏值存储于计数器中,所述时偏校正电路通过使所述计数器递增或递减由线路特定跃迁确定的量来对时偏测量结果进行加权。
14.根据权利要求9所述的装置,其特征在于,所述时偏校正电路用于将多线路总线的每一条线路的线路特定时偏控制信号传送至发射器。
15.根据权利要求9所述的装置,其特征在于,在所述特定码字序列期间有至少两个多输入比较器输出信号跃迁,所述装置还包括矩阵误差组合器,用于对所述至少两个多输入比较器输出信号生成的时偏测量结果进行组合。
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