CN114678416A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN114678416A
CN114678416A CN202210319629.7A CN202210319629A CN114678416A CN 114678416 A CN114678416 A CN 114678416A CN 202210319629 A CN202210319629 A CN 202210319629A CN 114678416 A CN114678416 A CN 114678416A
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China
Prior art keywords
region
insulating film
gate
impurity region
gate stack
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CN202210319629.7A
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English (en)
Inventor
郑会晟
姜太星
申东石
李公洙
李准原
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN114678416A publication Critical patent/CN114678416A/zh
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Abstract

提供了一种半导体装置。所述半导体装置包括：基底，包括形成有单元区域的第一区域和形成有核心‑外围区域的第二区域；栅极堆叠件，位于基底的第二区域上，栅极堆叠件包括包含氧化物的第一栅极绝缘膜、位于第一栅极绝缘膜上的包括铪的第二栅极绝缘膜、位于第二栅极绝缘膜上的包括镧和氮化钛的第一电极、位于第一电极上的第二电极；栅极堆叠绝缘膜，接触栅极堆叠件的侧表面和顶表面；杂质区域，具有设置在基底的第二区域中位于栅极堆叠件的至少一侧上的堆垛层错；氮化硅膜，覆盖杂质区域的上表面，氮化硅膜与栅极堆叠绝缘膜接触；以及接触件，穿过氮化硅膜延伸至杂质区域。

Description

半导体装置
本申请是申请日为2019年3月7日、申请号为201910171174.7、题为“制造半导体装置的方法”的专利申请的分案申请。
技术领域
本公开总体上涉及电子学领域，更具体地，涉及一种制造半导体装置的方法。
背景技术
集成电路装置可以在其中包括数百万或数十亿个晶体管。晶体管可以作为开关操作以允许电荷载流子(例如，电子)在导通时流动并且防止电荷载流子在截止时流动。晶体管的性能会受电荷载流子迁移率的影响。电荷载流子迁移率是表示电荷载流子随着电场的存在而移动的速度的标准。如果电荷载流子迁移率增大，则可以为晶体管的较高开关速度提供固定电压，或者可以对相同的开关速度施加较低的电压。
发明内容
根据本发明构思的一些实施例的制造半导体装置的方法可以通过对位于存储器装置(例如，动态随机存取存储器(DRAM))的核心-外围区域中的晶体管应用应力记忆技术(SMT)来增强性能。
根据本发明构思的一些实施例的制造半导体装置的方法可以通过由于在去除栅极间隔件之后执行额外的离子注入工艺减小沟道区的宽度来增强性能。
根据本发明构思的一些实施例，制造半导体装置的方法可以包括：在基底的核心-外围区域上形成栅极结构。基底还可以包括单元区域。所述方法还可以包括在栅极结构的侧壁上形成栅极间隔件；通过执行第一离子注入工艺在基底的核心-外围区域中形成与栅极间隔件相邻的第一杂质区域；去除栅极间隔件；通过执行第二离子注入工艺在基底的核心-外围区域中并且在栅极结构和第一杂质区域之间形成第二杂质区域；在栅极结构、第一杂质区域的上表面和第二杂质区域的上表面上形成应力膜；通过由于执行退火工艺使第一杂质区域和第二杂质区域结晶来形成再结晶区域。
根据本发明构思的一些实施例，制造半导体装置的方法可以包括在基底的核心-外围区域上形成栅极结构。基底还可以包括单元区域。所述方法还可以包括在栅极结构的相对侧壁上形成栅极间隔件；通过执行第一离子注入工艺在基底的核心-外围区域中形成第一杂质区域。每个第一杂质区域可以相邻于栅极间隔件中的相应的栅极间隔件，第一杂质区域可以限定位于基底的核心-外围区域中且位于第一杂质区域之间的第一沟道区，第一沟道区可以具有第一宽度。方法还可以包括：去除栅极间隔件；通过执行第二离子注入工艺在基底的核心-外围区域中形成第二杂质区域；在栅极结构、第一杂质区域的上表面和第二杂质区域的上表面上形成应力膜；通过由于执行退火工艺使第一杂质区域和第二杂质区域结晶来形成再结晶区域。每个第二杂质区域可以相邻于栅极结构的相对侧壁中的相应侧壁，第二杂质区域可以限定位于基底的核心-外围区域中且位于第二杂质区域之间的第二沟道区，第二沟道区可以具有比第一宽度窄的第二宽度。
根据本发明构思的一些实施例，制造半导体装置的方法可以包括：在基底的核心-外围区域上形成第一栅极结构和第二栅极结构。第一栅极结构和第二栅极结构可以在第一方向上彼此间隔开，基底还可以包括单元区域。所述方法还可以包括：在第一栅极结构的侧壁上形成第一栅极间隔件，并且在第二栅极结构的侧壁上形成第二栅极间隔件；通过执行第一离子注入工艺在基底的核心-外围区域中并且在第一栅极间隔件和第二栅极间隔件之间形成第一杂质区域；去除第一栅极间隔件和第二栅极间隔件；通过执行第二离子注入工艺在基底的核心-外围区域的第一部分和第二部分中形成第二杂质区域。基底的核心-外围区域的第一部分位于第一栅极结构和第一杂质区域之间，基底的核心-外围区域的第二部分位于第二栅极结构和第一杂质区域之间。所述方法还可以包括在第一栅极结构、第二栅极结构、第一杂质区域的上表面和第二杂质区域的上表面上形成应力膜；通过由于执行退火工艺使第一杂质区域和第二杂质区域结晶来形成再结晶区域。
本发明构思旨在解决的目的不限于上述目的，并且基于下面提供的描述，本领域技术人员可以清楚地理解上面未提及的其它目的。
附图说明
通过参照附图详细地描述本发明构思的示例实施例，对于本领域技术人员来说，本发明构思的以上和其它对象、特征和优点将变得更加清楚，在附图中：
图1是通过根据本发明构思的一些实施例的方法制造的半导体装置的布图；
图2是沿图1的线A-A和B-B截取的剖视图；
图3至图13是示出根据本发明构思的一些实施例的制造半导体装置的方法的剖视图；
图14是示出根据本发明构思的一些实施例的制造半导体装置的方法的剖视图；
图15至图17是示出根据本发明构思的一些实施例的制造半导体装置的方法的剖视图；
图18和图19是示出根据本发明构思的一些实施例的制造半导体装置的方法的剖视图。
具体实施方式
在下文中，参照图1和图2，将描述通过根据本发明构思的一些实施例的方法制造的半导体装置。
图1是通过根据本发明构思的一些实施例的方法制造的半导体装置的布图。图2是沿图1的线A-A和B-B截取的剖视图。
参照图1和图2，通过根据一些实施例的方法制造的半导体装置包括单元区域和核心-外围区域。在一些实施例中，核心-外围区域可以位于单元区域的边缘，如图1中所示。
本发明构思涉及一种存储器元件，存储器元件包括DRAM装置、闪存装置和PRAM装置中的任何一种。在一个实施例中，例如DRAM装置、闪存装置和PRAM装置的存储器元件可以位于单元区域上。在下文中，将描述DRAM作为示例。然而，本发明构思不限于此。
基底100包括形成有单元区域的第一区域R1，以及形成有核心-外围区域的第二区域R2。
基底100可以是基体基底和外延层彼此堆叠的结构，但是本发明构思不限于此。在一些实施例中，基底100可以是硅基底、砷化镓基底、硅锗基底、陶瓷基底、石英基底、用于显示的玻璃基底以及绝缘体上半导体(SOI)基底中的任何一种。在下文中，将描述硅基底作为示例。基底100可以具有第一导电类型(例如，P型导电性)，但是本发明构思不限于此。
单元区域包括单元有效区域10、元件隔离区域11、沟槽20、栅电极21、覆盖图案22、栅极绝缘膜23、第一源区/漏区30a、第二源区/漏区30b、层间绝缘膜40、第一接触插塞50、位线60和第二接触插塞70。
位线60和用作字线的栅电极21可以布置在基底100上。具体地，单元有效区域10和元件隔离区域11可以形成在基底100上。在这种情况下，两个晶体管可以形成在单个单元有效区域10中。
两个晶体管可以包括形成为与单元有效区域10交叉的两个栅电极21、形成在单元有效区域10中且在两个栅电极21之间的第一源区/漏区30a以及形成在栅电极21和元件隔离区域11之间的第二源区/漏区30b。在一些实施例中，两个晶体管共用第一源区/漏区30a并且不共用第二源区/漏区30b，如图2中所示。
在一些实施例中，栅极绝缘膜23可以沿形成在基底100中的沟槽20的侧壁和底表面形成。栅极绝缘膜23可以包括例如氧化硅或具有比氧化硅高的介电常数的高k介电材料。
在一些实施例中，栅电极21可以不完全填充沟槽20并且可以填充沟槽20的一部分(例如，下部分)。也就是说，栅电极21可以呈凹陷的形状。
栅电极21可以通过使用例如掺杂的多晶硅、氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、钛(Ti)、钽(Ta)和钨(W)中的任何一种来形成，但是本发明构思不限于此。
覆盖图案22可以形成在栅电极21上以填充在沟槽20中(例如，沟槽20的上部分)。覆盖图案22可以包括绝缘材料，并且例如可以包括氧化硅、氮化硅和氮氧化硅中的至少一种。
层间绝缘膜40可以形成在基底100上。层间绝缘膜40可以包括例如氧化硅、氮化硅和氮氧化硅中的至少一种。层间绝缘膜40可以是单层或多层。
第一接触插塞50可以形成在层间绝缘膜40中，以与第一源区/漏区30a电连接。第一接触插塞50可以包括导电材料，并且例如可以包括多晶硅、金属硅化物、导电金属氮化物和金属中的至少一种，但是本发明构思不限于此。
位线60可以形成在第一接触插塞50上，以与第一接触插塞50电连接。位线60可以包括导电材料，并且例如可以包括多晶硅、金属硅化物、导电金属氮化物和金属中的至少一种。然而，本发明构思不限于此。
第二接触插塞70可以形成在层间绝缘膜40中，以延伸穿过层间绝缘膜40。第二接触插塞70可以与第二源区/漏区30b电连接。第二接触插塞70可以包括存储节点接触件。
第二接触插塞70可以包括导电材料，并且例如可以包括多晶硅、金属硅化物、导电金属氮化物和金属中的至少一种。然而，本发明构思不限于此。
第二接触插塞70可以与形成在第二接触插塞70上的下电极(例如，电容器的电极)电连接，并且具有圆柱形或柱形形状。
核心-外围区域包括第一栅极结构1100、第二栅极结构1200、再结晶区域500、蚀刻停止膜600、层间绝缘膜700、接触件710和沟道区920。
第一栅极结构1100可以形成为在第二方向Y上延伸。在一些实施例中，第一栅极结构1100可以在第二方向Y上纵向地延伸。第一栅极结构1100可以包括栅极绝缘膜1001、第一导电膜1002、第二导电膜1003、第三导电膜1004、覆盖膜1005和第一栅极堆叠绝缘膜1111。
栅极绝缘膜1001、第一导电膜1002、第二导电膜1003、第三导电膜1004和覆盖膜1005可以顺序地堆叠在基底100的沟道区920上并且可以在第二方向Y上延伸。
具体地，栅极绝缘膜1001可以形成在基底100的沟道区920上。栅极绝缘膜1001可以包括例如氧化硅，但是本发明构思不限于此。
第一导电膜1002可以形成在栅极绝缘膜1001上。第一导电膜1002可以包括例如多晶硅，但是本发明构思不限于此。
第二导电膜1003可以形成在第一导电膜1002上。第二导电膜1003可以包括例如TiSiN，但是本发明构思不限于此。
第三导电膜1004可以形成在第二导电膜1003上。第三导电膜1004可以包括例如钨(W)，但是本发明构思不限于此。
覆盖膜1005可以形成在第三导电膜1004上。覆盖膜1005可以包括例如氮化硅，但是本发明构思不限于此。
在一些实施例中，第一栅极堆叠绝缘膜1111可以共形地形成为覆盖栅极堆叠件的上表面和侧壁，栅极堆叠件包括栅极绝缘膜1001、第一导电膜1002、第二导电膜1003、第三导电膜1004和覆盖膜1005，如图2中所示。将理解的是，“A层共形地形成为覆盖B”意味着“A层形成为沿B的表面具有均匀的厚度”。此外，将理解的是，“A层覆盖B层”意味着“A层部分地或完全地覆盖B层”。
第一栅极堆叠绝缘膜1111可以包括例如氮化硅，但是本发明构思不限于此。
在一些实施例中，高k介电膜和/或至少一个功函数调整膜可以形成在栅极绝缘膜1001和第一导电膜1002之间。
高k介电膜可以包括例如氧化铪(HfO)、硅酸铪(HfSiO)、氮氧化铪(HfON)、氮氧化铪硅(HfSiON)、氧化镧(LaO)、氧化镧铝(LaAlO)、氧化锆(ZrO)、硅酸锆(ZrSiO)、氧氮化锆(ZrON)、氧氮化锆硅(ZrSiON)、氧化钽(TaO)、氧化钛(TiO)、氧化钡锶钛(BaSrTiO)、氧化钡钛(BaTiO)、氧化锶钛(SrTiO)、氧化钇(YO)、氧化铝(AlO)、氧化铅钪钽(PbScTaO)或其组合，但本发明构思不限于此。
至少一个功函数调整膜可以包括例如钨(W)、钽(Ta)、铝(Al)、钌(Ru)、铂(Pt)、氮化钛(TiN)、氮化钽(TaN)、碳化钛(TiC)、碳化钽(TaC)、Al2O3/TiN、Al2O3/TaN、Al/TiN、Al/TaN、TiN/Al/TiN、TaN/Al/TaN、TiN/TiON、TaN/TiON、Ta/TiN、TaN/TiN、Mg/TiN、TiN/Mg/TiN、La/TiN、TiN/La/TiN、Sr/TiN、TiN/Sr/TiN或它们的组合，但本发明构思不限于此。
第二栅极结构1200可以形成为与第一栅极结构1100在第一方向X上间隔开并且可以在第二方向Y上延伸。第二栅极结构1200可以包括栅极绝缘膜1001、第一导电膜1002、第二导电膜1003、第三导电膜1004、覆盖膜1005和第二栅极堆叠绝缘膜1121。
第二栅极结构1200可以具有与第一栅极结构1100基本相同的结构。也就是说，第二栅极结构1200可以包括栅极堆叠件以及共形地形成为覆盖栅极堆叠件的上表面和侧壁的第二栅极堆叠绝缘膜1121，在栅极堆叠件中，栅极绝缘膜1001、第一导电膜1002、第二导电膜1003、第三导电膜1004和覆盖膜1005顺序地堆叠在基底100的沟道区920上。
然而，在一些实施例中，第二栅极结构1200可以具有与第一栅极结构1100不同的结构。
再结晶区域500可以形成在基底100中并在第一栅极结构1100的两侧上以及在第二栅极结构1200的两侧上。再结晶区域500可以在形成时为非晶区域，然后可以通过退火工艺使再结晶区域500再结晶。退火工艺可以使基底100的通过离子注入工艺变为非晶的部分(例如，下面讨论的第一杂质区域200和第二杂质区域300)结晶。
沟道区920可以形成在第一栅极结构1100的下部分的下方并且在第二栅极结构1200的下部分的下方。沟道区920可以形成在基底100中并且在再结晶区域500之间。
再结晶区域500可以包括沿(111)晶面形成的堆垛层错510。例如，堆垛层错510的堆垛层错面为(111)晶面。在一个实施例中，堆垛层错510可以从再结晶区域500的与第一栅极结构1100相邻的下表面500a延伸，以相对于再结晶区域500的下表面500a具有锐角θ，如图2中所示。
在一些实施例中，再结晶区域可以包括从再结晶区域的与栅极结构相邻的下部分延伸的堆垛层错，如图2中所示。堆垛层错可以相对于再结晶区域的下表面形成锐角。
堆垛层错510可以使再结晶区域500的晶格变形并且可以影响耦合长度。例如，堆垛层错510可以通过由于使再结晶区域500的晶格变形造成拉应力，来减小原子间耦合长度。
通过在形成堆垛层错510的过程中在沟道区920中感应应力来减小沟道区920的原子间距，可以增大沟道区920中的电荷载流子迁移率。在下面将对其进行更详细地描述。
蚀刻停止膜600可以形成为覆盖第一栅极结构1100、第二栅极结构1200以及再结晶区域500的上表面。
蚀刻停止膜600可以包括例如氮化硅(SiN)、氮氧化硅(SiON)、碳氮化硅(SiCN)、氧碳氮化硅(SiOCN)、氧碳化硅(SiOC)和低k介电材料中的至少一种，但本发明构思不限于此。
层间绝缘膜700可以形成为覆盖蚀刻停止膜600。接触件710可以形成在再结晶区域500上，以贯穿层间绝缘膜700和蚀刻停止膜600。接触件710的一部分可以形成为埋入再结晶区域500的上部分中，如图2中所示。
接触件710可以是形成为在第三方向Z上延伸的直接接触插塞(DCCP)。接触件710可以包括例如钨(W)，但本发明构思不限于此。
以下，将参照图3至图13描述根据一些实施例的制造半导体装置的方法。
图3至图13是示出根据本发明构思的一些实施例的制造半导体装置的方法的剖视图。
参照图3，可以在基底100的形成核心-外围区域的第二区域R2上形成堆叠结构1010。
具体地，堆叠结构1010可以包括顺序地堆叠在基底100的第二区域R2上的栅极绝缘膜1001、第一导电膜1002、第二导电膜1003、包括钨(W)的第三导电膜1004以及覆盖膜1005。
参照图4，可以通过利用掩模对堆叠结构1010进行蚀刻，来在基底100上形成第一栅极堆叠件1110和第二栅极堆叠件1120。
第一栅极堆叠件1110和第二栅极堆叠件1120中的每个可以包括顺序地堆叠在基底100上的栅极绝缘膜1001、第一导电膜1002、第二导电膜1003、包括钨(W)的第三导电膜1004以及覆盖膜1005。
第一栅极堆叠件1110和第二栅极堆叠件1120可以在第一方向X上彼此间隔开，第一栅极堆叠件1110和第二栅极堆叠件1120中的每个可以形成为在第二方向Y上延伸。在一些实施例中，第一栅极堆叠件1110和第二栅极堆叠件1120中的每个可以在第二方向Y上纵向地延伸。
参照图5，可以形成第一栅极堆叠绝缘膜1111以覆盖第一栅极堆叠件1110的上表面和侧壁，可以形成第二栅极堆叠绝缘膜1121以覆盖第二栅极堆叠件1120的上表面和侧壁。
第一栅极堆叠绝缘膜1111和第二栅极堆叠绝缘膜1121可以包括例如氮化硅，但本发明构思不限于此。
接下来，可以沿包括第一栅极堆叠件1110和第一栅极堆叠绝缘膜1111的第一栅极结构1100的侧壁形成第一栅极间隔件1150。另外，可以沿包括第二栅极堆叠件1120和第二栅极堆叠绝缘膜1121的第二栅极结构1200的侧壁形成第二栅极间隔件1250。
第一栅极间隔件1150和第二栅极间隔件1250可以包括例如氧化硅，但本发明构思不限于此。
参照图6，可以通过执行第一离子注入工艺I1来在基底100的暴露的部分中形成作为非晶区域的第一杂质区域200。在一些实施例中，基底100的形成有第一杂质区域200的部分可以通过第一离子注入工艺I1变为非晶的。
在一些实施例中，第一栅极结构1100、第一栅极间隔件1150、第二栅极结构1200和第二栅极间隔件1250可以在第一离子注入工艺I1期间被用作离子注入掩模，因此，离子可以被注入到基底100的被第一栅极结构1100、第一栅极间隔件1150、第二栅极结构1200和第二栅极间隔件1250暴露的部分中，如图6中所示。
具体地，通过对其上没有形成第一栅极结构1100、第一栅极间隔件1150、第二栅极结构1200和第二栅极间隔件1250的基底执行第一离子注入工艺I1，可以在基底100中形成第一杂质区域200。也就是说，在一些实施例中，第一杂质区域200可以分别形成在第一栅极间隔件1150的两侧上并且在第二栅极间隔件1250的两侧上，如图6中所示。
第一杂质区域200的上表面200b可以与第一栅极结构1100的下表面1100a以及第一栅极间隔件1150的下表面1150a共面。然而，本发明构思不限于此。
在第一方向X上具有第一宽度W1的第一沟道区910可以形成在基底100的位于第一栅极结构1100下方且位于第一杂质区域200之间的部分中。另外，在第一方向X上具有第一宽度W1的第一沟道区910可以形成在基底100的位于第二栅极结构1200下方且位于第一杂质区域200之间的部分中。
在一些实施例中，轻掺杂漏(LDD)注入工艺和源/漏(S/D)注入工艺可以应用到第一离子注入工艺I1，但本发明构思不限于此。
参照图7，可以去除第一栅极间隔件1150和第二栅极间隔件1250。
例如，可以利用包括HF的蚀刻剂对第一栅极间隔件1150和第二栅极间隔件1250进行湿法蚀刻。然而，本发明构思不限于此。
参照图8，可以通过执行第二离子注入工艺I2在基底100中并且在第一栅极结构1100和第一杂质区域200之间以及在第二栅极结构1200和第一杂质区域200之间形成作为非晶区域的第二杂质区域300。在一些实施例中，基底100的形成有第二杂质区域300的部分可以通过第二离子注入工艺I2变为非晶的。
第二杂质区域300的上表面300b可以与第一杂质区域200的上表面200b共面。
在一些实施例中，第一栅极结构1100和第二栅极结构1200可以在第二离子注入工艺I2期间被用作离子注入掩模，因此，离子可以被注入到基底100的被第一栅极结构1100和第二栅极结构1200暴露的部分中，如图8中所示。
在一些实施例中，如图8中所示，第二杂质区域300中的与第一栅极结构1100相邻的一个第二杂质区域300可以形成在基底100的与图6中所示的第一栅极间隔件1150叠置的部分中，第二杂质区域300中的与第二栅极结构1200相邻的一个第二杂质区域300可以形成在基底的与图6中所示的第二栅极间隔件1250叠置的部分中。
在一些实施例中，第二杂质区域300的上表面300b可以是在去除第一栅极间隔件1150之前与图6中所示的第一栅极间隔件1150的下表面1150a的至少一部分叠置的基底100的上表面。另外，第二杂质区域300的上表面300b可以是在去除第二栅极间隔件1250之前与图6中所示的第二栅极间隔件1250的下表面1150a的至少一部分叠置的基底100的上表面。
可以通过调节第二离子注入工艺I2的工艺参数来调节第二杂质区域300的深度。第二杂质区域300可以形成为例如距第二杂质区域300的上表面300b具有大约10纳米至大约60纳米的深度。然而，本发明构思不限于此。
从第一杂质区域200的上表面200b至第一杂质区域200的下表面200a的第一深度h1可以与从第二杂质区域300的上表面300b至第二杂质区域300的下表面300a的第二深度h2基本相同。然而，本发明构思不限于此。
在第一方向X上具有第二宽度W2的第二沟道区920可以形成在基底100的位于第一栅极结构1100下方并且在第二杂质区域300之间的部分中。另外，在第一方向X上具有第二宽度W2的第二沟道区920可以形成在基底100的位于第二栅极结构1200下方并且在第二杂质区域300之间的部分中。
第二沟道区920的第二宽度W2可以小于图6中所示的第一沟道区910的第一宽度W1。
利用例如Si、Ge、Ar、Xe、BF3、As和In中的至少一种的离子注入可以应用到第二离子注入工艺I2，但是本发明构思不限于此。
参照图9，可以形成应力膜400以覆盖第一栅极结构1100、第二栅极结构1200、第一杂质区域200的上表面200b和第二杂质区域300的上表面300b。
应力膜400可以包括例如氮化硅，但是本发明构思不限于此。
应力膜400可以形成为具有例如大约5纳米至大约50纳米的厚度，但是本发明构思不限于此。
参照图10，可以通过执行退火工艺(例如，热处理工艺)来形成再结晶区域500。
具体地，可以通过由于执行退火工艺(例如，热处理工艺)使图9中所示的第一杂质区域200和第二杂质区域300再结晶来形成再结晶区域500。
退火工艺可以包括例如尖峰RTA(spike RTA)、闪光RTP和激光退火中的任何一种，但是本发明构思不限于此。
可以在由应力膜400引起的应力条件下发生再结晶晶格的生长，结果，可以形成再结晶的再结晶区域500。再结晶区域500包括沿(111)晶面形成的堆垛层错510。例如，堆垛层错510的堆垛层错面是(111)晶面。
在一些实施例中，堆垛层错510可以延伸为，随着堆垛层错510变得越接近再结晶区域500的上表面而越远离第二沟道区920，如图10中所示。
尽管图10描绘了堆垛层错510从再结晶区域500和第二沟道区920之间的边界开始，但是本发明构思不限于此。也就是说，在一些实施例中，堆垛层错510可以从再结晶区域500的内部的与再结晶区域500和第二沟道区920之间的边界间隔开的部分开始。
参照图11，可以去除图10中所示的应力膜400。
再结晶区域500可以记忆由图10中所示的应力膜400引起的应力。因此，当去除应力膜400时，可以保持包括堆垛层错510的再结晶区域500的结构。
参照图12，可以形成蚀刻停止膜600，以覆盖第一栅极结构1100、第二栅极结构1200和再结晶区域500的上表面。
参照图13，可以形成层间绝缘膜700以覆盖蚀刻停止膜600。
接下来，可以在再结晶区域500上形成沟槽以贯穿层间绝缘膜700、蚀刻停止膜600以及再结晶区域500的一部分。接下来，可以在沟槽中形成接触件710。
可以通过上述制造方法来制造根据一些实施例的半导体装置。
根据一些实施例的半导体装置的制造方法可以通过应用应力记忆技术(SMT)来增强半导体装置的性能，该应力记忆技术通过利用形成在DRAM的核心-外围区域中的晶体管中的应力膜400来在基底100中形成再结晶区域500。
此外，根据一些实施例的半导体装置的制造方法可以通过在去除第一栅极间隔件1150和第二栅极间隔件1250之后由于执行额外的离子注入工艺(例如，第二离子注入工艺I2)减小第二沟道区920的宽度来增强半导体装置的性能。
在下文中，将参照图14描述根据一些实施例的制造半导体装置的方法。将集中于与图3至图13中所示的方法的不同之处。
图14是示出根据本发明构思的一些实施例的制造半导体装置的方法的剖视图。
参照图14，在执行图10中所示的退火工艺(例如，热处理工艺)之后，可以形成层间绝缘膜700以覆盖应力膜400。
接下来，可以在再结晶区域500上形成沟槽以贯穿层间绝缘膜700、应力膜400以及再结晶区域500的一部分。接下来，可以在沟槽中形成接触件710。
以下，将参照图15至图17描述根据一些实施例的制造半导体装置的方法。将集中于与图3至图13中所示的方法的不同之处。
图15至图17是示出根据本发明构思的一些实施例的制造半导体装置的方法的剖视图。
参照图15，在执行图8中所示的第二离子注入工艺I2之后，可以形成栅极结构绝缘膜800以覆盖第一栅极结构1100、第二栅极结构1200、第一杂质区域200的上表面200b和第二杂质区域300的上表面300b。
接下来，可以形成应力膜400以覆盖栅极结构绝缘膜800。
参照图16，可以通过由于执行退火工艺(例如，热处理工艺)使图15中所示的第一杂质区域200和图15中所示的第二杂质区域300再结晶，来在基底100中形成再结晶区域500。
参照图17，可以形成层间绝缘膜700以覆盖应力膜400。
接下来，可以在再结晶区域500上形成沟槽以贯穿层间绝缘膜700、应力膜400、栅极结构绝缘膜800以及再结晶区域500的一部分。接下来，可以在沟槽中形成接触件710。
以下，将参照图15、图16和图11至图13描述根据一些实施例的制造半导体装置的方法。将集中于与图3至图13中所示的方法的不同之处。
在执行图8中所示的第二离子注入工艺I2之后，可以形成栅极结构绝缘膜800以覆盖第一栅极结构1100、第二栅极结构1200、第一杂质区域200的上表面200b和第二杂质区域300的上表面300b。
接下来，可以形成应力膜400以覆盖栅极结构绝缘膜800。
参照图16，通过由于执行退火工艺(例如，热处理工艺)使第一杂质区域200和第二杂质区域300再结晶，来在基底100中形成再结晶区域500。
返回参照图11，在执行图16中所示的退火工艺(例如，热处理工艺)之后，可以去除应力膜400和栅极结构绝缘膜800。
返回参照图12，可以形成蚀刻停止膜600以覆盖第一栅极结构1100、第二栅极结构1200以及再结晶区域500的上表面。
返回参照图13，可以形成层间绝缘膜700以覆盖蚀刻停止膜600。
接下来，可以在再结晶区域500上形成沟槽以贯穿层间绝缘膜700、蚀刻停止膜600以及再结晶区域500的一部分。接下来，可以在沟槽中形成接触件710。
以下，将参照图18和图19描述根据一些实施例的制造半导体装置的方法。将集中于与图3至图13中所示的方法的不同之处。
图18和图19是示出根据本发明构思的一些实施例的制造半导体装置的方法的剖视图。
参照图18，可以在如图7中所示去除图6中所示的第一栅极间隔件1150和图6中所示的第二栅极间隔件1250之后，执行第二离子注入工艺I2。
通过第二离子注入工艺I2，可以在基底100中并且在第一栅极结构1100和第一杂质区域200之间以及在第二栅极结构1200和第一杂质区域200之间形成作为非晶区域的第二杂质区域310。
第二杂质区域310可以具有从第二杂质区域310的上表面310b至第二杂质区域310的下表面310a的第三深度h3。在这种情况下，第二杂质区域310的第三深度h3可以小于第一杂质区域200的第一深度h1。
参照图19，可以通过由于执行退火工艺(例如，热处理工艺)使图18中所示的第一杂质区域200和图18中所示的第二杂质区域300再结晶，来在基底100中形成再结晶区域501。再结晶区域501包括沿(111)晶面形成的堆垛层错520。第三沟道区930可以形成在基底100的位于第一栅极结构1100下方并且在再结晶区域501之间的部分中，并且第三沟道区930的在第三方向Z上的下表面可以高于再结晶区域501的下表面501a。
在此参照附图解释了根据本发明构思的示例实施例，但是应当理解的是，本发明构思不限于上述示例实施例，而是可以以各种不同的形式来制造，并且可以在不改变本发明构思的技术构思或本质特征的情况下，由本领域技术人员以其它具体形式来实现本发明构思。因此，将理解的是，上述示例实施例仅是说明性的，不应被解释为限制性的。所附权利要求意在覆盖落入本发明构思的真实精神和范围内的所有修改、增强和其它实施例。因此，在法律允许的最大范围内，范围应该通过所附权利要求及其等同物的最宽泛的可允许解释来确定，并且不应受前述详细描述的局限或限制。

Claims (10)

1.一种半导体装置，所述半导体装置包括：
基底，包括形成有单元区域的第一区域和形成有核心-外围区域的第二区域；
栅极堆叠件，位于所述基底的所述第二区域上，所述栅极堆叠件包括包含氧化物的第一栅极绝缘膜、位于所述第一栅极绝缘膜上的包括铪的第二栅极绝缘膜、位于所述第二栅极绝缘膜上的包括镧和氮化钛的第一电极、位于所述第一电极上的第二电极；
栅极堆叠绝缘膜，接触所述栅极堆叠件的侧表面和顶表面；
杂质区域，具有设置在所述基底的所述第二区域中位于所述栅极堆叠件的至少一侧上的堆垛层错；
氮化硅膜，覆盖所述杂质区域的上表面，所述氮化硅膜与所述栅极堆叠绝缘膜接触；以及
接触件，穿过所述氮化硅膜延伸至所述杂质区域。
2.根据权利要求1所述的半导体装置，其中，所述第一栅极绝缘膜包括氧化硅，所述第二栅极绝缘膜包括氮氧化铪硅，并且所述第二电极包括多晶硅、氮化钛硅和钨。
3.根据权利要求1所述的半导体装置，其中，所述堆垛层错设置在所述杂质区域的内部，所述堆垛层错从所述杂质区域的与所述栅极堆叠件相邻的下表面延伸，所述堆垛层错与所述杂质区域的所述下表面形成锐角。
4.根据权利要求1所述的半导体装置，所述半导体装置还包括：
第三电极，位于所述第二栅极绝缘膜与所述第一电极之间，所述第三电极包括第一氮化钛膜、铝膜和第二氮化钛膜。
5.根据权利要求1所述的半导体装置，其中，所述氮化硅膜在所述栅极堆叠件的所述侧表面和所述上表面上与所述栅极堆叠绝缘膜接触。
6.根据权利要求1所述的半导体装置，其中，所述杂质区域包括第一部分以及位于所述第一部分与所述栅极堆叠件之间的第二部分，
其中，从所述杂质区域的所述第一部分的上表面至所述杂质区域的所述第一部分的下表面的第一深度大于从所述杂质区域的所述第二部分的上表面至所述杂质区域的所述第二部分的下表面的第二深度，并且
其中，所述堆垛层错设置在所述杂质区域的所述第二部分处。
7.一种半导体装置，所述半导体装置包括：
基底，包括形成有单元区域的第一区域和形成有核心-外围区域的第二区域；
栅极堆叠件，位于所述基底的所述第二区域上，所述栅极堆叠件包括包含氧化物的第一栅极绝缘膜、位于所述第一栅极绝缘膜上的包括铪的第二栅极绝缘膜、位于所述第二栅极绝缘膜上的第一电极、位于所述第一电极上的包括镧和氮化钛的第二电极、位于所述第二电极上的第三电极，所述第一电极包括第一氮化钛膜、铝膜和第二氮化钛膜；
栅极堆叠绝缘膜，接触所述栅极堆叠件的侧表面和顶表面；
杂质区域，具有设置在所述基底的所述第二区域中位于所述栅极堆叠件的至少一侧上的堆垛层错；
氮化硅膜，覆盖所述杂质区域的上表面，所述氮化硅膜与所述栅极堆叠绝缘膜接触；以及
接触件，穿过所述氮化硅膜延伸至所述杂质区域。
8.根据权利要求7所述的半导体装置，其中，所述堆垛层错设置在所述杂质区域的内部，所述堆垛层错从所述杂质区域的与所述栅极堆叠件相邻的下表面延伸，所述堆垛层错与所述杂质区域的所述下表面形成锐角。
9.根据权利要求7所述的半导体装置，其中，所述第一栅极绝缘膜包括氧化硅，所述第二栅极绝缘膜包括氮氧化铪硅，并且所述第三电极包括多晶硅、氮化钛硅和钨。
10.一种半导体装置，所述半导体装置包括：
基底，包括形成有单元区域的第一区域和形成有核心-外围区域的第二区域；
栅极堆叠件，位于所述基底的所述第二区域上，所述栅极堆叠件包括包含氧化物的第一栅极绝缘膜、位于所述第一栅极绝缘膜上的包括铪的第二栅极绝缘膜、位于所述第二栅极绝缘膜上的包括镧和氮化钛的第一电极、位于所述第一电极上的第二电极；
栅极堆叠绝缘膜，接触所述栅极堆叠件的侧表面和顶表面；
杂质区域，具有设置在所述基底的所述第二区域中位于所述栅极堆叠件的一侧上的堆垛层错；
栅极结构绝缘膜，覆盖所述杂质区域的上表面，所述栅极结构绝缘膜与所述栅极堆叠绝缘膜接触；以及
氮化硅膜，与所述栅极结构绝缘膜接触；以及
接触件，穿过所述氮化硅膜和所述栅极结构绝缘膜延伸至所述杂质区域。
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CN110610855A (zh) 2019-12-24
US20190386008A1 (en) 2019-12-19

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