CN114512462A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN114512462A CN114512462A CN202111331458.1A CN202111331458A CN114512462A CN 114512462 A CN114512462 A CN 114512462A CN 202111331458 A CN202111331458 A CN 202111331458A CN 114512462 A CN114512462 A CN 114512462A
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- electrode
- semiconductor device
- circuit pattern
- insulating substrate
- semiconductor element
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910000679 solder Inorganic materials 0.000 claims abstract description 22
- 230000000630 rising effect Effects 0.000 claims description 20
- 238000005476 soldering Methods 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 230000001351 cycling effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003566 sealing material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
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- 238000004382 potting Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
得到能够提高可靠性的半导体装置及其制造方法。绝缘基板(1)具有电路图案(4)。半导体元件(8)安装于绝缘基板(1)之上,与电路图案(4)电连接。壳体(11)将绝缘基板(1)以及半导体元件(8)收容。电极(12)设置于壳体(11)。电极(12)的前端面通过焊料(14)而与电路图案(4)接合。电极(12)被壳体(11)压接于电路图案(4)。在前端面设置有凸起(12d)。
Description
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
公开了安装于壳体的电极被焊接于绝缘基板的电路图案的半导体装置(例如,参照专利文献1)。
专利文献1:日本特开2006-295158号公报
在温度循环时由于结构部件的线膨胀系数差而在半导体装置产生翘曲。由此,电极相对于壳体以及绝缘基板的上下方向的位置发生变化,因此,在电极的焊接部沿上下方向作用有拉伸应力或压缩应力。由于存在绝缘基板,因此电极难以在压缩方向上产生位移。但是,电极容易在拉伸方向上产生位移,因此,存在焊料劣化而产生剥离、可靠性下降的问题。
发明内容
本发明就是为了解决上述这样的课题而提出的,其目的在于得到能够提高可靠性的半导体装置及其制造方法。
本发明涉及的半导体装置的特征在于,具有:绝缘基板,其具有电路图案;半导体元件,其安装于所述绝缘基板之上,与所述电路图案电连接;壳体,其将所述绝缘基板以及所述半导体元件收容;以及
电极,其设置于所述壳体,所述电极的前端面被焊接于所述电路图案,所述电极被所述壳体压接于所述电路图案,在所述前端面设置有凸起。
发明的效果
在本发明中,电极被壳体压接于电路图案。由此,能够减小由于温度循环时的翘曲而在电极与电路图案的接合部产生的拉伸应力。另外,焊料的厚度由于压接而减小,但能够通过在前端面设置凸起而确保焊料的厚度。因此,能够防止温度循环时的焊料的剥离,提高可靠性。
附图说明
图1是表示实施方式1涉及的半导体装置的剖视图。
图2是沿图1的I-II的放大剖视图。
图3是表示实施方式1涉及的半导体装置的制造工序的图。
图4是表示实施方式1涉及的半导体装置的制造工序的图。
图5是将实施方式1涉及的半导体装置的一部分放大的剖视图。
图6是表示实施方式2涉及的半导体装置的剖视图。
图7是表示实施方式2涉及的半导体装置的变形例的剖视图。
图8是表示实施方式2涉及的半导体装置的变形例的俯视图。
图9是表示实施方式3涉及的半导体装置的剖视图。
图10是表示实施方式4涉及的半导体装置的剖视图。
图11是沿图10的I-II的放大剖视图。
图12是表示实施方式5涉及的半导体装置的剖视图。
图13是表示实施方式6涉及的电极的立起部的侧视图。
图14是表示实施方式6涉及的电极的立起部的变形例1的侧视图。
图15是表示实施方式6涉及的电极的立起部的变形例2的侧视图。
具体实施方式
参照附图,对实施方式涉及的半导体装置及其制造方法进行说明。对相同或相应的结构要素标注相同的标号,有时省略重复说明。
实施方式1.
图1是表示实施方式1涉及的半导体装置的剖视图。绝缘基板1具有绝缘板2、绝缘板2的下表面的金属图案3和绝缘板2的上表面的电路图案4、5。绝缘板2是AlN或SiN等陶瓷,也可以是树脂绝缘。
绝缘基板1的金属图案3通过焊料6而与基座板6的上表面接合。半导体元件8安装于绝缘基板1之上。半导体元件8的下表面电极通过焊料9而与电路图案4电连接。此外,不限于焊接,也可以是Ag接合或激光熔接等。半导体元件8的上表面电极通过导线等配线10而与电路图案5电连接。壳体11将绝缘基板1以及半导体元件8收容。壳体11被粘接于基座板6的上表面。
电极12、13安装于壳体11。电极12的前端面通过焊料14而与电路图案4接合。电极12、13呈板状,具有前端面、彼此相对的主面和彼此相对的侧面。前端面呈长方形,前端面的短边对应于电极12的板厚度,前端面的长边对应于电极12的横向宽度。
封装材料15将绝缘基板1、半导体元件8以及电极12封装,使半导体元件8等与外部电绝缘。封装材料15例如是凝胶,优选直接灌封树脂等树脂。通过树脂而抑制温度循环时的电极12的位移,因此焊接的可靠性提高。
电极12具有被嵌入而固定于壳体11的固定部12a、在电路图案4之上立起的立起部12b和将固定部12a与立起部12b的上端连接的连接部12c。电极12的立起部12b的上端的高度比固定部12a的高度高。固定部12a与基座板6的上表面以及绝缘基板1的电路图案4、5平行。另一方面,引出至壳体11的内部空间中的连接部12c从固定部12a朝向立起部12b的上端而上升,相对于基座板6的上表面以及绝缘基板1的电路图案4、5而倾斜。由于是这样的结构,因此电极12被壳体11压接于电路图案4。与电极12同样地,电极13的前端面被焊接于电路图案5,电极13被壳体11压接于电路图案5。
图2是沿图1的I-II的放大剖视图。在前端面设置有凸起12d。通过对电极12的凸起12d进行压接,从而在电路图案4的表面形成少许压痕。与电极12同样地,在电极13的前端面也设置有凸起(未图示)。
接下来,对本实施方式涉及的半导体装置的制造方法进行说明。图3以及图4是表示实施方式1涉及的半导体装置的制造工序的图。首先,将半导体元件8安装于绝缘基板1之上,与绝缘基板1的电路图案4电连接。接下来,以将绝缘基板1以及半导体元件8收容的方式而将壳体11安装于基座板6的上表面。此时,通过壳体11而将电极12压接于电路图案4。并且,将电极12的前端面焊接于电路图案4。
在安装壳体11之前,如图3所示,电极12的固定部12a和连接部12c呈直线状,电极12的立起部12b的上端的高度与固定部12a的高度相同。在安装了壳体11之后,如图4所示,电极12的立起部12b的上端的高度比固定部12a的高度高。这样,电极12变形,由此,电极12被压接于电路图案4。
在本实施方式中,电极12被壳体11压接于电路图案4。由此,能够减小由于温度循环时的翘曲而在电极12与电路图案4的接合部产生的拉伸应力。另外,焊料14的厚度由于压接而减小,但能够通过在前端面设置凸起12d而确保焊料14的厚度。因此,能够防止温度循环时的焊料的剥离,提高可靠性。
另外,在应力变大的前端面的外周部存在焊料14这一情况能够缓和应力。因此,优选凸起12d不设置于前端面的外周部。并且,优选凸起12d为大于或等于2个,以能够均一地保持焊料14的厚度。由此,焊接的可靠性提高。
另外,不是板状的电极12的平面、而是电极12的立起部12b的前端面与电路图案4接合。由此,电极12的接合面积减小。因此,在将半导体元件8或配线10与接合有电极12的电路图案4接合的情况下,将它们进行接合的空间增加。另外,还能够增加电流容量。
图5是将实施方式1涉及的半导体装置的一部分放大的剖视图。从电极12与电路图案4的接合部起至电路图案4的端部、半导体元件8或外部配线10为止的距离R大于或等于焊料14的高度L(R≥L)。由此,焊料14的胶瘤成为角度小于45℃的平缓的形状,向焊料14的应力减小,因此,焊接的可靠性提高。
实施方式2.
图6是表示实施方式2涉及的半导体装置的剖视图。壳体11具有将绝缘基板1以及半导体元件8包围的方框即外壁11a和从外壁11a凸出至外壁11a的内侧的凸出部11b。被引出至外壁11a的内侧的电极12的连接部12c向上方产生位移,但与凸出部11b的下表面接触而被按下。由此,电极12受到向电路图案4压接的力。由此,与实施方式1同样地,能够减小由于温度循环时的翘曲而在电极12与电路图案4的接合部产生的拉伸应力。
图7是表示实施方式2涉及的半导体装置的变形例的剖视图。图8是表示实施方式2涉及的半导体装置的变形例的俯视图。凸出部11b成为横跨壳体11的彼此相对的外壁11a的梁。在这种情况下,也取得上述效果。
实施方式3.
图9是表示实施方式3涉及的半导体装置的剖视图。壳体11被直接粘接、固定于绝缘基板1。其它结构与实施方式1相同。在这种情况下,电极12、13也被壳体11压接于电路图案4、5,能够得到与实施方式1相同的效果。
实施方式4.
图10是表示实施方式4涉及的半导体装置的剖视图。图11是沿图10的I-II的放大剖视图。在电路图案4设置有凹部16。凹部16不需要将电路图案4贯通而到达绝缘板2。凸起12d嵌合于凹部16。由此,电路图案4与焊料14的接合区域增加,因此,接合的可靠性提高。
实施方式5.
图12是表示实施方式5涉及的半导体装置的剖视图。其它电极17与电极12平行地配置。如果将电流的流向相反的2个电极12、17接近地平行配置,则彼此抵消磁场,因此,能够减小电感。另外,在2个电极12、17同电位的情况下,能够增加电极密度,因此,通电能力提高。
实施方式6.
图13是表示实施方式6涉及的电极的立起部的侧视图。在电极12的立起部12b的侧面设置有切口12e。由于切口12e,电极12的刚性下降。因此,由电极12的变形引起的向焊料14的应力减小,所以焊接的可靠性提高。
图14是表示实施方式6涉及的电极的立起部的变形例1的侧视图。在图13中,切口12e设置于立起部12b的两侧,但在图14中仅设置于一侧。在这种情况下,也能够得到相同的效果。
图15是表示实施方式6涉及的电极的立起部的变形例2的侧视图。切口12e沿厚度方向设置,电极12的立起部12b的厚度局部地变薄。由于该薄部,电极12的刚性下降。因此,由电极12的变形引起的向焊料14的应力减小,所以焊接的可靠性提高。
此外,半导体元件8不限于由硅形成,也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或金刚石。由这样的宽带隙半导体形成的半导体元件由于耐电压性、容许电流密度高,因此能够小型化。通过使用该小型化的半导体元件,从而组装了该半导体元件的半导体装置也能够小型化、高集成化。另外,由于半导体元件的耐热性高,因此,能够使散热器的散热鳍片小型化,能够使水冷部空冷化,因而能够使半导体装置进一步小型化。另外,由于半导体元件的电力损耗低且高效,因此能够使半导体装置高效化。
另外,由宽带隙半导体构成的半导体元件8能够实现高温动作。与此相对,能够通过应用上述的实施方式而减小焊料14的应力,因此,高温时的可靠性提高。
标号的说明
1绝缘基板,4电路图案,6基座板,8半导体元件,10配线,11壳体,11a外壁,11b凸出部,12电极,12a固定部,12b立起部,12d凸起,12e切口,14焊料,15封装材料,16凹部
Claims (16)
1.一种半导体装置,其特征在于,具有:
绝缘基板,其具有电路图案;
半导体元件,其安装于所述绝缘基板之上,与所述电路图案电连接;
壳体,其将所述绝缘基板以及所述半导体元件收容;以及
电极,其设置于所述壳体,
所述电极的前端面被焊接于所述电路图案,
所述电极被所述壳体压接于所述电路图案,
在所述前端面设置有凸起。
2.根据权利要求1所述的半导体装置,其特征在于,
所述电极具有被固定于所述壳体的固定部和在所述电路图案之上立起的立起部,
所述电极的所述立起部的上端的高度比所述固定部的高度高。
3.根据权利要求1或2所述的半导体装置,其特征在于,
所述壳体具有将所述绝缘基板以及所述半导体元件包围的外壁和从所述外壁凸出至所述外壁的内侧的凸出部,
所述电极通过与所述凸出部的下表面接触而被按下,从而受到向所述电路图案压接的力。
4.根据权利要求1至3中任一项所述的半导体装置,其特征在于,
还具有基座板,
所述绝缘基板与所述基座板的上表面接合,
所述壳体被粘接于所述基座板的上表面。
5.根据权利要求1至3中任一项所述的半导体装置,其特征在于,
所述壳体被直接粘接于所述绝缘基板。
6.根据权利要求1至5中任一项所述的半导体装置,其特征在于,
在所述电路图案设置有凹部,
所述凸起被嵌合于所述凹部。
7.根据权利要求1至6中任一项所述的半导体装置,其特征在于,
还具有与所述电极平行地配置的其它电极。
8.根据权利要求1至7中任一项所述的半导体装置,其特征在于,
所述凸起未设置于所述前端面的外周部。
9.根据权利要求1至8中任一项所述的半导体装置,其特征在于,
所述凸起大于或等于2个。
10.根据权利要求1至9中任一项所述的半导体装置,其特征在于,
在所述电极的所述立起部的侧面设置有切口。
11.根据权利要求1至9中任一项所述的半导体装置,其特征在于,
所述电极的所述立起部的厚度局部地变薄。
12.根据权利要求1至11中任一项所述的半导体装置,其特征在于,
在接合有所述电极的所述电路图案接合有所述半导体元件或配线。
13.根据权利要求12所述的半导体装置,其特征在于,
从所述电极与所述电路图案的接合部起至所述电路图案的端部、所述半导体元件或所述外部配线为止的距离大于或等于所述焊料的高度。
14.根据权利要求1至13中任一项所述的半导体装置,其特征在于,
还具有将所述绝缘基板、所述半导体元件以及所述电极封装的树脂。
15.根据权利要求1至14中任一项所述的半导体装置,其特征在于,
所述半导体元件由宽带隙半导体形成。
16.一种半导体装置的制造方法,其特征在于,具有以下工序:
将半导体元件安装于绝缘基板之上,与所述绝缘基板的电路图案电连接;以及
以将所述绝缘基板以及所述半导体元件收容的方式安装壳体,将在所述壳体设置的电极的前端面焊接于所述电路图案,
在安装所述壳体时,通过所述壳体将所述电极压接于所述电路图案,
在所述前端面设置有凸起。
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