CN114512462A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN114512462A
CN114512462A CN202111331458.1A CN202111331458A CN114512462A CN 114512462 A CN114512462 A CN 114512462A CN 202111331458 A CN202111331458 A CN 202111331458A CN 114512462 A CN114512462 A CN 114512462A
Authority
CN
China
Prior art keywords
electrode
semiconductor device
circuit pattern
insulating substrate
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111331458.1A
Other languages
English (en)
Inventor
高桥卓也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN114512462A publication Critical patent/CN114512462A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4817Conductive parts for containers, e.g. caps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/8322Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/83224Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3672Foil-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10254Diamond [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1027IV
    • H01L2924/10272Silicon Carbide [SiC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/1033Gallium nitride [GaN]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

得到能够提高可靠性的半导体装置及其制造方法。绝缘基板(1)具有电路图案(4)。半导体元件(8)安装于绝缘基板(1)之上,与电路图案(4)电连接。壳体(11)将绝缘基板(1)以及半导体元件(8)收容。电极(12)设置于壳体(11)。电极(12)的前端面通过焊料(14)而与电路图案(4)接合。电极(12)被壳体(11)压接于电路图案(4)。在前端面设置有凸起(12d)。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
公开了安装于壳体的电极被焊接于绝缘基板的电路图案的半导体装置(例如,参照专利文献1)。
专利文献1:日本特开2006-295158号公报
在温度循环时由于结构部件的线膨胀系数差而在半导体装置产生翘曲。由此,电极相对于壳体以及绝缘基板的上下方向的位置发生变化,因此,在电极的焊接部沿上下方向作用有拉伸应力或压缩应力。由于存在绝缘基板,因此电极难以在压缩方向上产生位移。但是,电极容易在拉伸方向上产生位移,因此,存在焊料劣化而产生剥离、可靠性下降的问题。
发明内容
本发明就是为了解决上述这样的课题而提出的,其目的在于得到能够提高可靠性的半导体装置及其制造方法。
本发明涉及的半导体装置的特征在于,具有:绝缘基板,其具有电路图案;半导体元件,其安装于所述绝缘基板之上,与所述电路图案电连接;壳体,其将所述绝缘基板以及所述半导体元件收容;以及
电极,其设置于所述壳体,所述电极的前端面被焊接于所述电路图案,所述电极被所述壳体压接于所述电路图案,在所述前端面设置有凸起。
发明的效果
在本发明中,电极被壳体压接于电路图案。由此,能够减小由于温度循环时的翘曲而在电极与电路图案的接合部产生的拉伸应力。另外,焊料的厚度由于压接而减小,但能够通过在前端面设置凸起而确保焊料的厚度。因此,能够防止温度循环时的焊料的剥离,提高可靠性。
附图说明
图1是表示实施方式1涉及的半导体装置的剖视图。
图2是沿图1的I-II的放大剖视图。
图3是表示实施方式1涉及的半导体装置的制造工序的图。
图4是表示实施方式1涉及的半导体装置的制造工序的图。
图5是将实施方式1涉及的半导体装置的一部分放大的剖视图。
图6是表示实施方式2涉及的半导体装置的剖视图。
图7是表示实施方式2涉及的半导体装置的变形例的剖视图。
图8是表示实施方式2涉及的半导体装置的变形例的俯视图。
图9是表示实施方式3涉及的半导体装置的剖视图。
图10是表示实施方式4涉及的半导体装置的剖视图。
图11是沿图10的I-II的放大剖视图。
图12是表示实施方式5涉及的半导体装置的剖视图。
图13是表示实施方式6涉及的电极的立起部的侧视图。
图14是表示实施方式6涉及的电极的立起部的变形例1的侧视图。
图15是表示实施方式6涉及的电极的立起部的变形例2的侧视图。
具体实施方式
参照附图,对实施方式涉及的半导体装置及其制造方法进行说明。对相同或相应的结构要素标注相同的标号,有时省略重复说明。
实施方式1.
图1是表示实施方式1涉及的半导体装置的剖视图。绝缘基板1具有绝缘板2、绝缘板2的下表面的金属图案3和绝缘板2的上表面的电路图案4、5。绝缘板2是AlN或SiN等陶瓷,也可以是树脂绝缘。
绝缘基板1的金属图案3通过焊料6而与基座板6的上表面接合。半导体元件8安装于绝缘基板1之上。半导体元件8的下表面电极通过焊料9而与电路图案4电连接。此外,不限于焊接,也可以是Ag接合或激光熔接等。半导体元件8的上表面电极通过导线等配线10而与电路图案5电连接。壳体11将绝缘基板1以及半导体元件8收容。壳体11被粘接于基座板6的上表面。
电极12、13安装于壳体11。电极12的前端面通过焊料14而与电路图案4接合。电极12、13呈板状,具有前端面、彼此相对的主面和彼此相对的侧面。前端面呈长方形,前端面的短边对应于电极12的板厚度,前端面的长边对应于电极12的横向宽度。
封装材料15将绝缘基板1、半导体元件8以及电极12封装,使半导体元件8等与外部电绝缘。封装材料15例如是凝胶,优选直接灌封树脂等树脂。通过树脂而抑制温度循环时的电极12的位移,因此焊接的可靠性提高。
电极12具有被嵌入而固定于壳体11的固定部12a、在电路图案4之上立起的立起部12b和将固定部12a与立起部12b的上端连接的连接部12c。电极12的立起部12b的上端的高度比固定部12a的高度高。固定部12a与基座板6的上表面以及绝缘基板1的电路图案4、5平行。另一方面,引出至壳体11的内部空间中的连接部12c从固定部12a朝向立起部12b的上端而上升,相对于基座板6的上表面以及绝缘基板1的电路图案4、5而倾斜。由于是这样的结构,因此电极12被壳体11压接于电路图案4。与电极12同样地,电极13的前端面被焊接于电路图案5,电极13被壳体11压接于电路图案5。
图2是沿图1的I-II的放大剖视图。在前端面设置有凸起12d。通过对电极12的凸起12d进行压接,从而在电路图案4的表面形成少许压痕。与电极12同样地,在电极13的前端面也设置有凸起(未图示)。
接下来,对本实施方式涉及的半导体装置的制造方法进行说明。图3以及图4是表示实施方式1涉及的半导体装置的制造工序的图。首先,将半导体元件8安装于绝缘基板1之上,与绝缘基板1的电路图案4电连接。接下来,以将绝缘基板1以及半导体元件8收容的方式而将壳体11安装于基座板6的上表面。此时,通过壳体11而将电极12压接于电路图案4。并且,将电极12的前端面焊接于电路图案4。
在安装壳体11之前,如图3所示,电极12的固定部12a和连接部12c呈直线状,电极12的立起部12b的上端的高度与固定部12a的高度相同。在安装了壳体11之后,如图4所示,电极12的立起部12b的上端的高度比固定部12a的高度高。这样,电极12变形,由此,电极12被压接于电路图案4。
在本实施方式中,电极12被壳体11压接于电路图案4。由此,能够减小由于温度循环时的翘曲而在电极12与电路图案4的接合部产生的拉伸应力。另外,焊料14的厚度由于压接而减小,但能够通过在前端面设置凸起12d而确保焊料14的厚度。因此,能够防止温度循环时的焊料的剥离,提高可靠性。
另外,在应力变大的前端面的外周部存在焊料14这一情况能够缓和应力。因此,优选凸起12d不设置于前端面的外周部。并且,优选凸起12d为大于或等于2个,以能够均一地保持焊料14的厚度。由此,焊接的可靠性提高。
另外,不是板状的电极12的平面、而是电极12的立起部12b的前端面与电路图案4接合。由此,电极12的接合面积减小。因此,在将半导体元件8或配线10与接合有电极12的电路图案4接合的情况下,将它们进行接合的空间增加。另外,还能够增加电流容量。
图5是将实施方式1涉及的半导体装置的一部分放大的剖视图。从电极12与电路图案4的接合部起至电路图案4的端部、半导体元件8或外部配线10为止的距离R大于或等于焊料14的高度L(R≥L)。由此,焊料14的胶瘤成为角度小于45℃的平缓的形状,向焊料14的应力减小,因此,焊接的可靠性提高。
实施方式2.
图6是表示实施方式2涉及的半导体装置的剖视图。壳体11具有将绝缘基板1以及半导体元件8包围的方框即外壁11a和从外壁11a凸出至外壁11a的内侧的凸出部11b。被引出至外壁11a的内侧的电极12的连接部12c向上方产生位移,但与凸出部11b的下表面接触而被按下。由此,电极12受到向电路图案4压接的力。由此,与实施方式1同样地,能够减小由于温度循环时的翘曲而在电极12与电路图案4的接合部产生的拉伸应力。
图7是表示实施方式2涉及的半导体装置的变形例的剖视图。图8是表示实施方式2涉及的半导体装置的变形例的俯视图。凸出部11b成为横跨壳体11的彼此相对的外壁11a的梁。在这种情况下,也取得上述效果。
实施方式3.
图9是表示实施方式3涉及的半导体装置的剖视图。壳体11被直接粘接、固定于绝缘基板1。其它结构与实施方式1相同。在这种情况下,电极12、13也被壳体11压接于电路图案4、5,能够得到与实施方式1相同的效果。
实施方式4.
图10是表示实施方式4涉及的半导体装置的剖视图。图11是沿图10的I-II的放大剖视图。在电路图案4设置有凹部16。凹部16不需要将电路图案4贯通而到达绝缘板2。凸起12d嵌合于凹部16。由此,电路图案4与焊料14的接合区域增加,因此,接合的可靠性提高。
实施方式5.
图12是表示实施方式5涉及的半导体装置的剖视图。其它电极17与电极12平行地配置。如果将电流的流向相反的2个电极12、17接近地平行配置,则彼此抵消磁场,因此,能够减小电感。另外,在2个电极12、17同电位的情况下,能够增加电极密度,因此,通电能力提高。
实施方式6.
图13是表示实施方式6涉及的电极的立起部的侧视图。在电极12的立起部12b的侧面设置有切口12e。由于切口12e,电极12的刚性下降。因此,由电极12的变形引起的向焊料14的应力减小,所以焊接的可靠性提高。
图14是表示实施方式6涉及的电极的立起部的变形例1的侧视图。在图13中,切口12e设置于立起部12b的两侧,但在图14中仅设置于一侧。在这种情况下,也能够得到相同的效果。
图15是表示实施方式6涉及的电极的立起部的变形例2的侧视图。切口12e沿厚度方向设置,电极12的立起部12b的厚度局部地变薄。由于该薄部,电极12的刚性下降。因此,由电极12的变形引起的向焊料14的应力减小,所以焊接的可靠性提高。
此外,半导体元件8不限于由硅形成,也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或金刚石。由这样的宽带隙半导体形成的半导体元件由于耐电压性、容许电流密度高,因此能够小型化。通过使用该小型化的半导体元件,从而组装了该半导体元件的半导体装置也能够小型化、高集成化。另外,由于半导体元件的耐热性高,因此,能够使散热器的散热鳍片小型化,能够使水冷部空冷化,因而能够使半导体装置进一步小型化。另外,由于半导体元件的电力损耗低且高效,因此能够使半导体装置高效化。
另外,由宽带隙半导体构成的半导体元件8能够实现高温动作。与此相对,能够通过应用上述的实施方式而减小焊料14的应力,因此,高温时的可靠性提高。
标号的说明
1绝缘基板,4电路图案,6基座板,8半导体元件,10配线,11壳体,11a外壁,11b凸出部,12电极,12a固定部,12b立起部,12d凸起,12e切口,14焊料,15封装材料,16凹部

Claims (16)

1.一种半导体装置,其特征在于,具有:
绝缘基板,其具有电路图案;
半导体元件,其安装于所述绝缘基板之上,与所述电路图案电连接;
壳体,其将所述绝缘基板以及所述半导体元件收容;以及
电极,其设置于所述壳体,
所述电极的前端面被焊接于所述电路图案,
所述电极被所述壳体压接于所述电路图案,
在所述前端面设置有凸起。
2.根据权利要求1所述的半导体装置,其特征在于,
所述电极具有被固定于所述壳体的固定部和在所述电路图案之上立起的立起部,
所述电极的所述立起部的上端的高度比所述固定部的高度高。
3.根据权利要求1或2所述的半导体装置,其特征在于,
所述壳体具有将所述绝缘基板以及所述半导体元件包围的外壁和从所述外壁凸出至所述外壁的内侧的凸出部,
所述电极通过与所述凸出部的下表面接触而被按下,从而受到向所述电路图案压接的力。
4.根据权利要求1至3中任一项所述的半导体装置,其特征在于,
还具有基座板,
所述绝缘基板与所述基座板的上表面接合,
所述壳体被粘接于所述基座板的上表面。
5.根据权利要求1至3中任一项所述的半导体装置,其特征在于,
所述壳体被直接粘接于所述绝缘基板。
6.根据权利要求1至5中任一项所述的半导体装置,其特征在于,
在所述电路图案设置有凹部,
所述凸起被嵌合于所述凹部。
7.根据权利要求1至6中任一项所述的半导体装置,其特征在于,
还具有与所述电极平行地配置的其它电极。
8.根据权利要求1至7中任一项所述的半导体装置,其特征在于,
所述凸起未设置于所述前端面的外周部。
9.根据权利要求1至8中任一项所述的半导体装置,其特征在于,
所述凸起大于或等于2个。
10.根据权利要求1至9中任一项所述的半导体装置,其特征在于,
在所述电极的所述立起部的侧面设置有切口。
11.根据权利要求1至9中任一项所述的半导体装置,其特征在于,
所述电极的所述立起部的厚度局部地变薄。
12.根据权利要求1至11中任一项所述的半导体装置,其特征在于,
在接合有所述电极的所述电路图案接合有所述半导体元件或配线。
13.根据权利要求12所述的半导体装置,其特征在于,
从所述电极与所述电路图案的接合部起至所述电路图案的端部、所述半导体元件或所述外部配线为止的距离大于或等于所述焊料的高度。
14.根据权利要求1至13中任一项所述的半导体装置,其特征在于,
还具有将所述绝缘基板、所述半导体元件以及所述电极封装的树脂。
15.根据权利要求1至14中任一项所述的半导体装置,其特征在于,
所述半导体元件由宽带隙半导体形成。
16.一种半导体装置的制造方法,其特征在于,具有以下工序:
将半导体元件安装于绝缘基板之上,与所述绝缘基板的电路图案电连接;以及
以将所述绝缘基板以及所述半导体元件收容的方式安装壳体,将在所述壳体设置的电极的前端面焊接于所述电路图案,
在安装所述壳体时,通过所述壳体将所述电极压接于所述电路图案,
在所述前端面设置有凸起。
CN202111331458.1A 2020-11-16 2021-11-11 半导体装置及其制造方法 Pending CN114512462A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-190395 2020-11-16
JP2020190395A JP7435415B2 (ja) 2020-11-16 2020-11-16 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
CN114512462A true CN114512462A (zh) 2022-05-17

Family

ID=81345681

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111331458.1A Pending CN114512462A (zh) 2020-11-16 2021-11-11 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US11605568B2 (zh)
JP (1) JP7435415B2 (zh)
CN (1) CN114512462A (zh)
DE (1) DE102021121875A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240021505A1 (en) * 2022-07-12 2024-01-18 Littelfuse, Inc. Solderless and pressure contact connection

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005016650B4 (de) 2005-04-12 2009-11-19 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit stumpf gelöteten Anschluss- und Verbindungselementen
JP2014232832A (ja) 2013-05-30 2014-12-11 カルソニックカンセイ株式会社 電源装置およびビームリード
JP6308300B2 (ja) * 2014-08-12 2018-04-11 富士電機株式会社 半導体装置
US10475667B2 (en) 2014-11-06 2019-11-12 Mitsubishi Electric Corporation Semiconductor module and conductive member for semiconductor module including cut in bent portion
JP6272213B2 (ja) 2014-11-26 2018-01-31 三菱電機株式会社 半導体装置
DE112015005654T5 (de) * 2014-12-18 2017-08-31 Mitsubishi Electric Corporation Isolierte Leiterplatte, Leistungsmodul und Leistungseinheit
JP6621714B2 (ja) * 2016-07-01 2019-12-18 三菱電機株式会社 半導体装置
JP6515886B2 (ja) 2016-07-08 2019-05-22 株式会社豊田自動織機 半導体モジュール
US10622288B2 (en) * 2017-11-06 2020-04-14 Rohm Co., Ltd. Semiconductor device and method for producing semiconductor device
JP2020190395A (ja) 2019-05-23 2020-11-26 積水化学工業株式会社 温度調節システム

Also Published As

Publication number Publication date
JP7435415B2 (ja) 2024-02-21
US20220157672A1 (en) 2022-05-19
US11605568B2 (en) 2023-03-14
DE102021121875A1 (de) 2022-05-19
JP2022079287A (ja) 2022-05-26

Similar Documents

Publication Publication Date Title
JP6484588B2 (ja) 発光装置及び発光装置用パッケージ
JP4613077B2 (ja) 半導体装置、電極用部材および電極用部材の製造方法
KR101513961B1 (ko) 전력 반도체 모듈 및 그 제조방법
JP7452597B2 (ja) 半導体装置及びその製造方法
JP4899481B2 (ja) 外部に露出する放熱体を上部に有する樹脂封止型半導体装置の製法
CN108735692B (zh) 半导体装置
JP2001156219A (ja) 半導体装置
JP5863602B2 (ja) 電力用半導体装置
JP2003086737A (ja) 半導体装置
KR102228945B1 (ko) 반도체 패키지 및 이의 제조방법
JP2000323593A (ja) 半導体装置
US10497586B2 (en) Semiconductor device and a method of manufacturing the same
JP7338204B2 (ja) 半導体装置
KR102199360B1 (ko) 반도체 패키지
JP5218009B2 (ja) 半導体装置
CN114512462A (zh) 半导体装置及其制造方法
JP2010287726A (ja) 半導体装置
JP7427927B2 (ja) 半導体装置
US20130256920A1 (en) Semiconductor device
JP6747304B2 (ja) 電力用半導体装置
JP4556732B2 (ja) 半導体装置及びその製造方法
CN115206905A (zh) 半导体装置和使用该半导体装置的半导体模块
JP2009164511A (ja) 半導体装置およびその製造方法
JP2002076259A (ja) パワーモジュール
JP3894749B2 (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination