CN114171585A - 一种ldmosfet、制备方法及芯片和电路 - Google Patents

一种ldmosfet、制备方法及芯片和电路 Download PDF

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CN114171585A
CN114171585A CN202210124399.9A CN202210124399A CN114171585A CN 114171585 A CN114171585 A CN 114171585A CN 202210124399 A CN202210124399 A CN 202210124399A CN 114171585 A CN114171585 A CN 114171585A
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drift region
voltage
type drift
ldmosfet
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CN114171585B (zh
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余山
赵东艳
王于波
陈燕宁
付振
刘芳
王凯
吴波
邓永峰
刘倩倩
郁文
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Core Kejian Technology Co Ltd
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    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
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    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

本发明实施例提供一种LDMOSFET、制备方法及芯片和电路,为了实现上述目的,本发明实施例提供一种LDMOSFET,包括:衬底,所述衬底上设有埋层;所述埋层上方设有外延层;所述外延层上方设有高压P型阱和高压N型阱;所述高压N型阱上方依次设有第一N型漂移区、P型体区和第二N型漂移区,其中,所述第一N型漂移区、P型体区和第二N型漂移区中的至少一者的上表面有凸起。该LDMOSFET不仅有效的缩小了器件的尺寸,还大大提升了器件的性能。

Description

一种LDMOSFET、制备方法及芯片和电路
技术领域
本发明涉及半导体领域,具体地涉及一种LDMOSFET、制备方法及芯片和电路。
背景技术
LDMOSFET器件常常被用于各种应用,例如汽车应用中。现有技术中常常通过降低LDMOSFET器件中的表面电场(RESURF)结构来防止高压施加于漏极造成击穿。但是现有LDMOSFET器件的结构是平面结构,在提高击穿电压与减少LDMOSFET面积,降低成本之间存在矛盾。
发明内容
本发明实施例的目的是提供一种LDMOSFET、制备方法及芯片和电路,该LDMOSFET不仅有效的缩小了器件的尺寸,还大大提升了器件的性能。
为了实现上述目的,本发明实施例提供一种LDMOSFET,包括:衬底,所述衬底上设有埋层;所述埋层上方设有外延层;所述外延层上方设有高压P型阱和高压N型阱;所述高压N型阱上方依次设有第一N型漂移区、P型体区和第二N型漂移区,其中,所述第一N型漂移区、P型体区和第二N型漂移区中的至少一者的上表面有凸起。
可选的,所述第一N型漂移区和第二N型漂移区在同一横向维度彼此分开。
可选的,所述第一N型漂移区呈反L型立体图形,所述P型体区呈凹型立体图形,所述第二N型漂移区呈L型立体图形,三者边缘处相接,共同组成一个新的凹形立体图形。
可选的,所述第一N型漂移区的外侧和第二N型漂移区的外侧均设有侧墙;所述侧墙为氧化物,用于隔离。
可选的,所述高压P型阱设于所述高压N型阱两侧,且所述高压N型阱的深度大于所述高压P型阱。
可选的,所述高压P型阱与所述高压N型阱相接的上侧设有场氧结构;所述场氧结构为凸起形状,用于隔离。
可选的,所述第一N型漂移区的深度、P型体区的深度和第二N型漂移区的深度均小于所述高压N型阱的深度。
可选的,所述第一N型漂移区和第二N型漂移区的最外层设有多晶硅。
可选的,所述衬底为P型衬底。
另一方面,本发明提供一种LDMOSFET的制备方法,包括:形成衬底,所述衬底上设有埋层;所述埋层上方形成外延层;所述外延层上方形成高压P型阱和高压N型阱;所述高压N型阱上方依次形成第一N型漂移区、P型体区和第二N型漂移区,其中,所述第一N型漂移区、P型体区和第二N型漂移区中的至少一者的上表面有凸起。
可选的,所述第一N型漂移区的外侧和第二N型漂移区的外侧均形成侧墙;所述侧墙为氧化物,用于隔离。
可选的,所述高压P型阱形成于所述高压N型阱两侧,且所述高压N型阱的深度大于所述高压P型阱。
可选的,所述高压P型阱与所述高压N型阱相接的上侧形成场氧结构;所述场氧结构为凸起形状,用于隔离。
另一方面,本发明还提供一种芯片,该芯片包括上述所述的LDMOSFET。
另一方面,本发明还提供一种电路,该电路包括上述所述的LDMOSFET。
本发明提供的一种LDMOSFET,包括:衬底,所述衬底上设有埋层;所述埋层上方设有外延层;所述外延层上方设有高压P型阱和高压N型阱;所述高压N型阱上方依次设有第一N型漂移区、P型体区和第二N型漂移区,其中,所述第一N型漂移区、P型体区和第二N型漂移区中的至少一者的上表面有凸起。所述LDMOSFET通过对第一N型漂移区、P型体区和第二N型漂移区中至少一者进行三维立体设计,缩小了器件的尺寸,增大了击穿电压,减小了表面电场。
本发明实施例的其它特征和优点将在随后的具体实施方式部分予以详细说明。
附图说明
附图是用来提供对本发明实施例的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本发明实施例,但并不构成对本发明实施例的限制。在附图中:
图1-图2是本发明的LDMOSFET的制备方法示意图。
附图标记说明
100-衬底;
101-埋层;
102-外延层;
103-高压N型阱;
104-第一N型漂移区;
105-P型体区;
106-第二N型漂移区;
201-高压P型阱;
202-多晶硅;
203-侧墙;
204-场氧结构。
具体实施方式
以下结合附图对本发明实施例的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明实施例,并不用于限制本发明实施例。
本发明提供了一种LDMOSFET,如图2所示,所述LDMOSFET包括:衬底100,所述衬底100优选为P型衬底。所述衬底100上设有埋层101;所述埋层101上方设有外延层102;所述外延层102上方设有高压P型阱201和高压N型阱103;所述高压N型阱103上方依次设有第一N型漂移区104、P型体区105和第二N型漂移区106,其中,所述第一N型漂移区104、P型体区105和第二N型漂移区106中的至少一者的上表面有凸起,如图2所示,所述第一N型漂移区104呈反L型立体图形,所述P型体区105呈凹型立体图形,所述第二N型漂移区106呈L型立体图形,三者边缘处相接,共同组成一个新的凹形立体图形,所述第一N型漂移区和第二N型漂移区在同一横向维度彼此分开。
所述第一N型漂移区104的外侧和第二N型漂移区106的外侧均设有侧墙203,所述侧墙203优选氧化物,具有隔离的作用,有效的减少了器件表面电场。
所述高压P型阱201设于所述高压N型阱103两侧,且所述高压N型阱103的深度大于所述高压P型阱201。所述高压P型阱201与所述高压N型阱103相接的上侧设有场氧结构204;所述场氧结构204为凸起形状,用于隔离。
所述第一N型漂移区104的深度、P型体区105的深度和第二N型漂移区106的深度均小于所述高压N型阱103的深度,这些漂移区都是在高压N型阱上制作,N型漂移区与P型漂移区可以不同深度所述第一N型漂移区104和第二N型漂移区106的最外层设有多晶硅202。
本发明还提供一种LDMOSFET的制备方法,包括:形成衬底100,所述衬底100上设有埋层101;所述埋层101上方形成外延层102;所述外延层102上方形成高压P型阱201和高压N型阱103;所述高压N型阱103上方依次形成第一N型漂移区104、P型体区105和第二N型漂移区106,其中,所述第一N型漂移区104、P型体区105和第二N型漂移区106中的至少一者的上表面有凸起。所述第一N型漂移区104的外侧和第二N型漂移区106的外侧均形成侧墙;所述侧墙为氧化物,用于隔离。所述高压P型阱201形成于所述高压N型阱103两侧,且所述高压N型阱103的深度大于所述高压P型阱201。所述高压P型阱201与所述高压N型阱103相接的上侧形成场氧结构204;所述场氧结构204为凸起形状,用于隔离。
具体的,图1-图2是本发明的LDMOSFET的制备方法示意图。如图1所示,先在P型衬底上制作N+埋层(BL),然后在埋层101添加外延层102(EPI),在外延层102上面离子注入,依次形成高压N型阱103(HVNW),高压P型阱201(HVPW),第一N型漂移区104,P型体区105,第二N型漂移区106;然后对第一N型漂移区104、P型体区105、第二N型漂移区106进行3D 沟道区光刻,具体包括涂胶、曝光、显影等,然后干法刻蚀P型体区105和第一N型漂移区104、第二N型漂移区106的部分硅,然后进行去胶清洗。
如图2所示,对图1所示的LDMOSFET进行其他工艺操作,包括:首先做场氧结构204(LOCOS),具体流程为:衬垫氧化层制作(PAD Oxide)、LPCVD SiN(氮化硅)、光刻、干法刻蚀SiN和PAD OX(衬垫氧化层)、场氧结构204(LOCOS)氧化,然后湿法去除SiN;其次为侧墙203的形成,包括:CVD SiO2, 然后干法刻蚀SiO2,形成侧墙203;再次光刻,干法刻蚀掉P型体区105(P-body)的侧墙203,形成单边NRF侧墙;然后,栅氧化、Gate Polysilicon Deposition(多晶硅栅淀积)、多晶硅202(Poly)扩散掺杂、Poly Gate(多晶硅栅)光刻、干法刻蚀多晶硅;最后形成源漏离子注入掺杂,形成源漏。
本发明的一种LDMOSFET,包括:包括:形成衬底100,所述衬底100上设有埋层101;所述埋层101上方形成外延层102;所述外延层102上方形成高压P型阱201和高压N型阱103;所述高压N型阱103上方依次形成第一N型漂移区104、P型体区105和第二N型漂移区106,其中,所述第一N型漂移区104、P型体区105和第二N型漂移区106中的至少一者的上表面有凸起。所述LDMOSFET通过对第一N型漂移区、P型体区和第二N型漂移区中至少一者进行三维立体设计,缩小了器件的尺寸,增大了击穿电压,减小了表面电场。
以上结合附图详细描述了本发明实施例的可选实施方式,但是,本发明实施例并不限于上述实施方式中的具体细节,在本发明实施例的技术构思范围内,可以对本发明实施例的技术方案进行多种简单变型,这些简单变型均属于本发明实施例的保护范围。
另外需要说明的是,在上述具体实施方式中所描述的各个具体技术特征,在不矛盾的情况下,可以通过任何合适的方式进行组合。为了避免不必要的重复,本发明实施例对各种可能的组合方式不再另行说明。
还需要说明的是,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上仅为本申请的实施例而已,并不用于限制本申请。对于本领域技术人员来说,本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等,均应包含在本申请的权利要求范围之内。

Claims (15)

1.一种LDMOSFET,其特征在于,包括:
衬底,所述衬底上设有埋层;
所述埋层上方设有外延层;
所述外延层上方设有高压P型阱和高压N型阱;
所述高压N型阱上方依次设有第一N型漂移区、P型体区和第二N型漂移区,其中,所述第一N型漂移区、P型体区和第二N型漂移区中的至少一者的上表面有凸起。
2.根据权利要求1所述的LDMOSFET,其特征在于,
所述第一N型漂移区和第二N型漂移区在同一横向维度彼此分开。
3.根据权利要求1所述的LDMOSFET,其特征在于,
所述第一N型漂移区呈反L型立体图形,所述P型体区呈凹型立体图形,所述第二N型漂移区呈L型立体图形,三者边缘处相接,共同组成一个新的凹形立体图形。
4.根据权利要求1所述的LDMOSFET,其特征在于,
所述第一N型漂移区的外侧和第二N型漂移区的外侧均设有侧墙;
所述侧墙为氧化物,用于隔离。
5.根据权利要求1所述的LDMOSFET,其特征在于,
所述高压P型阱设于所述高压N型阱两侧,且所述高压N型阱的深度大于所述高压P型阱。
6.根据权利要求1或5所述的LDMOSFET,其特征在于,
所述高压P型阱与所述高压N型阱相接的上侧设有场氧结构;
所述场氧结构为凸起形状,用于隔离。
7.根据权利要求1所述的LDMOSFET,其特征在于,
所述第一N型漂移区的深度、P型体区的深度和第二N型漂移区的深度均小于所述高压N型阱的深度。
8.根据权利要求1所述的LDMOSFET,其特征在于,
所述第一N型漂移区和第二N型漂移区的最外层设有多晶硅。
9.根据权利要求1所述的LDMOSFET,其特征在于,
所述衬底为P型衬底。
10.一种LDMOSFET的制备方法,特征在于,包括:
形成衬底,所述衬底上设有埋层;
所述埋层上方形成外延层;
所述外延层上方形成高压P型阱和高压N型阱;
所述高压N型阱上方依次形成第一N型漂移区、P型体区和第二N型漂移区,其中,所述第一N型漂移区、P型体区和第二N型漂移区中的至少一者的上表面有凸起。
11.根据权利要求10所述的制备方法,其特征在于,
所述第一N型漂移区的外侧和第二N型漂移区的外侧均形成侧墙;
所述侧墙为氧化物,用于隔离。
12.根据权利要求10所述的制备方法,其特征在于,
所述高压P型阱形成于所述高压N型阱两侧,且所述高压N型阱的深度大于所述高压P型阱。
13.根据权利要求10或12所述的制备方法,其特征在于,
所述高压P型阱与所述高压N型阱相接的上侧形成场氧结构;
所述场氧结构为凸起形状,用于隔离。
14.一种芯片,其特征在于,该芯片包括权利要求1-9中任一项所述的LDMOSFET。
15.一种电路,其特征在于,该电路包括权利要求1-9中任一项所述的LDMOSFET。
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