CN113130646B - 一种半导体器件及其制作方法 - Google Patents

一种半导体器件及其制作方法 Download PDF

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CN113130646B
CN113130646B CN201911395825.7A CN201911395825A CN113130646B CN 113130646 B CN113130646 B CN 113130646B CN 201911395825 A CN201911395825 A CN 201911395825A CN 113130646 B CN113130646 B CN 113130646B
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drift region
semiconductor substrate
region
semiconductor device
gate structure
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CN113130646A (zh
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何乃龙
张森
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CSMC Technologies Fab2 Co Ltd
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Abstract

本发明提供一种半导体器件及其制作方法，所述半导体器件包括:半导体衬底，所述半导体衬底中形成有第一漂移区；所述半导体衬底上形成有栅极结构，所述栅极结构的一部分覆盖所述第一漂移区的一部分；所述第一漂移区内形成有第一凹槽，所述第一凹槽底部的半导体衬底中形成有漏区。根据本发明提供的半导体器件及其制作方法，通过在漂移区内形成凹槽，并在凹槽底部的半导体衬底中形成漏区，纵向延长了漂移区的长度，提高了半导体器件的承受电压，同时减小了半导体器件的面积。

Description

一种半导体器件及其制作方法
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件及其制作方法。
背景技术
随着半导体技术的不断发展，横向双扩散金属氧化物半导体场效应晶体管(Lateral Double Diffused MOSFET，LDMOS)器件和延长漏极金属氧化物半导体(ExtendedDrain Metal Oxide Semiconductor,EDMOS)器件由于具有工作电压相对较高、工艺简易，易于同低压CMOS电路在工艺上兼容等特点而被广泛的应用。与普通MOS器件相比，LDMOS和EDMOS均在漏极有一个轻掺杂注入区，被称为漂移区。由于LDMOS和EDMOS通常用于功率电路，需要获得较大的输出功率，因此必须能承受较高的击穿电压。
目前LDMOS和EDMOS都是硅表面器件，作为设计特定工作电压档位的晶体管，得到一定耐压的同时，需要尽量降低晶体管的导通电阻，导通电阻主要由沟道(channel)+结型场效应管区(JFET)+漂移区(Drift)三部分组成，工作电压档位越高的器件，漂移区部分占整个导通电阻比例越高；但是耐压又是通过横向的漂移区来承载，一定耐压的晶体管漂移区长度是一定的，或者说有长度下限(硅耐压物理极限)，所以漂移区尺寸无法无限制的减小，即使工艺特征尺寸减小，但是耐压尺寸是无法减小的。
因此，有必要提出一种新的半导体器件，以解决上述问题。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
本发明还提供一种半导体器件，包括：
半导体衬底，所述半导体衬底中形成有第一漂移区；
所述半导体衬底上形成有栅极结构，所述栅极结构的一部分覆盖所述第一漂移区的一部分；
所述第一漂移区内形成有第一凹槽，所述第一凹槽底部的半导体衬底中形成有漏区。
进一步，所述半导体器件还包括：源区，所述源区与所述漏区分别设置在所述栅极结构的两侧。
进一步，所述源区设置在所述半导体衬底的表面。
进一步，所述半导体器件还包括：第二漂移区，所述第二漂移区位于所述半导体衬底中，所述第二漂移区与所述第一漂移区分别设置在所述栅极结构的两侧，所述栅极结构的一部分覆盖所述第二漂移区的一部分。
进一步，所述第二漂移区内形成有第二凹槽，所述第二凹槽底部的半导体衬底中形成有所述源区。
进一步，所述半导体器件还包括：隔离结构，所述隔离结构设置在所述漏区和所述源区的外侧。
进一步，所述隔离结构包括沟槽隔离结构或局部硅氧化隔离。
本发明提供一种半导体器件的制作方法，包括以下步骤：
提供半导体衬底，在所述半导体衬底中形成第一漂移区；
在所述半导体衬底上形成栅极结构，所述栅极结构的一部分覆盖所述第一漂移区的一部分；
蚀刻所述第一漂移区，以在所述第一漂移区内形成第一凹槽；
执行离子注入，以在所述第一凹槽底部的半导体衬底中形成漏区。
进一步，所述半导体器件的制作方法还包括：
执行离子注入，以在所述半导体衬底的表面形成源区。
进一步，所述半导体器件的制作方法还包括：
在所述半导体衬底中形成第二漂移区，所述第二漂移区与所述第一漂移区分别设置在所述栅极结构的两侧，所述栅极结构的一部分覆盖所述第二漂移区的一部分；
蚀刻所述第二漂移区，以在所述第二漂移区内形成第二凹槽；
执行离子注入，以在所述第二凹槽底部的半导体衬底中形成源区。
根据本发明提供的半导体器件及其制作方法，通过在漂移区内形成凹槽，并在凹槽底部的半导体衬底中形成漏区，纵向延长了漂移区的长度，提高了半导体器件的承受电压，同时减小了半导体器件的面积。
附图说明
通过结合附图对本发明实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显。附图用来提供对本发明实施例的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
附图中：
图1是根据现有技术的一种半导体器件的剖面图。
图2A是根据本发明示例性实施例的一种半导体器件的剖面图。
图2B是根据本发明示例性实施例的另一种半导体器件的剖面图。
图3示出了本发明示例性实施例的一种半导体器件的制作方法的示意性流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
现有技术中，如图1所示，晶体管的耐压是通过横向的漂移区来承载，一定耐压的晶体管漂移区长度是一定的，或者说有长度下限(硅耐压物理极限)，所以漂移区尺寸无法无限制的减小，即使工艺特征尺寸减小，但是耐压尺寸是无法减小的。
针对现有技术的不足，本发明提供了一种半导体器件及其制造方法。
参照图2A和图2B，其中，图2A是根据本发明示例性实施例的一种半导体器件的剖面图；图2B是根据本发明示例性实施例的另一种半导体器件的剖面图。
根据本发明实施例，参照图2A和图2B，对本发明实施例提供的半导体器件的结构进行描述。该半导体器件包括：
半导体衬底200，所述半导体衬底200中形成有第一漂移区204；
所述半导体衬底上形成有栅极结构207，所述栅极结构207的一部分覆盖所述第一漂移区204的一部分；
所述第一漂移区204内形成有第一凹槽，所述第一凹槽底部的半导体衬底中形成有漏区206。
示例性地，所述半导体器件包括LDMOS器件或EDMOS器件。
示例性地，半导体衬底200可以是以下所提到的材料中的至少一种：单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在本实施例中，所述半导体衬底200为P型硅衬底(P-sub)，其具体的掺杂浓度不受本发明限制，半导体衬底200可以通过外延生长形成，也可以为晶圆衬底。
示例性地，在半导体衬底200中还形成有隔离结构202。所述隔离结构202为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构，隔离结构将半导体衬底200分为不同的有源区，有源区中可以形成各种半导体器件，例如NMOS和PMOS等。在半导体衬底200中还形成有各种阱(well)结构。
示例性地，所述半导体衬底200中形成有阱区201。作为一个实例，在半导体衬底200中形成P型阱区(P-well)。
示例性地，在半导体衬底200中至少形成有第一漂移区(Drift)204。
在一个实施例中，仅在半导体衬底中形成有第一漂移区204，如图2B所示。
在另一个实施例中，在半导体衬底中形成有第一漂移区204和第二漂移区203，如图2A所示。
示例性地，半导体衬底200上形成有栅极结构207。栅极结构207包括自下而上依次层叠的栅极介电层、栅极材料层。栅极介电层包括氧化物层，例如二氧化硅(SiO2)层。栅极材料层包括多晶硅层、金属层、导电性金属氮化物层、导电性金属氧化物层和金属硅化物层中的一种或多种。在半导体衬底200上还形成有位于栅极结构207两侧且紧靠栅极结构207的侧墙结构。
在一个实施例中，如图2A所示，所述第二漂移区203与所述第一漂移区204分别设置在所述栅极结构207的两侧，所述栅极结构207的一部分覆盖所述第一漂移区204的一部分，且所述栅极结构207的一部分覆盖所述第二漂移区203的一部分。
在另一个实施例中，如图2B所示，所述栅极结构207的一部分覆盖所述第一漂移区204的一部分。
通过形成位于栅极结构207两侧的第一漂移区204和第二漂移区203，以形成对称晶体管，如图2A所示；而仅在栅极结构207一侧形成第一漂移区204，则可以形成不对称晶体管，如图2B所示。
示例性地，所述第一漂移区204内形成有第一凹槽，所述第一凹槽底部的半导体衬底200中形成有漏区206。
在一个实施例中，如图2B所示，所述第一漂移区204内形成有第一凹槽，所述第一凹槽底部的半导体衬底200中形成有漏区206。所述半导体衬底200的表面形成有源区205，所述源区205和所述漏区206分别设置在所述栅极结构207的两侧。
通过在第一漂移区204内形成第一凹槽，并在第一凹槽底部的半导体衬底200中形成漏区206，纵向延长了第一漂移区204的长度，提高了半导体器件的漏端的承受电压，同时减小了半导体器件的面积。
在另一个实施例中，如图2A所示，所述第一漂移区204内形成第一凹槽，所述第一凹槽底部的半导体衬底200中形成有漏区206；所述第二漂移区203内形成第二凹槽，所述第二凹槽底部的半导体衬底200中形成有源区205。
通过在第一漂移区204和第二漂移区203内分别形成第一凹槽和第二凹槽，并在第一凹槽底部的半导体衬底200中形成漏区206，在第二凹槽底部的半导体衬底200中形成源区205，纵向延长了第一漂移区204和第二漂移区203的长度，提高了半导体器件两端的承受电压，同时减小了半导体器件的面积。
参照图2A、2B和图3，其中，图2A是根据本发明示例性实施例的一种半导体器件的剖面图；图2B是根据本发明示例性实施例的另一种半导体器件的剖面图；图3示出了本发明示例性实施例的一种半导体器件的制作方法的示意性流程图。
本发明提供一种半导体器件的制备方法，如图3所示，该制备方法的主要步骤包括：
步骤S301：提供半导体衬底，在所述半导体衬底中形成第一漂移区；
步骤S302：在所述半导体衬底上形成栅极结构，所述栅极结构的一部分覆盖所述第一漂移区的一部分；
步骤S303：蚀刻所述第一漂移区，以在所述第一漂移区内形成第一凹槽；
步骤S304：执行离子注入，以在所述第一凹槽底部的半导体衬底中形成漏区。
本发明的半导体器件的制作方法具体包括以下步骤：
首先，执行步骤S101：提供半导体衬底200，在所述半导体衬底中形成第一漂移区204。
示例性地，所述半导体器件包括LDMOS器件或EDMOS器件。
示例性地，半导体衬底200可以是以下所提到的材料中的至少一种：单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在本实施例中，半导体衬底200为P型硅衬底(P-sub)，其具体的掺杂浓度不受本发明限制，半导体衬底200可以通过外延生长形成，也可以为晶圆衬底。
示例性地，在半导体衬底200中还形成有隔离结构202。所述隔离结构202为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构，隔离结构将半导体衬底200分为不同的有源区，有源区中可以形成各种半导体器件，例如NMOS和PMOS等。在半导体衬底200中还形成有各种阱(well)结构。
示例性地，所述半导体衬底200中形成有阱区201。
示例性地，采用阱注入工艺在半导体衬底200中形成阱区201。作为一个实例，采用标准的阱注入工艺在半导体衬底中形成P型阱区(P-well)，可以通过高能量注入工艺形成P型阱区，也可以通过低能量注入，搭配高温热退火过程形成P型阱区。
示例性地，在所述半导体衬底中形成第一漂移区204。
示例性地，在半导体衬底200中至少形成第一漂移区(Drift)204。在一个实施例中，仅在半导体衬底中形成第一漂移区204，如图2B所示。在另一个实施例中，在半导体衬底中形成第一漂移区204和第二漂移区203，如图2A所示。
示例性地，第一漂移区204和/或第二漂移区203位于半导体衬底200内，一般为轻掺杂区，对于N沟道晶体管，漂移区为N型掺杂。作为一个实例，首先在半导体衬底200上形成漂移区掩蔽层，具体地，漂移区掩蔽层为光刻胶层，然后通过曝光、显影工艺在光刻胶中形成开口图案，接着通过高能量注入工艺在开口区域形成第一漂移区204和/或第二漂移区203，也可以通过低能量注入，搭配高温热退火过程形成第一漂移区204和/或第二漂移区203。
接下来，执行步骤S102：在所述半导体衬底200上形成栅极结构207，所述栅极结构207的一部分覆盖所述第一漂移区204的一部分。
示例性地，在半导体衬底200上形成栅极结构207。栅极结构207包括自下而上依次层叠的栅极介电层、栅极材料层。栅极介电层包括氧化物层，例如二氧化硅(SiO2)层。栅极材料层包括多晶硅层、金属层、导电性金属氮化物层、导电性金属氧化物层和金属硅化物层中的一种或多种。在半导体衬底200上还形成有位于栅极结构207两侧且紧靠栅极结构207的侧墙结构。
在一个实施例中，如图2A所示，所述第二漂移区203与所述第一漂移区204分别设置在所述栅极结构207的两侧，所述栅极结构207的一部分覆盖所述第一漂移区204的一部分，且所述栅极结构207的一部分覆盖所述第二漂移区203的一部分。
在另一个实施例中，如图2B所示，所述栅极结构207的一部分覆盖所述第一漂移区204的一部分。
通过形成位于栅极结构207两侧的第一漂移区204和第二漂移区203，以形成对称晶体管，如图2A所示；而仅在栅极结构207一侧形成第一漂移区204，则可以形成不对称晶体管，如图2B所示。
接下来，执行步骤S303：蚀刻所述第一漂移区204，以在所述第一漂移区204内形成第一凹槽。
在一个实施例中，如图2B所示，仅蚀刻所述第一漂移区204，以在所述第一漂移区204内形成第一凹槽。
在另一个实施例中，如图2A所示，蚀刻所述第一漂移区204和第二漂移区203，以在所述第一漂移区204内形成第一凹槽，并且在所述第二漂移区203内形成第二凹槽。
蚀刻所述第一漂移区204和/或所述第二漂移区203可选用干法刻蚀或者湿法刻蚀的方法。示例性地，干法刻蚀工艺包括但不限于：反应离子刻蚀(RIE)、离子束刻蚀、等离子体刻蚀、激光烧蚀或者这些方法的任意组合。也可以使用单一的刻蚀方法，或者也可以使用多于一个的刻蚀方法。干法刻蚀的其源气体可以包括HBr和/或CF4气体。
接下来，执行步骤S304：执行离子注入，以在所述第一凹槽底部的半导体衬底200中形成漏区206。
示例性地，在形成所述漏区206的同时，还包括形成源区205的步骤。
在一个实施例中，如图2B所示，形成源区205的步骤包括：执行离子注入，以在所述半导体衬底200的表面形成源区205。
在另一个实施例中，如图2A所示，形成源区205的步骤包括：执行离子注入，以在所述第二凹槽底部的半导体衬底200中形成源区205。
作为一个实例，在半导体衬底200表面或第二凹槽底部的半导体衬底200中注入N型杂质形成源区205，在第一凹槽底部的半导体衬底200中注入N型杂质形成漏区206，源区205和漏区206的掺杂浓度可以相同，因此，二者可以同步地掺杂形成。
通过在第一漂移区204内形成第一凹槽，并在第一凹槽底部的半导体衬底200中形成漏区206，纵向延长了第一漂移区204的长度，提高了半导体器件的漏端的承受电压，同时减小了半导体器件的面积。
进一步，通过在第一漂移区204和第二漂移区203内分别形成第一凹槽和第二凹槽，并在第一凹槽底部的半导体衬底200中形成漏区206，在第二凹槽底部的半导体衬底200中形成源区205，纵向延长了第一漂移区204和第二漂移区203的长度，提高了半导体器件两端的承受电压，同时减小了半导体器件的面积。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (10)

1.一种半导体器件，其特征在于，包括：
半导体衬底，所述半导体衬底中形成有第一漂移区；
所述半导体衬底上形成有栅极结构，所述栅极结构的一部分覆盖所述第一漂移区的一部分；
所述第一漂移区内形成有第一凹槽，所述第一凹槽的整个底部的半导体衬底中形成有漏区。
2.如权利要求1所述的半导体器件，其特征在于，还包括：
源区，所述源区与所述漏区分别设置在所述栅极结构的两侧。
3.如权利要求1所述的半导体器件，其特征在于，源区设置在所述半导体衬底的表面。
4.如权利要求2所述的半导体器件，其特征在于，还包括：
第二漂移区，所述第二漂移区位于所述半导体衬底中，所述第二漂移区与所述第一漂移区分别设置在所述栅极结构的两侧，所述栅极结构的一部分覆盖所述第二漂移区的一部分。
5.如权利要求4所述的半导体器件，其特征在于，所述第二漂移区内形成有第二凹槽，所述第二凹槽底部的半导体衬底中形成有所述源区。
6.如权利要求2所述的半导体器件，其特征在于，还包括：
隔离结构，所述隔离结构设置在所述漏区和所述源区的外侧。
7.如权利要求6所述的半导体器件，其特征在于，所述隔离结构包括沟槽隔离结构或局部硅氧化隔离。
8.一种半导体器件的制作方法，其特征在于，包括以下步骤：
提供半导体衬底，在所述半导体衬底中形成第一漂移区；
在所述半导体衬底上形成栅极结构，所述栅极结构的一部分覆盖所述第一漂移区的一部分；
蚀刻所述第一漂移区，以在所述第一漂移区内形成第一凹槽；
执行离子注入，以在所述第一凹槽的整个底部的半导体衬底中形成漏区。
9.如权利要求8所述的制作方法，其特征在于，还包括：
执行离子注入，以在所述半导体衬底的表面形成源区。
10.如权利要求8所述的制作方法，其特征在于，还包括：
在所述半导体衬底中形成第二漂移区，所述第二漂移区与所述第一漂移区分别设置在所述栅极结构的两侧，所述栅极结构的一部分覆盖所述第二漂移区的一部分；
蚀刻所述第二漂移区，以在所述第二漂移区内形成第二凹槽；
执行离子注入，以在所述第二凹槽底部的半导体衬底中形成源区。
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