CN114242777A - 一种ldmosfet、制备方法及芯片和电路 - Google Patents
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Abstract
本发明实施例提供一种LDMOSFET、制备方法及芯片和电路,所述LDMOSFET包括:衬底,所述衬底上设有埋层;所述埋层上方设有外延层;所述外延层上方设有高压N型阱;所述高压N型阱上方依次设有第一N型漂移区、P型体区和第二N型漂移区;所述P型体区的中间设有间隙,所述间隙的深度小于所述P型体区的深度。所述LDMOSFET不仅有效的缩小了器件的尺寸,还大大提升了器件的性能。
Description
技术领域
本发明涉及半导体领域,具体地涉及一种LDMOSFET、制备方法及芯片和电路。
背景技术
LDMOSFET器件常常被用于各种应用,例如汽车应用中。现有技术中常常通过降低LDMOSFET器件中的表面电场(RESURF)结构来防止高压施加于漏极造成击穿,但是对最高击穿电压的提高不明显。
发明内容
本发明实施例的目的是提供一种LDMOSFET、制备方法及芯片和电路,该LDMOSFET至少解决现有技术的上述部分问题。
本发明的发明人经过研究发现,现有的LDMOSFET最高击穿电压提高不明显的主要原因是,LDMOSFET工艺是平面型的,即器件沟道、源、漏在一个平面,这样限制了其最大击穿电压,并且还造成占用硅片面积较大的问题。
为了实现上述目的,本发明实施例提供一种LDMOSFET,包括:衬底,所述衬底上设有埋层;所述埋层上方设有外延层;所述外延层上方设有高压N型阱;所述高压N型阱上方依次设有第一N型漂移区、P型体区和第二N型漂移区;所述P型体区的中间设有间隙,所述间隙的深度小于所述P型体区的深度。
可选的,所述间隙的深度小于所述第一N型漂移区的深度、并且小于第二N型漂移区的深度。
可选的,所述第一N型漂移区和第二N型漂移区上均设有隔离层和第一高掺杂N离子。
可选的,所述P型体区的上方设有第二高掺杂N离子。
可选的,所述第一N型漂移区的深度和第二N型漂移区的深度均小于所述P型体区的深度。
可选的,所述LDMOSFET的上方设有多晶硅。
可选的,所述衬底为P型衬底。
另一方面,本发明提供一种LDMOSFET的制备方法,包括:形成衬底,所述衬底上设有埋层;所述埋层上方形成外延层;所述外延层上方形成高压N型阱;所述高压N型阱上方依次形成第一N型漂移区、P型体区和第二N型漂移区;所述P型体区的中间形成间隙,所述间隙的深度小于所述P型体区的深度。
可选的,所述间隙的深度小于所述第一N型漂移区的深度、并且小于第二N型漂移区的深度。
可选的,所述第一N型漂移区和第二N型漂移区上均形成隔离层和第一高掺杂N离子。
可选的,所述P型体区的上方形成第二高掺杂N离子。
可选的,所述第一N型漂移区的深度和第二N型漂移区的深度均小于所述P型体区的深度。
另一方面,本发明提供一种芯片,该芯片包括上述所述的LDMOSFET。
另一方面,本发明提供一种电路,该电路包括上述所述的LDMOSFET。
本发明提供的一种LDMOSFET,包括:衬底,所述衬底上设有埋层;所述埋层上方设有外延层;所述外延层上方设有高压N型阱;所述高压N型阱上方依次设有第一N型漂移区、P型体区和第二N型漂移区;所述P型体区的中间设有间隙,所述间隙的深度小于所述P型体区的深度。所述LDMOSFET通过在P型体区的中间设置间隙,提高了器件的击穿电压。
本发明实施例的其它特征和优点将在随后的具体实施方式部分予以详细说明。
附图说明
附图是用来提供对本发明实施例的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本发明实施例,但并不构成对本发明实施例的限制。在附图中:
图1-图2是本发明的一种LDMOSFET的制备方法的示意图。
附图标记说明
100-衬底;
101-埋层;
102-外延层;
103-高压N型阱;
104-第一N型漂移区;
105-P型体区;
106-第二N型漂移区;
201-场氧结构;
202-多晶硅。
具体实施方式
以下结合附图对本发明实施例的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明实施例,并不用于限制本发明实施例。
本发明提供了一种LDMOSFET,如图2所示,所述LDMOSFET包括:衬底100,所述衬底优选为P型衬底,所述衬底100上设有埋层101;所述埋层101上方设有外延层102;所述外延层102上方设有高压N型阱103;所述高压N型阱103上方依次设有第一N型漂移区104、P型体区105和第二N型漂移区106;所述P型体区105的中间设有间隙,所述间隙的深度小于所述P型体区105的深度。所述间隙的深度小于所述第一N型漂移区104的深度,并且小于第二N型漂移区106的深度。所述第一N型漂移区104和第二N型漂移区106上均设有隔离层和第一高掺杂N离子(N+);所述P型体区的上方设有第二高掺杂N离子(N+)。所述第一N型漂移区104的深度和第二N型漂移区106的深度均小于所述P型体区105的深度。所述LDMOSFET的上方设有多晶硅202。所述间隙的宽度和深度根据具体的LDMOSFET的击穿电压而定,具体的,所述间隙使得所述P型体区105的中间形成一个栅电极,用于承受一部分击穿电压,使得击穿电压不能直接流向第二高掺杂N离子(N+),起到了很好的隔离击穿电压的效果。
本发明还提供了一种LDMOSFET的制备方法,包括:形成衬底100,所述衬底100上设有埋层101;所述埋层101上方形成外延层102;所述外延层102上方形成高压N型阱103;所述高压N型阱103上方依次形成第一N型漂移区104、P型体区105和第二N型漂移区106;所述P型体区105的中间形成间隙,所述间隙的深度小于所述P型体区105的深度。所述间隙的深度小于所述第一N型漂移区104的深度、并且小于第二N型漂移区106的深度。所述第一N型漂移区104和第二N型漂移区106上均形成隔离层和第一高掺杂N离子(N+);所述P型体区105的上方形成第二高掺杂N离子(N+)。所述第一N型漂移区104的深度和第二N型漂移区106的深度均小于所述P型体区105的深度。
图1-图2是本发明的一种LDMOSFET的制备方法的示意图,具体的,如图1所示,在P型衬底上制作N+埋层(BL),然后添加外延层102(EPI),在外延层上面进行离子注入,分布形成高压N型阱103(HVNW)、第一N型漂移区104、P型体区105(P-BODY)及第二N型漂移区106;然后对P型体区105(P-BODY)进行光刻操作,最后干法刻蚀P型体区105(P-BODY)的部分硅及对所述LDMOSFET进行去胶清洗。
如图2所示,接下来对图1的器件进行常规工艺制作(STI),完成后,光刻打开P型体区105(P-BODY),湿法刻蚀在P型体区105(P-BODY)槽里面的SiO2,然后栅氧化,LPCVDPolysilicon(多晶硅), Polysilicon(多晶硅)掺杂,栅电极和场板光刻,干法刻蚀后形成栅电极和场板,然后离子注入Arsenic(砷元素),形成LDMOSFET的源极和漏极。
本发明提供的LDMOSFET包括:衬底100,所述衬底100上设有埋层101;所述埋层101上方设有外延层102;所述外延层102上方设有高压N型阱103;所述高压N型阱103上方依次设有第一N型漂移区104、P型体区105和第二N型漂移区106;所述P型体区105的中间设有间隙,所述间隙的深度小于所述P型体区105的深度。所述LDMOSFET通过在P型体区105的中间设置间隙,使得所述P型体区105的中间形成一个栅电极,用于承受一部分击穿电压,使得击穿电压不能直接流向第二高掺杂N离子(N+),起到了很好的隔离击穿电压的效果,提高了器件的击穿电压。
以上结合附图详细描述了本发明实施例的可选实施方式,但是,本发明实施例并不限于上述实施方式中的具体细节,在本发明实施例的技术构思范围内,可以对本发明实施例的技术方案进行多种简单变型,这些简单变型均属于本发明实施例的保护范围。
另外需要说明的是,在上述具体实施方式中所描述的各个具体技术特征,在不矛盾的情况下,可以通过任何合适的方式进行组合。为了避免不必要的重复,本发明实施例对各种可能的组合方式不再另行说明。
还需要说明的是,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上仅为本申请的实施例而已,并不用于限制本申请。对于本领域技术人员来说,本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等,均应包含在本申请的权利要求范围之内。
Claims (14)
1.一种LDMOSFET,其特征在于,包括:
衬底,所述衬底上设有埋层;
所述埋层上方设有外延层;
所述外延层上方设有高压N型阱;
所述高压N型阱上方依次设有第一N型漂移区、P型体区和第二N型漂移区;
所述P型体区的中间设有间隙,所述间隙的深度小于所述P型体区的深度。
2.根据权利要求1所述的LDMOSFET,其特征在于,
所述间隙的深度小于所述第一N型漂移区的深度、并且小于第二N型漂移区的深度。
3.根据权利要求1所述的LDMOSFET,其特征在于,
所述第一N型漂移区和第二N型漂移区上均设有隔离层和第一高掺杂N离子。
4.根据权利要求1所述的LDMOSFET,其特征在于,
所述P型体区的上方设有第二高掺杂N离子。
5.根据权利要求1所述的LDMOSFET,其特征在于,
所述第一N型漂移区的深度和第二N型漂移区的深度均小于所述P型体区的深度。
6.根据权利要求1所述的LDMOSFET,其特征在于,
所述LDMOSFET的上方设有多晶硅。
7.根据权利要求1所述的LDMOSFET,其特征在于,
所述衬底为P型衬底。
8.一种LDMOSFET的制备方法,特征在于,包括:
形成衬底,所述衬底上设有埋层;
所述埋层上方形成外延层;
所述外延层上方形成高压N型阱;
所述高压N型阱上方依次形成第一N型漂移区、P型体区和第二N型漂移区;
所述P型体区的中间形成间隙,所述间隙的深度小于所述P型体区的深度。
9.根据权利要求8所述的制备方法,其特征在于,
所述间隙的深度小于所述第一N型漂移区的深度、并且小于第二N型漂移区的深度。
10.根据权利要求8所述的制备方法,其特征在于,
所述第一N型漂移区和第二N型漂移区上均形成隔离层和第一高掺杂N离子。
11.根据权利要求8所述的制备方法,其特征在于,
所述P型体区的上方形成第二高掺杂N离子。
12.根据权利要求8所述的制备方法,其特征在于,
所述第一N型漂移区的深度和第二N型漂移区的深度均小于所述P型体区的深度。
13.一种芯片,其特征在于,该芯片包括权利要求1-7中任一项所述的LDMOSFET。
14.一种电路,其特征在于,该电路包括权利要求1-7中任一项所述的LDMOSFET。
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