CN114038915A - 半导体功率器件及其制备方法 - Google Patents
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Abstract
本发明公开了一种半导体功率器件及其制备方法,包括自下而上依次设置的衬底、氧化层和介质层,衬底上表面内离子注入形成间隔设置的阱区和漂移区,相邻阱区和漂移区之间设置有沟槽,该沟槽靠近阱区的一内侧设置有栅氧化层,该沟槽的其余内侧设置有场氧化层,栅氧化层和场氧化层的内侧填充有与衬底表面齐平的多晶硅。本发明结合了LDMOS和SGT的优点,实现低导通电阻,高耐压,易集成,占用芯片面积小,可应用在BCD技术领域。
Description
技术领域
本发明涉及一种半导体器件,尤其涉及一种半导体功率器件及其制备方法。
背景技术
半导体功率器件按结构可分为横向导电型功率器件和垂直导电型功率器件;横向功率器件以LDMOS(Laterally-diffused metal-oxide semiconductor)为主,而垂直功率器件以VDMOS(Vertical-diffused metal-oxide semiconductor),SGT MOS(shield gatetrench或splitgatetrench MOS),IGBT(Insulated Gate Bipolar Transistor:绝缘栅双极型晶体管)为主。半导体功率器件始终在追求更高耐压,更低的单位面积导通电阻,减少芯片面积。
LDMOS的优点是易于集成,和CMOS工艺兼容,广泛应用于BCD技术。其缺点也很明显,要获得较高的击穿电压,主要通过延长漂移区,占用很大的芯片面积,尽管引入RESURF技术(Reduce Surface Field降低表面电场),该缺点仍然存在,LDMOS结构如图1所示。
SGT的优点主要是通过纵向结构,大大减小芯片占用面积,并通过纵向场氧化层设置,利用电荷平衡机理,可保证一定耐压下提高漂移区的浓度,从而降低器件导通电阻。但是缺点在于工艺复杂,制造成本高;其纵向结构使SGT MOS难以和CMOS工艺兼容,因此不易集成,SGT结构见图2。
因此,亟待解决上述问题。
发明内容
发明目的:本发明的第一目的是提供一种结合LDMOS和SGT的优点,实现低导通电阻、高耐压、易集成和占用芯片面积小,可应用在BCD技术领域的半导体功率器件。
本发明的第二目的是提供该半导体功率器件的制备方法。
技术方案:为实现以上目的,本发明公开了一种半导体功率器件包括自下而上依次设置的衬底、氧化层和介质层,衬底上表面内离子注入形成间隔设置的阱区和漂移区,相邻阱区和漂移区之间设置有沟槽,该沟槽靠近阱区的一内侧设置有栅氧化层,该沟槽的其余内侧设置有场氧化层,栅氧化层和场氧化层的内侧填充有与衬底表面齐平的多晶硅。
其中,所述阱区上表面设有栅氧化层。
优选的,所述介质层上设置有接触孔沟槽,接触孔沟槽内淀积有分别形成源极、栅极和漏极的接触金属。
再者,所述衬底为P型衬底,阱区为P型阱区,漂移区为N型漂移区。
进一步,所述沟槽底部注入N型离子形成轻掺杂区。
优选的,所述阱区和漂移区上表面均注入N型离子形成重掺杂区。
再者,所述衬底为N型衬底,阱区为N型阱区,漂移区为P型漂移区。
进一步,所述沟槽底部注入P型离子形成轻掺杂区。
优选的,所述阱区和漂移区上表面均注入P型离子形成重掺杂区。
本发明一种半导体功率器件的制备方法,包括如下步骤:
(1)、在衬底表面生长一层氧化层,并注入离子形成漂移区;
(2)、在氧化层上淀积一层氮化硅形成掩膜层;
(3)、进行沟槽光刻,先刻蚀掩膜层和氧化层形成刻蚀窗口,然后去除光刻胶;
(4)、对刻蚀窗口进行沟槽刻蚀,在掩蔽层的掩蔽作用下形成沟槽;
(5)、在沟槽表面生长一层牺牲氧化层,然后在沟槽底部注入N型离子形成轻掺杂区;
(6)、去除牺牲氧化层,然后在沟槽内侧表面生长场氧化层;
(7)、在掩膜层表面和沟槽内填充氮化硅;
(8)、将氮化硅刻蚀至与衬底硅表面齐平;
(9)、涂覆光刻胶,进行场氧化层光刻,离子注入衬底形成阱区;
(10)、去除阱区上表面以及沟槽靠近阱区一侧的场氧化层;
(11)、去除光刻胶,并去除沟槽内氮化硅,然后只在阱区表面生长栅氧化层;
(12)、在沟槽内填充多晶硅并刻蚀至与衬底硅表面齐平;
(13)、在阱区和漂移区上表面均离子注入形成重掺杂区;
(14)、淀积介质层,然后接触孔光刻,再在接触孔沟槽内淀积接触金属形成源极、栅极和漏极电极。
有益效果:与现有技术相比,本发明具有以下显著优点:
(1)、本发明采用纵向场氧化层设置,利用电荷平衡机理,可保证一定耐压下,提高漂移区的浓度,从而降低器件导通电阻;
(2)、本发明通过沟槽栅结构,纵向沟道和纵向栅极场氧化层设置,纵向P-N结构,减少小元胞漂移区尺寸,缩小元胞尺寸,从而大大减少芯片占用面积;
(3)、本发明的源极和漏极在晶圆同一侧,属于平面结构,相对于SGT的垂直结构,工艺复杂度较低,易和CMOS工艺兼容,易集成,在BCD集成领域有很大发挥空间。
附图说明
图1为本发明中LDMOS器件的结构示意图;
图2为本发明中SGT器件的结构示意图;
图3为本发明实施例1中生长氧化层的示意图;
图4为本发明实施例1中淀积掩膜层的示意图;
图5为本发明实施例1中沟槽光刻的示意图;
图6为本发明实施例1中沟槽刻蚀的示意图;
图7为本发明实施例1中生长牺牲氧化层的示意图;
图8为本发明实施例1中生长场氧化层的示意图;
图9为本发明实施例1中填充氮化硅的示意图;
图10为本发明实施例1中场氧化层光刻的示意图;
图11为本发明实施例1中去除部分场氧化层的示意图;
图12为本发明实施例1中接触孔淀积金属的示意图;
图13为本发明实施例1中生长栅氧化层的示意图;
图14为本发明实施例1中填充多晶硅的示意图;
图15为本发明实施例1中离子注入形成轻掺杂区的示意图;
图16为本发明实施例1中形成源极、栅极和漏极的示意图;
图17为本发明实施例2的结构示意图。
具体实施方式
下面结合附图对本发明的技术方案作进一步说明。
实施例1
将以NMOS为例,本发明一种半导体功率器件包括衬底1、氧化层2、介质层3、阱区4、漂移区5、沟槽6、栅氧化层7、场氧化层8、多晶硅9、源极10、栅极11、漏极12、轻掺杂区13和重掺杂区14,其中衬底1为P型衬底,阱区4为P型阱区,漂移区5为N型漂移区,沟槽6底部注入N型离子形成轻掺杂区13,阱区4和漂移区5上表面均注入N型离子形成重掺杂区14。
本发明中衬底1、氧化层2和介质层3自下而上依次设置,P型衬底上表面内离子注入形成P型阱区,P型衬底上表面内离子注入形成N型漂移区,P型阱区和N型漂移区间隔设置,相邻P型阱区和N型漂移区之间设置有沟槽,该沟槽6靠近阱区的一内侧设置有栅氧化层7,同时在阱区4上表面设有栅氧化层7,栅氧化层7包覆在阱区4的两侧和上表面;该沟槽的其余内侧设置有场氧化层8,栅氧化层7和场氧化层8两者连成一体,但栅氧化层7和场氧化层8两者形成工艺和厚度均不同,场氧化层8比栅氧化层7厚度大;沟槽内在栅氧化层7和场氧化层8的内侧填充有与衬底表面齐平的多晶硅9。
本发明中介质层3上设置有接触孔沟槽,接触孔沟槽内淀积有分别形成源极10、栅极11和漏极12的接触金属;本发明中源级10和漏极12设置在同一侧。本发明结合了LDMOS和SGT的优点,实现低导通电阻,高耐压,易集成,占用芯片面积小,可应用在BCD技术领域。
以NMOS为例,本发明一种半导体功率器件的制备方法,包括如下步骤:
(1)、在P型衬底表面生长一层氧化层,氧化层厚度为300A~1000A,并注入N型离子形成N型漂移区,如图3所示;
(2)、在氧化层上淀积一层氮化硅形成掩膜层,氮化硅的厚度为800A~1200A,如图4所示;
(3)、进行沟槽光刻,先刻蚀掩膜层和氧化层形成刻蚀窗口,然后去除光刻胶,如图5所示;
(4)、对刻蚀窗口进行沟槽刻蚀,在掩蔽层的掩蔽作用下形成沟槽,沟槽深度为1.5um~3um,如图6所示;
(5)、在沟槽表面生长一层牺牲氧化层,牺牲氧化层的厚度为250A~350A,然后在沟槽底部注入N型离子形成轻掺杂区,如图7所示;
(6)、去除牺牲氧化层,然后在沟槽内侧表面生长场氧化层,场氧化层厚度为1000A~2000A,如图8所示;
(7)、在掩膜层表面和沟槽内填充氮化硅,如图9所示;
(8)、将氮化硅刻蚀至与衬底硅表面齐平,如图10所示;
(9)、涂覆光刻胶,进行场氧化层光刻,P型离子注入衬底形成P型阱区,如图11所示;
(10)、去除阱区上表面以及沟槽靠近P型阱区一侧的场氧化层,如图12所示;
(11)、去除光刻胶,并去除沟槽内氮化硅,然后只在P型阱区表面生长栅氧化层,栅氧化层的厚度为200A~1000A,如图13所示;
(12)、在沟槽内填充多晶硅并刻蚀至与衬底硅表面齐平,如图14所示;
(13)、在P型阱区和N型漂移区上表面均进行N型离子注入形成重掺杂区,如图15所示;
(14)、淀积介质层,然后接触孔光刻,再在接触孔沟槽内淀积接触金属形成源极、栅极和漏极电极,如图16所示。
实施例2
将以PMOS为例,本发明一种半导体功率器件包括衬底1、氧化层2、介质层3、阱区4、漂移区5、沟槽6、栅氧化层7、场氧化层8、多晶硅9、源极10、栅极11、漏极12、轻掺杂区13和重掺杂区14,其中衬底1为N型衬底,阱区4为N型阱区,漂移区5为P型漂移区,沟槽6底部注入P型离子形成轻掺杂区13,阱区4和漂移区5上表面均注入P型离子形成重掺杂区14。
本发明中衬底1、氧化层2和介质层3自下而上依次设置,N型衬底上表面内离子注入形成N型阱区,N型衬底上表面内离子注入形成P型漂移区,N型阱区和P型漂移区间隔设置,相邻N型阱区和P型漂移区之间设置有沟槽,该沟槽6靠近阱区的一内侧设置有栅氧化层7,同时在阱区4上表面设有栅氧化层7,栅氧化层7包覆在阱区4的两侧和上表面;该沟槽的其余内侧设置有场氧化层8,栅氧化层7和场氧化层8两者连成一体,但栅氧化层7和场氧化层8两者形成工艺和厚度均不同;沟槽内在栅氧化层7和场氧化层8的内侧填充有与衬底表面齐平的多晶硅9。
本发明中介质层3上设置有接触孔沟槽,接触孔沟槽内淀积有分别形成源极10、栅极11和漏极12的接触金属;本发明中源级10和漏极12设置在同一侧。
以PMOS为例,本发明一种半导体功率器件的制备方法,包括如下步骤:
(1)、在N型衬底表面生长一层氧化层,氧化层厚度为300A~1000A,并注入P型离子形成P型漂移区;
(2)、在氧化层上淀积一层氮化硅形成掩膜层,氮化硅的厚度为800A~1200A;
(3)、进行沟槽光刻,先刻蚀掩膜层和氧化层形成刻蚀窗口,然后去除光刻胶,如图5所示;
(4)、对刻蚀窗口进行沟槽刻蚀,在掩蔽层的掩蔽作用下形成沟槽,沟槽深度为1.5um~3um;
(5)、在沟槽表面生长一层牺牲氧化层,牺牲氧化层的厚度为250A~350A,然后在沟槽底部注入P型离子形成轻掺杂区,如图7所示;
(6)、去除牺牲氧化层,然后在沟槽内侧表面生长场氧化层,场氧化层厚度为1000A~2000A;
(7)、在掩膜层表面和沟槽内填充氮化硅;
(8)、将氮化硅刻蚀至与衬底硅表面齐平;
(9)、涂覆光刻胶,场氧化层光刻,N型离子注入衬底形成N型阱区;
(10)、去除阱区上表面以及沟槽靠近N型阱区一侧的场氧化层;
(11)、去除光刻胶,并去除沟槽内氮化硅,然后只在N型阱区表面生长栅氧化层,栅氧化层的厚度为200A~1000A;
(12)、在沟槽内填充多晶硅并刻蚀至与衬底硅表面齐平;
(13)、在N型阱区和P型漂移区上表面均进行P型离子注入形成重掺杂区;
(14)、淀积介质层,然后接触孔光刻,再在接触孔沟槽内淀积接触金属形成源极、栅极和漏极电极。
Claims (10)
1.一种半导体功率器件,其特征在于:包括自下而上依次设置的衬底(1)、氧化层(2)和介质层(3),衬底上表面内离子注入形成间隔设置的阱区(4)和漂移区(5),相邻阱区(4)和漂移区(5)之间设置有沟槽(6),该沟槽(6)靠近阱区的一内侧设置有栅氧化层(7),该沟槽的其余内侧设置有场氧化层(8),栅氧化层(7)和场氧化层(8)的内侧填充有与衬底表面齐平的多晶硅(9)。
2.根据权利要求1所述的半导体功率器件,其特征在于:所述阱区(4)上表面设有栅氧化层(7)。
3.根据权利要求1所述的半导体功率器件,其特征在于:所述介质层(3)上设置有接触孔沟槽,接触孔沟槽内淀积有分别形成源极(10)、栅极(11)和漏极(12)的接触金属。
4.根据权利要求1所述的半导体功率器件,其特征在于:所述衬底(1)为P型衬底,阱区(4)为P型阱区,漂移区(5)为N型漂移区。
5.根据权利要求4所述的半导体功率器件,其特征在于:所述沟槽(6)底部注入N型离子形成轻掺杂区(13)。
6.根据权利要求4所述的半导体功率器件,其特征在于:所述阱区(4)和漂移区(5)上表面均注入N型离子形成重掺杂区(14)。
7.根据权利要求1所述的半导体功率器件,其特征在于:所述衬底(1)为N型衬底,阱区(4)为N型阱区,漂移区(5)为P型漂移区。
8.根据权利要求7所述的半导体功率器件,其特征在于:所述沟槽(6)底部注入P型离子形成轻掺杂区(13)。
9.根据权利要求7所述的半导体功率器件,其特征在于:所述阱区(4)和漂移区(5)上表面均注入P型离子形成重掺杂区(14)。
10.根据权利要求1至9任一所述的一种半导体功率器件的制备方法,其特征在于,包括如下步骤:
(1)、在衬底(1)表面生长一层氧化层(2),并注入离子形成漂移区(5);
(2)、在氧化层(2)上淀积一层氮化硅(15)形成掩膜层;
(3)、进行沟槽光刻,先刻蚀掩膜层和氧化层形成刻蚀窗口(16),然后去除光刻胶;
(4)、对刻蚀窗口进行沟槽刻蚀,在掩蔽层的掩蔽作用下形成沟槽(6);
(5)、在沟槽表面生长一层牺牲氧化层(17),然后在沟槽底部注入N型离子形成轻掺杂区(13);
(6)、去除牺牲氧化层,然后在沟槽内侧表面生长场氧化层(8);
(7)、在掩膜层表面和沟槽内填充氮化硅(15);
(8)、将氮化硅刻蚀至与衬底硅表面齐平;
(9)、涂覆光刻胶(18),进行场氧化层光刻,离子注入衬底形成阱区(4);
(10)、去除阱区上表面以及沟槽靠近阱区一侧的场氧化层(7);
(11)、去除光刻胶,并去除沟槽内氮化硅,然后只在阱区表面生长栅氧化层(7);
(12)、在沟槽内填充多晶硅(9)并刻蚀至与衬底硅表面齐平;
(13)、在阱区(4)和漂移区(5)上表面均离子注入形成重掺杂区(14);
(14)、淀积介质层,然后接触孔光刻,再在接触孔沟槽内淀积接触金属形成源极(10)、栅极(11)和漏极(12)电极。
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