WO2023066096A1 - 超级结器件及其制造方法 - Google Patents

超级结器件及其制造方法 Download PDF

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WO2023066096A1
WO2023066096A1 PCT/CN2022/124750 CN2022124750W WO2023066096A1 WO 2023066096 A1 WO2023066096 A1 WO 2023066096A1 CN 2022124750 W CN2022124750 W CN 2022124750W WO 2023066096 A1 WO2023066096 A1 WO 2023066096A1
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type
gate
region
super junction
trench
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PCT/CN2022/124750
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French (fr)
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李�昊
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上海华虹宏力半导体制造有限公司
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device.
  • the invention also relates to a manufacturing method of a super junction device.
  • the super junction is composed of alternately arranged P-type thin layers also called P-type pillars (Pillar) and N-type thin layers also called N-type pillars formed in the semiconductor substrate.
  • Devices using super junctions are super junction devices such as super junction devices.
  • junction MOSFET junction MOSFET.
  • the internal reduced surface electric field (Resurf) technology using P-type thin layer and N-type thin layer charge balance can increase the reverse breakdown voltage of the device while maintaining a small on-resistance.
  • the pillar structure of the PN interval of the super junction is the biggest feature of the super junction.
  • the latter method is to make a super junction device through a trench process. It is necessary to etch a trench with a certain depth and width on the N-type doped epitaxial layer on the surface of a semiconductor substrate such as a silicon substrate, and then use epitaxial filling (EPI Filling ) way to fill the etched trenches with P-type doped silicon epitaxy.
  • the super junction is made by deep trench, that is, super junction trench etching and epitaxial filling process, due to the influence of epitaxial layer steps such as silicon steps (Step silicon) near the surface of the super junction trench, it is easy to make super junctions in the bulk near the surface. Defects form in the silicon, resulting in leakage failure of the device.
  • epitaxial layer steps such as silicon steps (Step silicon) near the surface of the super junction trench
  • a P-type body region is formed in a super junction device such as a super junction MOSFET, and the P-type body region is formed by ion implantation and annealing after the trench filling of the super junction is completed, and the bottom of the P-type body region It is an N-type drift region corresponding to the N-type column, and a body diode is formed between the P-type body region and the N-type drift region.
  • the surface of the P-type body region is usually used to form a channel, and specifically the surface of the P-type body region covered by the gate structure is used to form a channel.
  • the gate structure Due to the complexity of the manufacturing process of the P-type pillar and N-type pillar of the super junction pillar structure, the gate structure is usually placed after the manufacture of the pillar structure is completed; and the manufacturing process of the P-type body region will be placed on the gate structure. After forming.
  • the existing process of first forming the columnar structure of the super junction, then forming the gate structure, and then forming the P-type body region has the following contradictions:
  • a deep P-type body region In order to shield the influence of surface defects of the super junction, a deep P-type body region is required, but a deep P-type body region requires a large thermal process, that is, the temperature of thermal annealing will be high and the time will be long; but after the columnar structure is formed, it is not expected Due to the large thermal process, because the large thermal process will cause the impurities of the P-type column and the N-type column in the columnar structure to diffuse and compensate each other to reduce the net doping concentration, and thus cause a significant decline in device performance.
  • the P-type body region can be formed by superimposing the first P-type doped region and the second P-type doped region, so that the deep P-type At the same time, the depth of the body region is avoided, and the thermal process of the annealing of the body region is prevented from adversely affecting the performance of the super junction, and at the same time, the threshold voltage of the device is not affected.
  • the gate-source Capacitance will improve the switching softness and EMI characteristics of the device.
  • the size of the gate-source capacitance needs to be adjusted according to the application. In some cases, the size of the gate-source capacitance limited by the junction depth of the body region cannot meet the requirements of the application.
  • the technical problem to be solved by the present invention is to provide a super junction device, which can make the adjustment of the channel length independent of the depth adjustment of the body region, so that the gate-source capacitance of the device can be controlled by adjusting the length of the channel, and can also be increased by increasing the body region.
  • the depth of the region is used to shield the adverse effects of surface defects of the super junction and thereby improve product yield.
  • the invention also provides a method for manufacturing a super junction device.
  • the device unit area of the super junction device includes:
  • the P-type pillars are composed of P-type epitaxial layers filled in super junction trenches
  • the N-type pillars are composed of first N-type epitaxial layers located between the P-type pillars, and the super junction trenches form In the first N-type epitaxial layer; a P-type body region is formed in the first N-type epitaxial layer.
  • Each super junction device unit also includes a gate structure, the gate structure is a trench gate, including a gate trench and a gate dielectric layer formed on the inner surface of the gate trench and filled in the gate trench in the polysilicon gate.
  • At least one side of the gate trench is located in the N-type pillar, and the depth of the gate trench is greater than the junction depth of the P-type body region.
  • the top surface of the gate trench is level with the top surface of the super junction cell, and the top surface of the polysilicon gate is etched back below the top surface of the gate trench.
  • the source region is composed of an N+ doped region formed by ion implantation on the side of the gate trench on the top of the polysilicon gate and the surface of the P-type body region outside the gate trench.
  • the surface of the P-type body region located at the bottom of the source region and covered by the side of the polysilicon gate is used to form a channel, and the length of the channel is controlled by controlling the position of the top surface of the polysilicon gate and the control gate Source capacitance, the larger the distance between the top surface of the polysilicon gate and the top surface of the gate trench, the shorter the length of the channel, and the smaller the gate-source capacitance.
  • a further improvement is that the P-type body region is formed by overlapping the first P-type doped region and the second P-type doped region, so as to increase the junction depth of the P-type body region.
  • the first P-type doped region is formed by ion implantation and annealing advance before the formation of the P-type column, and the doping concentration and depth of the first P-type doped region are determined by the corresponding ion implantation and annealing advance process
  • the annealing advancement process of the first P-type doped region has the characteristics that it is not limited by the process conditions of the super junction including the P-type pillar, so that the depth of the first P-type doped region can be deepened and thus The junction depth of the P-type body region is deepened.
  • the second P-type doped region is formed in the In the first P-type doped region on both sides of the gate structure, the full-scale ion implantation of the second P-type doped region is used to adjust the threshold voltage for forming the channel.
  • a further improvement is that a terminal region of a super junction device is also formed on the peripheral side of the device unit region; the terminal region includes a P-type ring surrounding the device unit region, and the first P-type doped region It has the same doping structure as the P-type ring and is formed simultaneously by the same ion implantation and annealing process, and the junction depth of the P-type body region is 1 micron to 5 microns.
  • a further improvement is that the first N-type epitaxial layer is formed on the surface of the semiconductor substrate.
  • a further improvement is that the semiconductor substrate is a silicon substrate, the first N-type epitaxial layer is a silicon epitaxial layer, and the P-type epitaxial layer of the P-type column is a silicon epitaxial layer.
  • a further improvement is that an N+ doped drain region is formed at the bottom of the first N-type epitaxial layer, and the drain region is composed of the thinned N+ doped semiconductor substrate or is formed of the thinned N+ doped semiconductor substrate.
  • the above-mentioned semiconductor substrate is formed by adding N+ backside ion implantation.
  • a further improvement is that the ion implantation dose of the first P-type doped region is above 2e13cm -2 , and the junction depth of the P-type body region is 3 microns.
  • the forming steps of the device unit region of the super junction device in the manufacturing method of the super junction device provided by the present invention include:
  • Step 1 forming super junction trenches in the first N-type epitaxial layer, filling the super junction trenches with P-type epitaxial layers to form P-type pillars, and forming the first N-type epitaxial junction between the P-type pillars
  • the layers make up N-pillars.
  • the P-type pillars and the N-type pillars are alternately arranged to form a super junction, and one P-type pillar and one adjacent N-type pillar form a super junction unit.
  • Step 2 forming a P-type body region in the first N-type epitaxial layer.
  • Step 3 forming the gate structure corresponding to each super junction device unit, the gate structure is located on the top of the corresponding super junction unit, the gate structure is a trench gate, and the sub-steps of forming the gate trench include:
  • Step 31 forming a gate trench, at least one side of the gate trench is located in the N-type column, and the depth of the gate trench is greater than the junction depth of the P-type body region; the gate The top surface of the trench is even with the top surface of the super junction unit.
  • Step 32 forming a gate dielectric layer on the inner surface of the gate trench.
  • Step 33 filling the gate trench with a polysilicon gate, the top surface of the polysilicon gate being level with the top surface of the gate trench.
  • Step 34 forming a pattern of a mask layer to define a formation region of a source region, and each of the gate trenches is located in the formation region of the source region.
  • Step 35 using the mask layer pattern as a mask to etch back each of the polysilicon gates so that the top surface of the polysilicon gate is lower than the top surface of the gate trench;
  • the gate dielectric layer in the groove and the polysilicon gate overlap to form the trench gate.
  • Step 4 performing N+ ion implantation to form a source region on the side of the gate trench on the top of the polysilicon gate and on the surface of the P-type body region outside the gate trench.
  • the surface of the P-type body region located at the bottom of the source region and covered by the side of the polysilicon gate is used to form a channel, and the length of the channel is controlled by controlling the position of the top surface of the polysilicon gate and the control gate Source capacitance, the larger the distance between the top surface of the polysilicon gate and the top surface of the gate trench, the shorter the length of the channel, and the smaller the gate-source capacitance.
  • a further improvement is that the P-type body region is formed by overlapping the first P-type doped region and the second P-type doped region, so as to increase the junction depth of the P-type body region; the P-type body region in step 2
  • the formation steps of the body area are decomposed into:
  • the annealing advance process using the first P-type doped region has the characteristics that it is not limited by the process conditions of the super junction including the P-type column, so that the depth of the first P-type doped region can be deepened and thereby deepen the junction depth of the P-type body region;
  • step 33 is completed and before step 34 is performed, a full-scale ion implantation is performed to form a second P-type doped region by self-alignment in the first P-type doped region on both sides of the gate structure.
  • a further improvement is that a termination region including a super junction device is formed around the device unit region; the termination region includes a P-type ring surrounding the device unit region;
  • the first P-type doped region and the P-type ring are simultaneously formed by using the same ion implantation and annealing process; the junction depth of the P-type body region is 1 micron to 5 microns.
  • a further improvement is that the first N-type epitaxial layer is formed on the surface of the semiconductor substrate.
  • a further improvement is that the semiconductor substrate is a silicon substrate, the first N-type epitaxial layer is a silicon epitaxial layer, and the P-type epitaxial layer of the P-type column is a silicon epitaxial layer.
  • a further improvement is that the ion implantation dose of the first P-type doped region is above 2e13cm -2 , and the junction depth of the P-type body region is 3 microns.
  • a further improvement is to further include the step of forming an N+ doped drain region at the bottom of the first N-type epitaxial layer;
  • the drain region is directly formed by thinning the N+ doped semiconductor substrate
  • the drain region is formed by thinning the semiconductor substrate and then performing N+ ion implantation on the thinned semiconductor substrate.
  • step 32 the gate dielectric layer is a gate oxide layer formed by a thermal oxidation process.
  • the present invention forms a P-type body on the side of the gate trench on the top of the polysilicon gate and outside the gate trench by etching back the top surface of the polysilicon gate below the top surface of the gate trench and self-aligning the source region In this way, the length of the channel can be controlled by adjusting the position of the top surface of the polysilicon gate.
  • the surface of the body region covered by the side of the polysilicon gate will form a channel composed of an inversion layer, so the channel length is reduced. That is to say, the area covered by the side of the polysilicon gate becomes smaller.
  • the area covered by the side of the polysilicon gate becomes smaller. A smaller value will make the parasitic capacitance between the gate and the source, that is, the gate-source capacitance, smaller.
  • the polysilicon gate generally passes through the body region completely, so the polysilicon gate can fully cover the entire depth range of the body region, and the deeper the body region is, the greater the gate-source capacitance will be; the trench of the present invention
  • the channel length is achieved by etching back the polysilicon gate, so the adjustment of the channel length can be independent of the depth adjustment of the body region, so that the gate-source capacitance of the device can be controlled by adjusting the length of the channel, that is, the depth of the parasitic body region Deeper, the present invention can also obtain the length of the channel that meets the requirement of the gate-source capacitance.
  • the junction depth of the body region of the present invention is no longer limited by the size of the gate-source capacitance, the junction depth of the body region of the present invention can be made deeper, and the deeper junction depth can shield the disadvantages of super junction surface defects. Affect and thus improve product yield.
  • Fig. 1 is a schematic structural diagram of a super junction device according to an embodiment of the present invention
  • 2A-2H are structural schematic diagrams in each step of the manufacturing method of the super junction device according to the embodiment of the present invention.
  • the device unit area of a super junction device according to an embodiment of the present invention includes:
  • the P-type columns 3 are composed of P-type epitaxial layers filled in super junction trenches, and the N-type columns are composed of first N-type epitaxial layers 2 located between the P-type columns 3.
  • the super junction A trench is formed in the first N-type epitaxial layer 2 ; a P-type body region 4 is formed in the first N-type epitaxial layer 2 .
  • Each super junction device unit also includes a gate structure, the gate structure is a trench gate, including a gate trench 5 and a gate dielectric layer 6 formed on the inner surface of the gate trench 5 and filled in the gate The polysilicon gate 7 in the pole trench 5 .
  • the gate structure is a trench gate, including a gate trench 5 and a gate dielectric layer 6 formed on the inner surface of the gate trench 5 and filled in the gate The polysilicon gate 7 in the pole trench 5 .
  • At least one side of the gate trench 5 is located in the N-type pillar, and the depth of the gate trench 5 is greater than the junction depth of the P-type body region 4 .
  • the top surface of the gate trench 5 is level with the top surface of the super junction unit, and the top surface of the polysilicon gate 7 is etched back to be lower than the top surface of the gate trench 5 .
  • the source region 8 is composed of an N+ doped region formed by ion implantation on the side of the gate trench 5 on the top of the polysilicon gate 7 and the surface of the P-type body region 4 outside the gate trench 5.
  • the surface of the P-type body region 4 located at the bottom of the source region 8 and covered by the side of the polysilicon gate 7 is used to form a channel, and the position of the channel is controlled by controlling the position of the top surface of the polysilicon gate 7 length and control the gate-source capacitance, the larger the distance between the top surface of the polysilicon gate 7 and the top surface of the gate trench 5 is, the shorter the length of the channel is, and the smaller the gate-source capacitance is.
  • the P-type body region 4 is formed by overlapping a first P-type doped region and a second P-type doped region, so as to increase the junction depth of the P-type body region 4 .
  • the first P-type doped region is formed by ion implantation and annealing before the formation of the P-type pillar 3, and the doping concentration and depth of the first P-type doped region are determined by the corresponding ion implantation and annealing process It is determined that the annealing advance process of the first P-type doped region is not limited by the process conditions of the super junction including the P-type pillar 3 so that the depth of the first P-type doped region can be deepened And thus the junction depth of the P-type body region 4 is deepened.
  • the second P-type doped region is self-aligned by full-scale ion implantation. quasi-formed in the first P-type doped region on both sides of the gate structure, and the overall ion implantation of the second P-type doped region is used to adjust the threshold voltage for forming the channel.
  • the terminal area of the super junction device is also formed on the peripheral side of the device unit area; the terminal area includes a P-type ring surrounding the device unit area, the first P-type doped area and the P-type
  • the rings have the same doping structure and are simultaneously formed using the same ion implantation and annealing process, and the junction depth of the P-type body region 4 is 1 micron to 5 microns; more preferably, the first P-type doped
  • the implantation dose of ion implantation in the P-type body region 4 is above 2e13cm -2 , and the junction depth of the P-type body region 4 is 3 microns.
  • the first N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1 .
  • the semiconductor substrate 1 is a silicon substrate
  • the first N-type epitaxial layer 2 is a silicon epitaxial layer
  • the P-type epitaxial layer of the P-type column 3 is a silicon epitaxial layer.
  • An N+ doped drain region is formed at the bottom of the first N-type epitaxial layer 2, and the drain region is composed of the thinned N+ doped semiconductor substrate 1 or the thinned semiconductor substrate Bottom 1 is formed by ion implantation on the back of N+.
  • the interlayer film 9 covers the top region of the polysilicon gate 7 in the gate trench 5 .
  • the contact hole 10 is formed on the top of the source region 8 and the polysilicon gate 7 , and only the contact hole 10 on the top of the source region 8 is shown in FIG. 1 .
  • the bottom of the contact hole 10 at the top of the source region 8 also passes through the source region 8 and contacts the P-type body region 4, and the P-type body region at the bottom of the contact hole 10 at the top of the source region 8
  • a contact region 11 composed of a P+ region is also formed on the surface of the body region 4 .
  • a backside metal layer 13 is formed on the backside of the semiconductor substrate 1 after the backside is thinned, and the drain electrode is composed of the backside metallization layer 13 .
  • the top surface of the polysilicon gate 7 is etched back below the top surface of the gate trench 5 and the source region 8 is self-aligned to form the side of the gate trench 5 and the gate on the top of the polysilicon gate 7.
  • the surface of the P-type body region 4 outside the trench 5 can control the length of the channel by adjusting the position of the top surface of the polysilicon gate 7.
  • the polysilicon gate 7 Since the source region 8 and the body region of the device are usually connected to the source, the polysilicon gate 7 will be connected to the The gate, the body region covered by the side of the polysilicon gate 7 will reduce the parasitic capacitance between the gate and the source, that is, the gate-source capacitance.
  • the polysilicon gate 7 usually passes through the body region completely, so the polysilicon gate 7 can fully cover the entire depth range of the body region, so that the deeper the body region is, the greater the gate-source capacitance will be; the present invention
  • the channel length of the embodiment is realized by etching back the polysilicon gate 7, so the adjustment of the channel length can be independent of the depth adjustment of the body region, so that the gate-source capacitance of the device can be controlled by adjusting the length of the channel, that is, The depth of the parasitic body region is relatively deep, and the present invention can also obtain the length of the channel that meets the requirement of gate-source capacitance.
  • the junction depth of the body region in the embodiment of the present invention is no longer limited by the size of the gate-source capacitance, the junction depth of the body region of the present invention can be made deeper, and the deeper junction depth can shield the surface defects of the super junction adverse effects and thereby improve product yield.
  • FIG. 2A to FIG. 2H it is a schematic structural view of each step of the manufacturing method of the super junction device in the embodiment of the present invention; the forming steps of the device unit area of the super junction device in the manufacturing method of the super junction device in the embodiment of the present invention include:
  • Step 1 as shown in FIG. 2A, a super junction trench is formed in the first N-type epitaxial layer 2, and a P-type epitaxial layer is filled in the super junction trench to form a P-type pillar 3, and the P-type pillar 3 is formed by The first N-type epitaxial layer 2 between the 3 forms an N-type column.
  • the P-type pillars 3 and the N-type pillars are alternately arranged to form a super junction, and one P-type pillar 3 and an adjacent N-type pillar form a super junction unit.
  • the first N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1 .
  • the semiconductor substrate 1 is a silicon substrate
  • the first N-type epitaxial layer 2 is a silicon epitaxial layer
  • the P-type epitaxial layer of the P-type column 3 is a silicon epitaxial layer.
  • Step 2 as shown in FIG. 2B , forming a P-type body region 4 in the first N-type epitaxial layer 2 .
  • Step 3 as shown in Figure 2C, form the gate structure corresponding to each super junction device unit, the gate structure is located on the top of the corresponding super junction unit, the gate structure is a trench gate, and the gate structure is formed
  • the sub-steps of pole trench 5 include:
  • Step 31 as shown in FIG. 2C, form a gate trench 5, at least one side of the gate trench 5 is located in the N-type column, and the depth of the gate trench 5 is greater than that of the P-type body
  • the junction depth of the region 4; the top surface of the gate trench 5 is flat with the top surface of the super junction unit.
  • Step 32 as shown in FIG. 2C , forming a gate dielectric layer 6 on the inner surface of the gate trench 5 .
  • the gate dielectric layer 6 is a gate oxide layer formed by a thermal oxidation process.
  • Step 33 as shown in FIG. 2C , filling the gate trench 5 with a polysilicon gate 7 , the top surface of the polysilicon gate 7 is even with the top surface of the gate trench 5 .
  • Step 34 as shown in FIG. 2D , forming a mask layer pattern 201 to define the formation area of the source region 8 , and each of the gate trenches 5 is located in the formation area of the source region 8 .
  • the mask layer pattern 201 is formed by photoresist pattern.
  • Step 35 use the mask layer pattern 201 as a mask to etch back each polysilicon gate 7 so that the top surface of the polysilicon gate 7 is lower than the top of the gate trench 5 Surface: the gate dielectric layer 6 filled in the gate trench 5 and the polysilicon gate 7 are stacked to form the trench gate.
  • Step 4 as shown in FIG. 2F , perform N+ ion implantation to form a source region on the side of the gate trench 5 at the top of the polysilicon gate 7 and on the surface of the P-type body region 4 outside the gate trench 5 8. After that, the mask layer pattern 201 is removed.
  • the surface of the P-type body region 4 located at the bottom of the source region 8 and covered by the side of the polysilicon gate 7 is used to form a channel, and the position of the channel is controlled by controlling the position of the top surface of the polysilicon gate 7 length and control the gate-source capacitance, the larger the distance between the top surface of the polysilicon gate 7 and the top surface of the gate trench 5 is, the shorter the length of the channel is, and the smaller the gate-source capacitance is.
  • the P-type body region 4 is formed by overlapping the first P-type doped region and the second P-type doped region, so as to increase the junction depth of the P-type body region 4;
  • the formation steps of the P-type body region 4 are decomposed into:
  • the annealing advance process using the first P-type doped region has the characteristics that it is not limited by the process conditions of the super junction including the P-type column 3, so that the depth of the first P-type doped region can be Deepen and thus deepen the junction depth of the P-type body region 4 .
  • step 33 is completed and before step 34 is performed, a full-scale ion implantation is performed to form a second P-type doped region by self-alignment in the first P-type doped region on both sides of the gate structure.
  • a terminal region including a super junction device is also formed on the peripheral side of the device unit area; the terminal area includes a P-type ring surrounding the device unit area;
  • the first P-type doped region and the P-type ring are simultaneously formed by using the same ion implantation and annealing process; the junction depth of the P-type body region 4 is 1 micron to 5 microns. More preferably, the ion implantation dose of the first P-type doped region is above 2e13 cm -2 , and the junction depth of the P-type body region 4 is 3 microns.
  • an interlayer film 9 is formed.
  • the interlayer film 9 covers the top region of the polysilicon gate 7 in the gate trench 5 .
  • the opening 10a of the contact hole 10 is formed.
  • the contact hole 10 is formed on the top of the source region 8 and the polysilicon gate 7 , and only the opening 10 a of the contact hole 10 on the top of the source region 8 is shown in FIG. 2G .
  • the bottom of the opening 10 a of the contact hole 10 at the top of the source region 8 also passes through the source region 8 and contacts the P-type body region 4 .
  • a contact region 11 is formed on the surface of the P-type body region 4 at the bottom of the contact hole 10 at the top of the source region 8 by implanting P+ ions.
  • the contact hole 10 is formed by filling the opening 10 a with a metal layer. Forming the front metal layer 12 and patterning the front metal layer 12 to form a source and a gate composed of the patterned front metal layer 12 .
  • an N+ doped drain region is formed at the bottom of the first N-type epitaxial layer 2, and the step of forming the drain region includes: the drain region passes through the N+ doped semiconductor substrate 1 is directly formed after thinning; or, the drain region is formed by thinning the semiconductor substrate 1 and then performing N+ backside ion implantation on the thinned semiconductor substrate 1 .
  • a backside metal layer 13 is formed on the backside of the semiconductor substrate 1 after the backside is thinned, and the drain electrode is composed of the backside metallization layer 13 .

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Abstract

本发明公开了一种超级结器件，器件单元区的栅极结构为沟槽栅，栅极沟槽的深度大于P型体区的结深；栅极沟槽的顶部表面和超结单元的顶部表面相平，多晶硅栅的顶部表面被回刻到低于栅极沟槽的顶部表面；源区由对多晶硅栅顶部的栅极沟槽侧面和栅极沟槽外的P型体区表面进行离子注入形成的N+掺杂区组成；位于源区底部且被多晶硅栅侧面覆盖的体区的表面用于形成沟道，通过控制多晶硅栅的顶部表面的位置控制沟道的长度并控制栅源电容。本发明还公开了一种超级结器件的制造方法。本发明能使沟道长度的调节独立于体区的深度调节，从而能通过调节沟道的长度控制器件的栅源电容，还能通过增加体区的深度来提高产品良率。

Description

超级结器件及其制造方法 技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种超级结器件。本发明还涉及一种超级结器件的制造方法。
背景技术
超级结为由形成于半导体衬底中的交替排列的P型薄层也称P型柱(Pillar)和N型薄层也称N型柱组成，采用了超级结的器件为超级结器件如超级结MOSFET。利用P型薄层和N型薄层电荷平衡的体内降低表面电场(Resurf)技术能提升器件的反向击穿电压的同时又保持较小的导通电阻。
超级结的PN间隔的Pillar结构是超级结的最大特点。现有制作PN间隔的pillar结构主要有两种方法，一种是通过多次外延以及离子注入的方法获得，另一种是通过深沟槽刻蚀以及外延(EPI)填充的方式来制作。后一种方法是通过沟槽工艺制作超级结器件，需要先在半导体衬底如硅衬底表面的N型掺杂外延层上刻蚀一定深度和宽度的沟槽，然后利用外延填充(EPI Filling)的方式在刻出的沟槽上填充P型掺杂的硅外延。
在通过深沟槽即超级结沟槽刻蚀及外延填充工艺来制作超级结时，由于受到超级结沟槽的表面附近外延层台阶如硅台阶(Step silicon)的影响，容易在靠近表面的体硅中形成缺陷，从而导致器件的漏电失效。
现有方法中，超级结器件如超级结MOSFET中会形成P型体区，且P型体区是通过在超级结的沟槽填充完成之后通过离子注入加退火推进形成，P型体区的底部为N型柱对应的N型漂移区，P型体区和N型漂移区之间会形成体二极管。通过加深P型体区的深度能将绝大部分表面缺陷排除在耗尽区之外，从而能很好的改善器件漏电。也即，如果需要将超级结的表面缺陷所带来的不利影响屏蔽，需要较深的P型体区。
超级结器件中，P型体区的表面通常用于形成沟道，具体为被栅极结构覆盖的P型体区表面用于形成沟道。由于超级结的柱状(Pillar)结构即P型柱和N型柱的制作工艺复杂，栅极结构通常放置在柱状结构的制造完成之后；而P型体区的制造工艺又会放置在栅极结构形成之后。现有的这种先形成超级结的柱状结构、再形成栅极结 构以及再形成P型体区的工艺存在如下矛盾：
为了屏蔽超级结的表面缺陷的影响需要深的P型体区，但是深的P型体区需要大的热过程即热退火推进的温度会高以及时间会久；但是柱状结构形成之后，不希望由大的热过程，因为大的热过程会使柱状结构中的P型柱的杂质和N型柱的杂质互相扩散并且互相补偿使净掺杂浓度降低，并从而会导致器件性能大幅衰退。
在申请人之前一个申请号为2020100690252的专利申请中，申请人公开了通过第一P型掺杂区和第二P型掺杂区的叠加来形成P型体区，从而能在较深P型体区的深度的同时，避免体区的退火推进的热过程对超级结的性能的不利影响以及同时不影响器件的阈值电压。
但是，对应沟槽栅超级结器件，随着体区的结深的增加，沟槽栅侧面覆盖的结深的区域范围也会增加，由体区的深结所带来的寄生电容即栅源电容也会增加。栅源电容增加会使器件开关软度及EMI特性均有所提升。
但是在一些开关频率更高的场合，大的栅源电容带来大的开关损耗，会导致系统效率的下降。所以，栅源电容的大小需要根据应用场合进行调节，有些场合中，体区的结深所限定的栅源电容的大小并不能满足应用场合的要求。
发明内容
本发明所要解决的技术问题是提供一种超级结器件，能使沟道长度的调节独立于体区的深度调节，从而能通过调节沟道的长度控制器件的栅源电容，还能通过增加体区的深度来屏蔽超级结的表面缺陷的不利影响并从而提高产品良率。为此，本发明还提供一种超级结器件的制造方法。
为解决上述技术问题，本发明提供的超级结器件的器件单元区中包括：
由交替排列的P型柱和N型柱组成的超级结，由一个所述P型柱和相邻的一个所述N型柱组成一个超级结单元。
所述P型柱由填充于超级结沟槽中的P型外延层组成，所述N型柱由位于所述P型柱之间的第一N型外延层组成，所述超级结沟槽形成于所述第一N型外延层中；在所述第一N型外延层中形成有P型体区。
各超级结器件单元还包括栅极结构，所述栅极结构为沟槽栅，包括栅极沟槽和形成于所述栅极沟槽内侧表面的栅介质层以及填充于所述栅极沟槽中的多晶硅栅。
所述栅极沟槽的至少一个侧面位于所述N型柱中，所述栅极沟槽的深度大于所述 P型体区的结深。
所述栅极沟槽的顶部表面和所述超结单元的顶部表面相平，所述多晶硅栅的顶部表面被回刻到低于所述栅极沟槽的顶部表面。
源区由对所述多晶硅栅顶部的所述栅极沟槽侧面和所述栅极沟槽外的所述P型体区表面进行离子注入形成的N+掺杂区组成。
位于所述源区底部且被所述多晶硅栅侧面覆盖的所述P型体区的表面用于形成沟道，通过控制所述多晶硅栅的顶部表面的位置控制所述沟道的长度并控制栅源电容，所述多晶硅栅的顶部表面和所述栅极沟槽的顶部表面的间距越大，所述沟道的长度越短，所述栅源电容越小。
进一步的改进是，所述P型体区由第一P型掺杂区和第二P型掺杂区叠加而成，用以增加所述P型体区的结深。
所述第一P型掺杂区在所述P型柱形成之前通过离子注入和退火推进形成，所述第一P型掺杂区的掺杂浓度和深度由对应的离子注入和退火推进工艺确定，所述第一P型掺杂区的退火推进工艺具有不受包括所述P型柱的所述超级结的工艺条件限制的特点使得所述第一P型掺杂区的深度能加深并从而使所述P型体区的结深加深。
在所述多晶硅栅回刻之前，所述多晶硅栅的顶部表面和所述栅极沟槽的顶部表面相平的条件下，所述第二P型掺杂区通过全面离子注入自对准形成于所述栅极结构两侧的所述第一P型掺杂区中，所述第二P型掺杂区的全面离子注入用于调节形成所述沟道的阈值电压。
进一步的改进是，在所述器件单元区的周侧还形成有超级结器件的终端区；所述终端区中包括环绕所述器件单元区的P型环，所述第一P型掺杂区和所述P型环具有相同的掺杂结构且采用相同的离子注入和退火推进工艺同时形成，所述P型体区的结深为1微米～5微米。
进一步的改进是，所述第一N型外延层形成于半导体衬底表面。
进一步的改进是，所述半导体衬底为硅衬底，所述第一N型外延层为硅外延层，所述P型柱的P型外延层为硅外延层。
进一步的改进是，N+掺杂的漏区形成于所述第一N型外延层的底部，所述漏区由减薄后的N+掺杂的所述半导体衬底组成或由减薄后的所述半导体衬底加N+背面离子注入形成。
进一步的改进是，所述第一P型掺杂区的离子注入的注入剂量为2e13cm -2以上，所述P型体区的结深为3微米。
为解决上述技术问题，本发明提供的超级结器件的制造方法中超级结器件的器件单元区的形成步骤包括：
步骤一、在第一N型外延层中形成超级结沟槽，在所述超级结沟槽中填充P型外延层组成P型柱，由位于所述P型柱之间的第一N型外延层组成N型柱。
所述P型柱和所述N型柱交替排列形成超级结，由一个所述P型柱和相邻的一个所述N型柱组成一个超级结单元。
步骤二、在所述第一N型外延层中形成P型体区。
步骤三、形成各超级结器件单元对应的栅极结构，所述栅极结构位于对应的所述超级结单元顶部，所述栅极结构为沟槽栅，形成所述栅极沟槽的分步骤包括：
步骤31、形成栅极沟槽，所述栅极沟槽的至少一个侧面位于所述N型柱中，所述栅极沟槽的深度大于所述P型体区的结深；所述栅极沟槽的顶部表面和所述超结单元的顶部表面相平。
步骤32、在所述栅极沟槽的内侧表面形成栅介质层。
步骤33、在所述栅极沟槽中填充多晶硅栅，所述多晶硅栅的顶部表面和所述栅极沟槽的顶部表面相平。
步骤34、形成掩膜层图形定义出源区的形成区域，各所述栅极沟槽位于所述源区的形成区域中。
步骤35、以所述掩膜层图形为掩膜对各所述多晶硅栅进行回刻使所述多晶硅栅的顶部表面低于所述栅极沟槽的顶部表面；由填充于所述栅极沟槽中的所述栅介质层和所述多晶硅栅叠加形成所述沟槽栅。
步骤四、进行N+离子注入在所述多晶硅栅顶部的所述栅极沟槽侧面和所述栅极沟槽外的所述P型体区表面形成源区。
位于所述源区底部且被所述多晶硅栅侧面覆盖的所述P型体区的表面用于形成沟道，通过控制所述多晶硅栅的顶部表面的位置控制所述沟道的长度并控制栅源电容，所述多晶硅栅的顶部表面和所述栅极沟槽的顶部表面的间距越大，所述沟道的长度越短，所述栅源电容越小。
进一步的改进是，所述P型体区由第一P型掺杂区和第二P型掺杂区叠加而成， 用以增加所述P型体区的结深；步骤二的所述P型体区的形成步骤分解为：
在步骤一的所述超级结沟槽形成之前，进行离子注入和退火推进形成第一P型掺杂区，通过离子注入和退火推进工艺调节所述第一P型掺杂区的掺杂浓度和深度；利用所述第一P型掺杂区的退火推进工艺具有不受包括所述P型柱的所述超级结的工艺条件限制的特点使得所述第一P型掺杂区的深度能加深并从而使所述P型体区的结深加深；
在步骤33完成后以及进行步骤34之前，进行全面离子注入在所述栅极结构两侧的所述第一P型掺杂区中自对准形成第二P型掺杂区。
进一步的改进是，在所述器件单元区的周侧还形成包括超级结器件的终端区；所述终端区中包括环绕所述器件单元区的P型环；
采用相同的离子注入和退火推进工艺同时形成所述第一P型掺杂区和所述P型环；所述P型体区的结深为1微米～5微米。
进一步的改进是，所述第一N型外延层形成于半导体衬底表面。
进一步的改进是，所述半导体衬底为硅衬底，所述第一N型外延层为硅外延层，所述P型柱的P型外延层为硅外延层。
进一步的改进是，所述第一P型掺杂区的离子注入的注入剂量为2e13cm -2以上，所述P型体区的结深为3微米。
进一步的改进是，还包括在所述第一N型外延层的底部形成N+掺杂的漏区的步骤；
所述漏区通过对N+掺杂的所述半导体衬底减薄后直接形成；
或者，所述漏区通过对所述半导体衬底减薄后再对减薄后的所述半导体衬底进行N+背面离子注入形成。
进一步的改进是，步骤32中，所述栅介质层为采用热氧化工艺形成的栅氧化层。
本发明通过将多晶硅栅的顶部表面回刻到栅极沟槽的顶部表面之下且将源区自对准形成在多晶硅栅的顶部的栅极沟槽侧面和栅极沟槽外的P型体区表面，这样通过调节多晶硅栅的顶部表面位置就能控制沟道的长度，在器件导通时被多晶硅栅侧面覆盖的体区表面会形成由反型层组成的沟道，故沟道长度减少也即为多晶硅栅侧面覆盖体区的区域范围变小，由于器件的源区和体区通常都会连接到源极，多晶硅栅则会连接到栅极，多晶硅栅侧面覆盖的体区的区域范围变小后则会使得栅极和源极之间的寄 生电容即栅源电容变小。
现有器件中，多晶硅栅通常会全部穿过体区，所以多晶硅栅会对体区的整个深度范围实现全覆盖，这样体区的深度越深，则栅源电容会越大；本发明的沟道长度是通过对多晶硅栅的回刻实现，故能使沟道长度的调节独立于体区的深度调节，从而能通过调节沟道的长度控制器件的栅源电容，也即寄生体区的深度较深，本发明也能得到满足栅源电容要求的沟道的长度。
另外，由于本发明的体区的结深不再受到栅源电容的大小限制，故本发明的体区的结深能做的较深，较深的结深能屏蔽超级结的表面缺陷的不利影响并从而提高产品良率。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是本发明实施例超级结器件的结构示意图；
图2A-图2H是本发明实施例超级结器件的制造方法各步骤中的结构示意图。
具体实施方式
如图1所示，是本发明实施例超级结器件的结构示意图；本发明实施例超级结器件的器件单元区中包括：
由交替排列的P型柱3和N型柱组成的超级结，由一个所述P型柱3和相邻的一个所述N型柱组成一个超级结单元。
所述P型柱3由填充于超级结沟槽中的P型外延层组成，所述N型柱由位于所述P型柱3之间的第一N型外延层2组成，所述超级结沟槽形成于所述第一N型外延层2中；在所述第一N型外延层2中形成有P型体区4。
各超级结器件单元还包括栅极结构，所述栅极结构为沟槽栅，包括栅极沟槽5和形成于所述栅极沟槽5内侧表面的栅介质层6以及填充于所述栅极沟槽5中的多晶硅栅7。
所述栅极沟槽5的至少一个侧面位于所述N型柱中，所述栅极沟槽5的深度大于所述P型体区4的结深。
所述栅极沟槽5的顶部表面和所述超结单元的顶部表面相平，所述多晶硅栅7的顶部表面被回刻到低于所述栅极沟槽5的顶部表面。
源区8由对所述多晶硅栅7顶部的所述栅极沟槽5侧面和所述栅极沟槽5外的所 述P型体区4表面进行离子注入形成的N+掺杂区组成。
位于所述源区8底部且被所述多晶硅栅7侧面覆盖的所述P型体区4的表面用于形成沟道，通过控制所述多晶硅栅7的顶部表面的位置控制所述沟道的长度并控制栅源电容，所述多晶硅栅7的顶部表面和所述栅极沟槽5的顶部表面的间距越大，所述沟道的长度越短，所述栅源电容越小。
较佳为，所述P型体区4由第一P型掺杂区和第二P型掺杂区叠加而成，用以增加所述P型体区4的结深。
所述第一P型掺杂区在所述P型柱3形成之前通过离子注入和退火推进形成，所述第一P型掺杂区的掺杂浓度和深度由对应的离子注入和退火推进工艺确定，所述第一P型掺杂区的退火推进工艺具有不受包括所述P型柱3的所述超级结的工艺条件限制的特点使得所述第一P型掺杂区的深度能加深并从而使所述P型体区4的结深加深。
在所述多晶硅栅7回刻之前，所述多晶硅栅7的顶部表面和所述栅极沟槽5的顶部表面相平的条件下，所述第二P型掺杂区通过全面离子注入自对准形成于所述栅极结构两侧的所述第一P型掺杂区中，所述第二P型掺杂区的全面离子注入用于调节形成所述沟道的阈值电压。
在所述器件单元区的周侧还形成有超级结器件的终端区；所述终端区中包括环绕所述器件单元区的P型环，所述第一P型掺杂区和所述P型环具有相同的掺杂结构且采用相同的离子注入和退火推进工艺同时形成，所述P型体区4的结深为1微米～5微米；更优选择为，所述第一P型掺杂区的离子注入的注入剂量为2e13cm -2以上，所述P型体区4的结深为3微米。
本发明实施例中，所述第一N型外延层2形成于半导体衬底1表面。
所述半导体衬底1为硅衬底，所述第一N型外延层2为硅外延层，所述P型柱3的P型外延层为硅外延层。
N+掺杂的漏区形成于所述第一N型外延层2的底部，所述漏区由减薄后的N+掺杂的所述半导体衬底1组成或由减薄后的所述半导体衬底1加N+背面离子注入形成。
还包括，层间膜9，接触孔10以及正面金属层12。层间膜9会将所述多晶硅栅7的顶部区域的所述栅极沟槽5中。
在所述源区8和所述多晶硅栅7的顶部都会形成所述接触孔10，图1中仅显示了所述源区8顶部的接触孔10。所述源区8顶部的接触孔10的底部还会穿过所述源区 8并和所述P型体区4接触，且在所述源区8顶部的接触孔10底部的所述P型体区4的表面还形成有由P+区组成的接触区11。
背面减薄后的所述半导体衬底1的背面形成有背面金属层13，漏极由所述背面金属层13组成。
本发明实施例通过将多晶硅栅7的顶部表面回刻到栅极沟槽5的顶部表面之下且将源区8自对准形成在多晶硅栅7的顶部的栅极沟槽5侧面和栅极沟槽5外的P型体区4表面，这样通过调节多晶硅栅7的顶部表面位置就能控制沟道的长度，在器件导通时被多晶硅栅7侧面覆盖的体区表面会形成由反型层组成的沟道，故沟道长度减少也即为多晶硅栅7侧面覆盖体区的区域范围变小，由于器件的源区8和体区通常都会连接到源极，多晶硅栅7则会连接到栅极，多晶硅栅7侧面覆盖的体区的区域范围变小后则会使得栅极和源极之间的寄生电容即栅源电容变小。
现有器件中，多晶硅栅7通常会全部穿过体区，所以多晶硅栅7会对体区的整个深度范围实现全覆盖，这样体区的深度越深，则栅源电容会越大；本发明实施例的沟道长度是通过对多晶硅栅7的回刻实现，故能使沟道长度的调节独立于体区的深度调节，从而能通过调节沟道的长度控制器件的栅源电容，也即寄生体区的深度较深，本发明也能得到满足栅源电容要求的沟道的长度。
另外，由于本发明实施例的体区的结深不再受到栅源电容的大小限制，故本发明的体区的结深能做的较深，较深的结深能屏蔽超级结的表面缺陷的不利影响并从而提高产品良率。
如图2A至图2H所示，是本发明实施例超级结器件的制造方法各步骤中的结构示意图；本发明实施例超级结器件的制造方法中超级结器件的器件单元区的形成步骤包括：
步骤一、如图2A所示，在第一N型外延层2中形成超级结沟槽，在所述超级结沟槽中填充P型外延层组成P型柱3，由位于所述P型柱3之间的第一N型外延层2组成N型柱。
所述P型柱3和所述N型柱交替排列形成超级结，由一个所述P型柱3和相邻的一个所述N型柱组成一个超级结单元。
本发明实施例方法中，所述第一N型外延层2形成于半导体衬底1表面。
所述半导体衬底1为硅衬底，所述第一N型外延层2为硅外延层，所述P型柱3 的P型外延层为硅外延层。
步骤二、如图2B所示，在所述第一N型外延层2中形成P型体区4。
步骤三、如图2C所示，形成各超级结器件单元对应的栅极结构，所述栅极结构位于对应的所述超级结单元顶部，所述栅极结构为沟槽栅，形成所述栅极沟槽5的分步骤包括：
步骤31、如图2C所示，形成栅极沟槽5，所述栅极沟槽5的至少一个侧面位于所述N型柱中，所述栅极沟槽5的深度大于所述P型体区4的结深；所述栅极沟槽5的顶部表面和所述超结单元的顶部表面相平。
步骤32、如图2C所示，在所述栅极沟槽5的内侧表面形成栅介质层6。
本发明实施例方法中，所述栅介质层6为采用热氧化工艺形成的栅氧化层。
步骤33、如图2C所示，在所述栅极沟槽5中填充多晶硅栅7，所述多晶硅栅7的顶部表面和所述栅极沟槽5的顶部表面相平。
步骤34、如图2D所示，形成掩膜层图形201定义出源区8的形成区域，各所述栅极沟槽5位于所述源区8的形成区域中。通常，所述掩膜层图形201采用光刻胶图形形成。
步骤35、如图2E所示，以所述掩膜层图形201为掩膜对各所述多晶硅栅7进行回刻使所述多晶硅栅7的顶部表面低于所述栅极沟槽5的顶部表面；由填充于所述栅极沟槽5中的所述栅介质层6和所述多晶硅栅7叠加形成所述沟槽栅。
步骤四、如图2F所示，进行N+离子注入在所述多晶硅栅7顶部的所述栅极沟槽5侧面和所述栅极沟槽5外的所述P型体区4表面形成源区8。之后去除所述掩膜层图形201。
位于所述源区8底部且被所述多晶硅栅7侧面覆盖的所述P型体区4的表面用于形成沟道，通过控制所述多晶硅栅7的顶部表面的位置控制所述沟道的长度并控制栅源电容，所述多晶硅栅7的顶部表面和所述栅极沟槽5的顶部表面的间距越大，所述沟道的长度越短，所述栅源电容越小。
较佳选择为，所述P型体区4由第一P型掺杂区和第二P型掺杂区叠加而成，用以增加所述P型体区4的结深；步骤二的所述P型体区4的形成步骤分解为：
在步骤一的所述超级结沟槽形成之前，进行离子注入和退火推进形成第一P型掺杂区，通过离子注入和退火推进工艺调节所述第一P型掺杂区的掺杂浓度和深度；利 用所述第一P型掺杂区的退火推进工艺具有不受包括所述P型柱3的所述超级结的工艺条件限制的特点使得所述第一P型掺杂区的深度能加深并从而使所述P型体区4的结深加深。
在步骤33完成后以及进行步骤34之前，进行全面离子注入在所述栅极结构两侧的所述第一P型掺杂区中自对准形成第二P型掺杂区。
在所述器件单元区的周侧还形成包括超级结器件的终端区；所述终端区中包括环绕所述器件单元区的P型环；
采用相同的离子注入和退火推进工艺同时形成所述第一P型掺杂区和所述P型环；所述P型体区4的结深为1微米～5微米。更优选择为，所述第一P型掺杂区的离子注入的注入剂量为2e13cm -2以上，所述P型体区4的结深为3微米。
之后，还包括如下器件正面工艺步骤：
如图2G所示，形成层间膜9。层间膜9会将所述多晶硅栅7的顶部区域的所述栅极沟槽5中。
形成接触孔10的开口10a。在所述源区8和所述多晶硅栅7的顶部都会形成所述接触孔10，图2G中仅显示了所述源区8顶部的接触孔10的开口10a。所述源区8顶部的接触孔10的开口10a的底部还会穿过所述源区8并和所述P型体区4接触。
在所述接触孔10的开口10a形成之后，还包括进行P+离子注入在所述源区8顶部的接触孔10底部的所述P型体区4的表面形成接触区11。
如图2H所示，在开口10a中填充金属层形成所述接触孔10。形成正面金属层12并对正面金属层12进行图形化形成由图形化后的所述正面金属层12组成的源极和栅极。
之后进行背面工艺，包括：
如图1所示，在所述第一N型外延层2的底部形成N+掺杂的漏区，形成所述漏区的步骤包括：所述漏区通过对N+掺杂的所述半导体衬底1减薄后直接形成；或者，所述漏区通过对所述半导体衬底1减薄后再对减薄后的所述半导体衬底1进行N+背面离子注入形成。
背面减薄后的所述半导体衬底1的背面形成有背面金属层13，漏极由所述背面金属层13组成。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限 制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (15)

  1. 一种超级结器件，其特征在于，超级结器件的器件单元区中包括：
    由交替排列的P型柱和N型柱组成的超级结，由一个所述P型柱和相邻的一个所述N型柱组成一个超级结单元；
    所述P型柱由填充于超级结沟槽中的P型外延层组成，所述N型柱由位于所述P型柱之间的第一N型外延层组成，所述超级结沟槽形成于所述第一N型外延层中；在所述第一N型外延层中形成有P型体区；
    各超级结器件单元还包括栅极结构，所述栅极结构为沟槽栅，包括栅极沟槽和形成于所述栅极沟槽内侧表面的栅介质层以及填充于所述栅极沟槽中的多晶硅栅；
    所述栅极沟槽的至少一个侧面位于所述N型柱中，所述栅极沟槽的深度大于所述P型体区的结深；
    所述栅极沟槽的顶部表面和所述超结单元的顶部表面相平，所述多晶硅栅的顶部表面被回刻到低于所述栅极沟槽的顶部表面；
    源区由对所述多晶硅栅顶部的所述栅极沟槽侧面和所述栅极沟槽外的所述P型体区表面进行离子注入形成的N+掺杂区组成；
    位于所述源区底部且被所述多晶硅栅侧面覆盖的所述P型体区的表面用于形成沟道，通过控制所述多晶硅栅的顶部表面的位置控制所述沟道的长度并控制栅源电容，所述多晶硅栅的顶部表面和所述栅极沟槽的顶部表面的间距越大，所述沟道的长度越短，所述栅源电容越小。
  2. 如权利要求1所述的超级结器件，其特征在于：所述P型体区由第一P型掺杂区和第二P型掺杂区叠加而成，用以增加所述P型体区的结深；
    所述第一P型掺杂区在所述P型柱形成之前通过离子注入和退火推进形成，所述第一P型掺杂区的掺杂浓度和深度由对应的离子注入和退火推进工艺确定，所述第一P型掺杂区的退火推进工艺具有不受包括所述P型柱的所述超级结的工艺条件限制的特点使得所述第一P型掺杂区的深度能加深并从而使所述P型体区的结深加深；
    在所述多晶硅栅回刻之前，所述多晶硅栅的顶部表面和所述栅极沟槽的顶部表面相平的条件下，所述第二P型掺杂区通过全面离子注入自对准形成于所述栅极结构两侧的所述第一P型掺杂区中，所述第二P型掺杂区的全面离子注入用于调节形成所述沟道的阈值电压。
  3. 如权利要求2所述的超级结器件，其特征在于：在所述器件单元区的周侧还形成有超级结器件的终端区；所述终端区中包括环绕所述器件单元区的P型环，所述第一P型掺杂区和所述P型环具有相同的掺杂结构且采用相同的离子注入和退火推进工艺同时形成，所述P型体区的结深为1微米～5微米。
  4. 如权利要求3所述的超级结器件，其特征在于：所述第一N型外延层形成于半导体衬底表面。
  5. 如权利要求4所述的超级结器件，其特征在于：所述半导体衬底为硅衬底，所述第一N型外延层为硅外延层，所述P型柱的P型外延层为硅外延层。
  6. 如权利要求1所述的超级结器件，其特征在于：N+掺杂的漏区形成于所述第一N型外延层的底部，所述漏区由减薄后的N+掺杂的所述半导体衬底组成或由减薄后的所述半导体衬底加N+背面离子注入形成。
  7. 如权利要求3所述的超级结器件，其特征在于：所述第一P型掺杂区的离子注入的注入剂量为2e13cm -2以上，所述P型体区的结深为3微米。
  8. 一种超级结器件的制造方法，其特征在于，超级结器件的器件单元区的形成步骤包括：
    步骤一、在第一N型外延层中形成超级结沟槽，在所述超级结沟槽中填充P型外延层组成P型柱，由位于所述P型柱之间的第一N型外延层组成N型柱；
    所述P型柱和所述N型柱交替排列形成超级结，由一个所述P型柱和相邻的一个所述N型柱组成一个超级结单元；
    步骤二、在所述第一N型外延层中形成P型体区；
    步骤三、形成各超级结器件单元对应的栅极结构，所述栅极结构位于对应的所述超级结单元顶部，所述栅极结构为沟槽栅，形成所述栅极沟槽的分步骤包括：
    步骤31、形成栅极沟槽，所述栅极沟槽的至少一个侧面位于所述N型柱中，所述栅极沟槽的深度大于所述P型体区的结深；所述栅极沟槽的顶部表面和所述超结单元的顶部表面相平；
    步骤32、在所述栅极沟槽的内侧表面形成栅介质层；
    步骤33、在所述栅极沟槽中填充多晶硅栅，所述多晶硅栅的顶部表面和所述栅极沟槽的顶部表面相平；
    步骤34、形成掩膜层图形定义出源区的形成区域，各所述栅极沟槽位于所述源区 的形成区域中；
    步骤35、以所述掩膜层图形为掩膜对各所述多晶硅栅进行回刻使所述多晶硅栅的顶部表面低于所述栅极沟槽的顶部表面；由填充于所述栅极沟槽中的所述栅介质层和所述多晶硅栅叠加形成所述沟槽栅；
    步骤四、进行N+离子注入在所述多晶硅栅顶部的所述栅极沟槽侧面和所述栅极沟槽外的所述P型体区表面形成源区；
    位于所述源区底部且被所述多晶硅栅侧面覆盖的所述P型体区的表面用于形成沟道，通过控制所述多晶硅栅的顶部表面的位置控制所述沟道的长度并控制栅源电容，所述多晶硅栅的顶部表面和所述栅极沟槽的顶部表面的间距越大，所述沟道的长度越短，所述栅源电容越小。
  9. 如权利要求8所述的超级结器件的制造方法，其特征在于：所述P型体区由第一P型掺杂区和第二P型掺杂区叠加而成，用以增加所述P型体区的结深；步骤二的所述P型体区的形成步骤分解为：
    在步骤一的所述超级结沟槽形成之前，进行离子注入和退火推进形成第一P型掺杂区，通过离子注入和退火推进工艺调节所述第一P型掺杂区的掺杂浓度和深度；利用所述第一P型掺杂区的退火推进工艺具有不受包括所述P型柱的所述超级结的工艺条件限制的特点使得所述第一P型掺杂区的深度能加深并从而使所述P型体区的结深加深；
    在步骤33完成后以及进行步骤34之前，进行全面离子注入在所述栅极结构两侧的所述第一P型掺杂区中自对准形成第二P型掺杂区。
  10. 如权利要求9所述的超级结器件的制造方法，其特征在于：在所述器件单元区的周侧还形成包括超级结器件的终端区；所述终端区中包括环绕所述器件单元区的P型环；
    采用相同的离子注入和退火推进工艺同时形成所述第一P型掺杂区和所述P型环；所述P型体区的结深为1微米～5微米。
  11. 如权利要求10所述的超级结器件的制造方法，其特征在于：所述第一N型外延层形成于半导体衬底表面。
  12. 如权利要求11所述的超级结器件的制造方法，其特征在于：所述半导体衬底为硅衬底，所述第一N型外延层为硅外延层，所述P型柱的P型外延层为硅外延层。
  13. 如权利要求10所述的超级结器件，其特征在于：所述第一P型掺杂区的离子注入的注入剂量为2e13cm -2以上，所述P型体区的结深为3微米。
  14. 如权利要求8所述的超级结器件的制造方法，其特征在于：还包括在所述第一N型外延层的底部形成N+掺杂的漏区的步骤；
    所述漏区通过对N+掺杂的所述半导体衬底减薄后直接形成；
    或者，所述漏区通过对所述半导体衬底减薄后再对减薄后的所述半导体衬底进行N+背面离子注入形成。
  15. 如权利要求8所述的超级结器件的制造方法，其特征在于：步骤32中，所述栅介质层为采用热氧化工艺形成的栅氧化层。
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