CN114744027B - 碳化硅ldmosfet器件制造方法及碳化硅ldmosfet器件 - Google Patents

碳化硅ldmosfet器件制造方法及碳化硅ldmosfet器件 Download PDF

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CN114744027B
CN114744027B CN202210652972.3A CN202210652972A CN114744027B CN 114744027 B CN114744027 B CN 114744027B CN 202210652972 A CN202210652972 A CN 202210652972A CN 114744027 B CN114744027 B CN 114744027B
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silicon carbide
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CN114744027A (zh
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余山
赵东艳
王于波
陈燕宁
付振
刘芳
王凯
吴波
邓永峰
刘倩倩
郁文
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Core Kejian Technology Co Ltd
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Abstract

本发明涉及半导体领域，提供一种碳化硅LDMOSFET器件制造方法及碳化硅LDMOSFET器件。所述方法包括：在P型碳化硅衬底上形成碳化硅外延层，在碳化硅外延层上粘接P型硅层；对P型硅层进行刻蚀处理，形成两个延伸至碳化硅外延层的沟槽；分别沿两个沟槽的底部对碳化硅外延层进行离子掺杂形成沟道区；离子掺杂形成N型漂移区，填充沟槽形成P型体区；对填充沟槽进行刻蚀，形成场板隔离介质层；在刻蚀后的填充沟槽内填充多晶硅形成多晶硅栅极；在P型体区和N型漂移区形成源漏区。本发明采用碳化硅衬底，利用碳化硅的高击穿特性，提高器件的击穿电压；通过沟道区将两个多晶硅栅极串联形成组合栅结构，降低器件的导通电阻。

Description

碳化硅LDMOSFET器件制造方法及碳化硅LDMOSFET器件
技术领域
本发明涉及半导体领域，具体地涉及一种碳化硅LDMOSFET器件制造方法以及一种碳化硅LDMOSFET器件。
背景技术
双扩散金属氧化物半导体场效应管(Double-diffused MOS，简称DMOS)具有耐压高、功耗低、大电流驱动能力等特点，广泛采用于电源管理电路中。双扩散金属氧化物半导体场效应管主要有两种类型，垂直双扩散金属氧化物半导体场效应管（Vertical Double-diffused MOSFET，简称VDMOSFET）和横向双扩散金属氧化物半导体场效应管（LateralDouble-diffused MOSFET，简称LDMOSFET）。
对于LDMOSFET，导通电阻和击穿电压是两个重要指标，其外延层的厚度、掺杂浓度、漂移区的长度是最重要的特性参数。通常，可以通过增加沟道长度和漂移区的长度来提高击穿电压，但是这样会增加LDMOSFET的导通电阻。现有的LDMOSFET通常采用硅衬底，由于硅的禁带宽度（1.1eV）不够宽，临界击穿场强（0.3MV/cm）不高，因此器件的击穿电压不高。目前，亟需研究一种高击穿电压、低导通电阻的LDMOSFET器件。
发明内容
本发明实施方式的目的是提供一种碳化硅LDMOSFET器件制造方法及碳化硅LDMOSFET器件，以提高击穿电压、降低导通电阻。
为了实现上述目的，本发明第一方面提供一种碳化硅LDMOSFET器件制造方法，所述方法包括：
在P型碳化硅衬底上形成碳化硅外延层，在碳化硅外延层上粘接P型硅层；
对粘接的P型硅层进行刻蚀处理，在P型硅层内形成两个延伸至碳化硅外延层的沟槽；
分别沿两个沟槽的底部对碳化硅外延层进行离子掺杂形成沟道区；
对两个沟槽外侧的P型硅层进行离子掺杂形成N型漂移区，在两个沟槽内填充氧化物形成填充沟槽，使得两个填充沟槽之间的P型硅层形成为P型体区；
对两个填充沟槽进行刻蚀处理，去除两个填充沟槽内的一部分氧化物，两个填充沟槽内预留的氧化物形成为场板隔离介质层；
在刻蚀后的填充沟槽内填充多晶硅形成多晶硅栅极；
在P型体区和N型漂移区形成源漏区。
进一步地，所述对粘接的P型硅层进行刻蚀处理，在P型硅层内形成两个延伸至碳化硅外延层的沟槽，包括：在P型硅层上涂覆光刻胶，通过光刻处理形成刻蚀窗口；沿刻蚀窗口对P型硅层进行刻蚀处理，形成延伸至碳化硅外延层的沟槽。
进一步地，所述分别沿两个沟槽的底部对碳化硅外延层进行离子掺杂形成沟道区，包括：采用离子注入工艺在沟槽底部的碳化硅外延层注入P型离子，形成与P型体区相接的P型碳化硅掺杂区，P型碳化硅掺杂区作为P型体区与N型漂移区之间的沟道区。
进一步地，所述对两个沟槽外侧的P型硅层进行离子掺杂形成N型漂移区，在两个沟槽内填充氧化物形成填充沟槽，使得两个填充沟槽之间的P型硅层形成为P型体区，包括：在两个沟槽外侧的P型硅层中注入N型离子，形成N型漂移区；在两个沟槽内填充氧化物形成填充沟槽；对填充沟槽进行平坦化处理，使得两个填充沟槽之间的P型硅层形成为P型体区。
进一步地，所述对两个填充沟槽进行刻蚀处理，去除两个填充沟槽内的一部分氧化物，两个填充沟槽内预留的氧化物形成为场板隔离介质层，包括：
对填充沟槽进行光刻及干法刻蚀处理，去除两个填充沟槽内的靠近P型体区的氧化物，预留沟槽底部的氧化物以及靠近N型漂移区的氧化物，预留的氧化物形成为场板隔离介质层。
进一步地，所述在刻蚀后的填充沟槽内填充多晶硅形成多晶硅栅极，包括：在两个填充沟槽的靠近P型体区的一侧生长氧化物形成栅氧化层；在刻蚀后的填充沟槽内沉积多晶硅，同时对多晶硅进行掺杂，形成两个多晶硅栅极。
进一步地，所述在P型体区和N型漂移区形成源漏区，包括：采用光刻及离子注入工艺，在P型体区形成源区，在N型漂移区形成漏区。
进一步地，所述P型碳化硅衬底和所述碳化硅外延层的材料均为4H-SiC。
本发明第二方面提供一种碳化硅LDMOSFET器件，包括P型衬底、P型体区、N型漂移区以及栅极，还包括：沟道区，所述沟道区与P型体区相接；所述P型衬底为P型碳化硅衬底，所述P型碳化硅衬底上形成有碳化硅外延层；所述沟道区通过以下方式形成：在碳化硅外延层上粘接P型硅层；对粘接的P型硅层进行刻蚀处理，在P型硅层内形成两个延伸至碳化硅外延层的沟槽；分别沿两个沟槽的底部对碳化硅外延层进行离子掺杂，形成两个与P型体区相接的沟道区。
进一步地，所述P型体区和N型漂移区通过以下方式形成：
对两个沟槽外侧的P型硅层进行离子掺杂形成N型漂移区，在两个沟槽内填充氧化物形成填充沟槽，使得两个填充沟槽之间的P型硅层形成为P型体区。
进一步地，还包括：场板隔离介质层，所述场板隔离介质层与N型漂移区相接；所述场板隔离介质层通过以下方式形成：对填充沟槽进行选择性刻蚀，去除两个填充沟槽内的靠近P型体区的氧化物，预留沟槽底部的氧化物以及靠近N型漂移区的氧化物，预留的氧化物形成为场板隔离介质层。
进一步地，所述栅极有两个，两个栅极通过以下方式形成：在两个填充沟槽的靠近P型体区的一侧生长氧化物形成栅氧化层；在刻蚀后的填充沟槽内沉积多晶硅，同时对多晶硅进行掺杂，形成两个多晶硅栅极。
进一步地，所述P型体区内形成有源区，所述N型漂移区内形成有漏区。
进一步地，所述P型碳化硅衬底和所述碳化硅外延层的材料均为4H-SiC。
本发明提供的碳化硅LDMOSFET器件制造方法，具有以下优势：
（1）采用碳化硅衬底，在碳化硅衬底上外延形成碳化硅外延层，在碳化硅外延层形成沟道区，从而形成碳化硅LDMOSFET器件。碳化硅LDMOSFET利用碳化硅材料的高击穿特性，相较于硅衬底的LDMOSFET，提高了器件的击穿电压。
（2）在碳化硅外延层上粘接一硅层，通过对粘接的硅层进行刻蚀形成形成体区和漂移区，不需要采用高压离子注入等难以控制的工艺来形成LDMOSFET的高压阱（N阱和P阱），降低了制造难度和工艺成本。
（3）通过对粘接的硅层进行刻蚀形成两个延伸至碳化硅外延层的沟槽，通过填充沟槽形成两个多晶硅栅极，通过碳化硅外延层的沟道区将两个多晶硅栅极串联形成组合栅结构，可降低器件的导通电阻。
（4）通过对粘接的硅层进行刻蚀形成沟槽，在沟槽内填充氧化物形成填充沟槽，对填充沟槽进行选择性刻蚀形成与漂移区相接的场板隔离介质层，可降低器件的表面电场，进一步提高击穿电压。
附图说明
附图是用来提供对本发明实施方式的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明实施方式，但并不构成对本发明实施方式的限制。在附图中：
图1是本发明实施方式提供的碳化硅LDMOSFET器件制造方法的流程图；
图2a至图2g是本发明实施方式提供的碳化硅LDMOSFET器件的制造过程示意图。
附图标记说明
1-沟槽，2-沟道区，3-氧化物，4-场板隔离介质层，
5-栅氧化层，6-多晶硅栅极。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
图1是本发明实施方式提供的碳化硅LDMOSFET器件制造方法的流程图。如图1所示，本实施方式提供一种碳化硅LDMOSFET器件制造方法，所述方法包括以下步骤：
S1.在P型碳化硅衬底上形成碳化硅外延层，在碳化硅外延层上粘接P型硅层。
参照图2a，在P型碳化硅衬底SUB-SiC上外延SiC材料形成碳化硅外延层EPI-SiC，在碳化硅外延层EPI-SiC上粘接P型硅晶圆，对P型硅晶圆进行减薄处理形成需要厚度的P型硅层P-Si。其中，P型碳化硅衬底和碳化硅外延层的材料均为4H-SiC。4H-SiC的禁带宽度为3.25eV，临界击穿场强为3.0MV/cm，SiC材料具有高击穿特性。然而，Si的禁带宽度为1.1eV，临界击穿场强为0.3MV/cm。因此，利用SiC作为LDMOSFET的衬底，相较于Si衬底能够进一步提高LDMOSFET器件的击穿电压。
S2.对粘接的P型硅层进行刻蚀处理，在P型硅层内形成两个延伸至碳化硅外延层的沟槽。
参照图2b，在P型硅层P-Si上涂覆光刻胶，通过光刻处理形成刻蚀窗口，沿刻蚀窗口对P型硅层进行刻蚀处理，形成两个延伸至碳化硅外延层EPI-SiC的沟槽1，沟槽1将P型硅层P-Si隔断为三部分，中间的P-Si作为后续的P型体区，两侧的P-Si作为后续的漂移区。
S3.分别沿两个沟槽的底部对碳化硅外延层进行离子掺杂形成沟道区。
由于碳化硅是一种本征半导体硅，电阻较大，因此需要通过沟道区来促使P型体区的载流子移动。
参照图2c，采用离子注入工艺在沟槽1底部的碳化硅外延层EPI-SiC注入P型离子（例如硼离子）形成P型碳化硅掺杂区，所述P型碳化硅掺杂区与后续的P型体区相接，作为后续的P型体区与漂移区之间的沟道区2。
S4.对两个沟槽外侧的P型硅层进行离子掺杂形成N型漂移区，在两个沟槽内填充氧化物形成填充沟槽，使得两个填充沟槽之间的P型硅层形成为P型体区。
参照图2d，采用离子注入工艺，在两个沟槽外侧的P型硅层（图2c两侧的P-Si）中注入N型离子（例如磷离子），形成N型漂移区NRF。在两个沟槽内填充氧化物3（例如二氧化硅）形成填充沟槽，对填充沟槽进行平坦化处理，使得两个填充沟槽之间的P型硅层（图2c中间的P-Si）形成为P型体区P-body。需要注意的是，在对沟槽外侧的P型硅层进行离子注入前，采用光刻胶覆盖沟槽以及沟槽之间的P型硅层，使邻近NRF的沟槽的底部暴露。在对P型硅层进行N型离子注入的同时，N型离子从暴露的沟槽底部扩散至沟道区2，因此邻近NRF的沟道区的载流子为N型，邻近P-body的沟道区的载流子为P型，沟道区2作为P-body与NRF之间的连通沟道。
S5.对两个填充沟槽进行刻蚀处理，去除两个填充沟槽内的一部分氧化物，两个填充沟槽内预留的氧化物形成为场板隔离介质层。
参照图2e，对填充沟槽进行光刻及干法刻蚀处理（选择性刻蚀），去除两个填充沟槽内的靠近P型体区P-body的氧化物，预留沟槽底部的氧化物以及靠近N型漂移区NRF的氧化物，预留的氧化物形成为场板隔离介质层4。
S6.在刻蚀后的填充沟槽内填充多晶硅形成多晶硅栅极。
参照图2f，在两个填充沟槽的靠近P型体区P-body的一侧生长氧化物形成栅氧化层5，在刻蚀后的填充沟槽内沉积多晶硅，同时对多晶硅进行掺杂，形成两个多晶硅栅极6。
S7.在P型体区和N型漂移区形成源漏区。
参照图2g，采用光刻及离子注入工艺，在P型体区P-body形成源区N+，在N型漂移区NRF形成漏区N+。
本发明实施方式的碳化硅LDMOSFET器件制造方法，具有以下优势：
（1）采用碳化硅衬底，在碳化硅衬底上外延形成碳化硅外延层，在碳化硅外延层形成沟道区，从而形成碳化硅LDMOSFET器件。碳化硅LDMOSFET利用碳化硅材料的高击穿特性，相较于硅衬底的LDMOSFET，提高了器件的击穿电压。
（2）在碳化硅外延层上粘接一硅层，通过对粘接的硅层进行刻蚀形成形成体区和漂移区，不需要采用高压离子注入等难以控制的工艺来形成LDMOSFET的高压阱（N阱和P阱），降低了制造难度和工艺成本。
（3）通过对粘接的硅层进行刻蚀形成两个延伸至碳化硅外延层的沟槽，通过填充沟槽形成两个多晶硅栅极，通过碳化硅外延层的沟道区将两个多晶硅栅极串联形成组合栅结构，可降低器件的导通电阻。
（4）通过对粘接的硅层进行刻蚀形成沟槽，在沟槽内填充氧化物形成填充沟槽，对填充沟槽进行选择性刻蚀形成与漂移区相接的场板隔离介质层，可降低器件的表面电场，进一步提高击穿电压。
本发明实施方式还提供一种碳化硅LDMOSFET器件。参照图2g，所述碳化硅LDMOSFET器件包括：P型衬底、P型体区P-body、N型漂移区NRF以及多晶硅栅极6，P型体区P-body内形成有源区N+，N型漂移区NRF内形成有漏区N+。所述碳化硅LDMOSFET器件还包括沟道区2和场板隔离介质层4，所述沟道区2与P型体区P-body相接，所述场板隔离介质层4与N型漂移区NRF相接。所述P型衬底为P型碳化硅衬底SUB-SiC，P型碳化硅衬底SUB-SiC上形成有碳化硅外延层EPI-SiC。P型碳化硅衬底和碳化硅外延层的材料均为4H-SiC。
参照图2a至图2f，沟道区2通过以下方式形成：在碳化硅外延层EPI-SiC上粘接P型硅层P-Si；对粘接的P型硅层进行刻蚀处理，在P型硅层内形成两个延伸至碳化硅外延层的沟槽1；分别沿两个沟槽的底部对碳化硅外延层EPI-SiC进行离子掺杂，形成两个与P型体区P-body相接的沟道区2。P型体区P-body和N型漂移区NRF通过以下方式形成：采用离子注入工艺，在两个沟槽外侧剩余的P型硅层（图2c两侧的P-Si）中注入N型离子，形成N型漂移区NRF。在两个沟槽内填充氧化物3形成填充沟槽，使得两个填充沟槽之间的P型硅层形成为P型体区P-body。场板隔离介质层4通过以下方式形成：对填充沟槽进行选择性刻蚀，去除两个填充沟槽内的靠近P型体区P-body的氧化物，预留沟槽底部的氧化物以及靠近N型漂移区NRF的氧化物，预留的氧化物形成为场板隔离介质层4。所述多晶硅栅极有两个，两个多晶硅栅极6通过以下方式形成：在两个填充沟槽的靠近P型体区P-body的一侧生长氧化物形成栅氧化层5；在刻蚀后的填充沟槽内沉积多晶硅，同时对多晶硅进行掺杂，形成两个多晶硅栅极6。
本发明实施方式提供的碳化硅LDMOSFET器件，采用碳化硅衬底，在碳化硅衬底上外延形成碳化硅外延层，在碳化硅外延层形成沟道区，利用碳化硅材料的高击穿特性，提高器件的击穿电压。本发明通过对粘接的硅层进行刻蚀形成两个延伸至碳化硅外延层的沟槽，通过填充沟槽形成两个多晶硅栅极，通过碳化硅外延层的沟道区将两个多晶硅栅极串联形成组合栅结构，可降低器件的导通电阻；通过在沟槽内填充氧化物形成填充沟槽，对填充沟槽进行选择性刻蚀形成与漂移区相接的场板隔离介质层，可降低器件的表面电场，进一步提高击穿电压。
以上结合附图详细描述了本发明的可选实施方式，但是，本发明实施方式并不限于上述实施方式中的具体细节，在本发明实施方式的技术构思范围内，可以对本发明实施方式的技术方案进行多种简单变型，这些简单变型均属于本发明实施方式的保护范围。另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合。为了避免不必要的重复，本发明实施方式对各种可能的组合方式不再另行说明。

Claims (13)

1.一种碳化硅LDMOSFET器件制造方法，其特征在于，所述方法包括：
在P型碳化硅衬底上形成碳化硅外延层，在碳化硅外延层上粘接P型硅层；
对粘接的P型硅层进行刻蚀处理，在P型硅层内形成两个延伸至碳化硅外延层的沟槽；
分别沿两个沟槽的底部对碳化硅外延层进行离子掺杂形成沟道区；
对两个沟槽外侧的P型硅层进行离子掺杂形成N型漂移区，在两个沟槽内填充氧化物形成填充沟槽，使得两个填充沟槽之间的P型硅层形成为P型体区；
对两个填充沟槽进行刻蚀处理，去除两个填充沟槽内的一部分氧化物，两个填充沟槽内预留的氧化物形成为场板隔离介质层；
在刻蚀后的填充沟槽内填充多晶硅形成多晶硅栅极；
在P型体区和N型漂移区形成源漏区；
其中，所述分别沿两个沟槽的底部对碳化硅外延层进行离子掺杂形成沟道区，包括：采用离子注入工艺在沟槽底部的碳化硅外延层注入P型离子，形成与P型体区相接的P型碳化硅掺杂区，将P型碳化硅掺杂区作为P型体区与N型漂移区之间的沟道区。
2.根据权利要求1所述的碳化硅LDMOSFET器件制造方法，其特征在于，所述对粘接的P型硅层进行刻蚀处理，在P型硅层内形成两个延伸至碳化硅外延层的沟槽，包括：
在P型硅层上涂覆光刻胶，通过光刻处理形成刻蚀窗口；
沿刻蚀窗口对P型硅层进行刻蚀处理，形成延伸至碳化硅外延层的沟槽。
3.根据权利要求1所述的碳化硅LDMOSFET器件制造方法，其特征在于，所述对两个沟槽外侧的P型硅层进行离子掺杂形成N型漂移区，在两个沟槽内填充氧化物形成填充沟槽，使得两个填充沟槽之间的P型硅层形成为P型体区，包括：
在两个沟槽外侧的P型硅层中注入N型离子，形成N型漂移区；
在两个沟槽内填充氧化物形成填充沟槽；
对填充沟槽进行平坦化处理，使得两个填充沟槽之间的P型硅层形成为P型体区。
4.根据权利要求1所述的碳化硅LDMOSFET器件制造方法，其特征在于，所述对两个填充沟槽进行刻蚀处理，去除两个填充沟槽内的一部分氧化物，两个填充沟槽内预留的氧化物形成为场板隔离介质层，包括：
对填充沟槽进行光刻及干法刻蚀处理，去除两个填充沟槽内的靠近P型体区的氧化物，预留沟槽底部的氧化物以及靠近N型漂移区的氧化物，预留的氧化物形成为场板隔离介质层。
5.根据权利要求4所述的碳化硅LDMOSFET器件制造方法，其特征在于，所述在刻蚀后的填充沟槽内填充多晶硅形成多晶硅栅极，包括：
在两个填充沟槽的靠近P型体区的一侧生长氧化物形成栅氧化层；
在刻蚀后的填充沟槽内沉积多晶硅，同时对多晶硅进行掺杂，形成两个多晶硅栅极。
6.根据权利要求1所述的碳化硅LDMOSFET器件制造方法，其特征在于，所述在P型体区和N型漂移区形成源漏区，包括：
采用光刻及离子注入工艺，在P型体区形成源区，在N型漂移区形成漏区。
7.根据权利要求1所述的碳化硅LDMOSFET器件制造方法，其特征在于，所述P型碳化硅衬底和所述碳化硅外延层的材料均为4H-SiC。
8.一种碳化硅LDMOSFET器件，包括P型衬底、P型体区、N型漂移区以及栅极，其特征在于，还包括：沟道区，所述沟道区与P型体区相接；
所述P型衬底为P型碳化硅衬底，所述P型碳化硅衬底上形成有碳化硅外延层；
所述沟道区通过以下方式形成：
在碳化硅外延层上粘接P型硅层；
对粘接的P型硅层进行刻蚀处理，在P型硅层内形成两个延伸至碳化硅外延层的沟槽；
采用离子注入工艺在沟槽底部的碳化硅外延层注入P型离子，形成与P型体区相接的P型碳化硅掺杂区，将P型碳化硅掺杂区作为P型体区与N型漂移区之间的沟道区。
9.根据权利要求8所述的碳化硅LDMOSFET器件，其特征在于，所述P型体区和N型漂移区通过以下方式形成：
对两个沟槽外侧的P型硅层进行离子掺杂形成N型漂移区，在两个沟槽内填充氧化物形成填充沟槽，使得两个填充沟槽之间的P型硅层形成为P型体区。
10.根据权利要求9所述的碳化硅LDMOSFET器件，其特征在于，还包括：场板隔离介质层，所述场板隔离介质层与N型漂移区相接；
所述场板隔离介质层通过以下方式形成：
对填充沟槽进行选择性刻蚀，去除两个填充沟槽内的靠近P型体区的氧化物，预留沟槽底部的氧化物以及靠近N型漂移区的氧化物，预留的氧化物形成为场板隔离介质层。
11.根据权利要求10所述的碳化硅LDMOSFET器件，其特征在于，所述栅极有两个，两个栅极通过以下方式形成：
在两个填充沟槽的靠近P型体区的一侧生长氧化物形成栅氧化层；
在刻蚀后的填充沟槽内沉积多晶硅，同时对多晶硅进行掺杂，形成两个多晶硅栅极。
12.根据权利要求8所述的碳化硅LDMOSFET器件，其特征在于，所述P型体区内形成有源区，所述N型漂移区内形成有漏区。
13.根据权利要求8所述的碳化硅LDMOSFET器件，其特征在于，所述P型碳化硅衬底和所述碳化硅外延层的材料均为4H-SiC。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511528A (zh) * 2018-04-11 2018-09-07 西安电子科技大学 具有深漏区的横向双扩散金属氧化物复合半导体场效应管及其制作方法
CN114038915A (zh) * 2021-10-28 2022-02-11 江苏格瑞宝电子有限公司 半导体功率器件及其制备方法
CN114038914A (zh) * 2021-10-28 2022-02-11 江苏格瑞宝电子有限公司 双重耐压半导体功率器件及其制备方法
CN114420761A (zh) * 2022-03-30 2022-04-29 成都功成半导体有限公司 一种耐高压碳化硅器件及其制备方法

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US20100090274A1 (en) * 2008-10-10 2010-04-15 Force Mos Technology Co. Ltd. Trench mosfet with shallow trench contact

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511528A (zh) * 2018-04-11 2018-09-07 西安电子科技大学 具有深漏区的横向双扩散金属氧化物复合半导体场效应管及其制作方法
CN114038915A (zh) * 2021-10-28 2022-02-11 江苏格瑞宝电子有限公司 半导体功率器件及其制备方法
CN114038914A (zh) * 2021-10-28 2022-02-11 江苏格瑞宝电子有限公司 双重耐压半导体功率器件及其制备方法
CN114420761A (zh) * 2022-03-30 2022-04-29 成都功成半导体有限公司 一种耐高压碳化硅器件及其制备方法

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