CN115241283A - 集成的平面-沟道栅极功率mosfet - Google Patents

集成的平面-沟道栅极功率mosfet Download PDF

Info

Publication number
CN115241283A
CN115241283A CN202210390724.6A CN202210390724A CN115241283A CN 115241283 A CN115241283 A CN 115241283A CN 202210390724 A CN202210390724 A CN 202210390724A CN 115241283 A CN115241283 A CN 115241283A
Authority
CN
China
Prior art keywords
channel
gate
conductivity type
epitaxial layer
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210390724.6A
Other languages
English (en)
Inventor
李文军
管灵鹏
王健
陈凌兵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha and Omega Semiconductor Cayman Ltd
Original Assignee
Alpha and Omega Semiconductor Cayman Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Cayman Ltd filed Critical Alpha and Omega Semiconductor Cayman Ltd
Publication of CN115241283A publication Critical patent/CN115241283A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

晶体管器件及其制造方法，包括重掺杂第一导电类型的衬底和在衬底顶部轻掺杂第一导电类型的外延层。在外延层中形成掺杂有第二导电类型的本体区域，其中第二导电类型与第一导电类型相对，并且在外延层的本体区域中形成掺杂有第一导电类型的源区域。具有平面栅极部分的集成平面沟道栅极形成在外延层的表面上，该外延层与在外延层中形成的栅极沟道部分相连。

Description

集成的平面-沟道栅极功率MOSFET
技术领域
本发明的各个方面通常涉及晶体管，更具体地说，涉及垂直双扩散金属氧化物半导体(VDMOS)场效应晶体管和沟道栅金属氧化物半导体场效应晶体管(MOSFET)。
背景技术
消费市场需要更小的设备。此外，计算能力和性能随着可安装在单个晶圆上的晶体管数量的增加而增加。减小晶体管节距，降低导通电阻(Rdson)，可以降低制冷用量和功耗。
目前对于高压应用来说，平面晶体管的间距存在限制。当共用栅极的本体区之间的距离减小时，两个本体区之间的JFET区中电荷载流子的横向耗尽率增大。这导致从漏极到源极(RDS)的电阻增加。解决这个问题的办法是增加JFET区域的掺杂浓度，但由此产生的尺寸减小是有限的。
正是在这一前提下，提出了本发明的各种实施例。
发明内容
本发明公开了一种晶体管器件，包括：一个重掺杂第一导电类型的衬底；一个轻掺杂第一导电类型的外延层，形成在衬底上；一个掺杂第二导电类型的本体区，形成在外延层中，其中第二导电类型与第一导电类型相反；一个掺杂第一导电类型的源极区，形成在外延层的本体区中；一个集成平面-沟道栅极，其具有一平面栅极部分形成在外延层的表面上，与在外延层中的沟道中形成的沟道栅极部分相连，其中衬底中的沟道栅极部分底部的深度，小于本体区的最低掺杂深度。
其中，沟道栅极部分形成在外延层的本体区中。
其中，还包括一个局域化的JFET注入区，重掺杂第一导电类型，形成在沟道栅极部分的底部和边缘周围。
其中，外延层的轻掺杂第一导电类型的区域，分隔局域化的JFET注入和本体区。
如权利要求1所述的晶体管器件，还包括一个在沟道底部的厚绝缘层，其中沟道底部的厚绝缘层，比沟道至少一边的绝缘层更厚。
如权利要求1所述的晶体管器件，其中外延层还包括可选的掺杂第二导电类型的本体区立柱，以及轻掺杂第一导电类型的外延层立柱。
其中，所述栅极沟道部分的沟道侧壁与所述栅极沟道部分的沟道底面以大于90度的角度相交。
其中，栅极沟道部分具有0.3至0.8微米之间的沟道深度。
其中，在栅极沟道部分的沟道底部的绝缘层厚度，是在沟道边缘的绝缘层厚度的1.5至2倍。
本发明还公开了一种制备晶体管器件的方法，包括：制备一个轻掺杂第一导电类型的外延层，在重掺杂第一导电类型的衬底上，其中第一导电类型与第二导电类型相反；在外延层中制备一个沟道；在外延层的表面上和沟道中，制备一个绝缘层；并且通过在外延层表面和沟道中的绝缘层上形成连续导电层来创建集成平面沟道栅极。
其中，还包括在外延层表面和沟道中形成绝缘层之前，在沟道底部形成厚的底部绝缘层。
其中，在形成绝缘层之前，使用第一导电类型掺杂沟道的侧面和底部，以在沟道的侧面和底部周围创建重掺杂第一导电类型的局部JFET注入区。
其中，用第二导电线路进一步掺杂一个外延区，以形成本体区。
其中，沟道形成在外延层的本体区中。
其中，本体区还包括制备分别掺杂第一导电类型和第二导电类型的交替立柱。
其中，本体区掺杂得比沟道底部更深。
其中，还包括在外延层的本体区中制备一个源极区。
其中，在沟道底部的源极层厚度是沟道边缘的绝缘层厚度的1.5至2倍。
其中，形成沟道还包括形成沟道的侧壁，该侧壁以大于90度的角度与沟道的底部相交。
附图说明
阅读以下详细说明并参照以下附图之后，本发明的其他特征和优势将显而易见：
图1表示依据本发明的各个方面，一种集成的平面-沟道栅极晶体管器件的侧面剖视图。
图2显示依据本发明的各个方面，集成的平面-沟道栅极晶体管器件的一种可选配置的侧面剖视图。
图3表示依据本发明的各个方面，具有集成的平面-沟道栅极的超级结晶体管器件的侧面剖视图。
图4A显示依据本发明的各个方面，一个重掺杂第一导电类型离子的衬底和一个较轻掺杂的外延层。
图4B表示依据本发明的各个方面，在外延层中制备一个沟道用于集成的平面-沟道栅极晶体管器件的侧面剖视图。
图4C表示依据本发明的各个方面，制备一个局域化的JFET注入区的侧面剖面图。
图4D表示依据本发明的各个方面，在沟道底部制备一个厚的底部绝缘层的剖面图。
图4E显示依据本发明的各个方面，制备具有一个平面部分和一个沟道部分的栅极绝缘层的剖面侧视图。
图4F表示依据本发明的各个方面，具有连续平面部分和沟道部分的导电层的集成平面-沟道栅极的形成的剖面侧视图。
图4G表示依据本发明的各个方面，具有相连平面栅极部分和沟道栅极部分的栅极的图案化导电层，制备集成平面-沟道栅极的形成的剖面侧视图。
图4H显示依据本发明的各个方面，制备本体区，用于具有集成的平面-沟道栅极的晶体管器件的剖面侧视图。
图4I表示依据本发明的各个方面，制备源极区，用于具有集成的平面-沟道栅极的晶体管器件的剖面侧视图。
图4J显示依据本发明的各个方面，在集成的平面-沟道栅极晶体管器件上制备其他结构的剖面侧视图。
具体实施方式
尽管为了说明的目的，以下详细描述包含许多特定细节，但本领域的普通技术人员将理解，对以下细节的许多变化和修改都在本发明的范围内。因此，下文描述的本发明的示例性实施例对所要求保护的发明没有任何一般性损失，也没有施加限制。
本发明涉及掺杂有第一导电类型或第二导电类型离子的硅。第一导电类型的离子可以是第二导电类型的相反离子。例如，第一导电类型的离子可以是n型，其在掺杂到硅中时产生电荷载流子。第一种导电类型的离子包括磷、锑、铋、锂和砷。第二导电性的离子可以是p型，当掺杂到硅中时，其为电荷载流子创建空穴，并且以这种方式被称为与n型相反。p型离子包括硼、铝、镓和铟。尽管上述描述将n型称为第一导电类型，将p型称为第二导电类型，但本发明并不限于此，p型可以是第一导电类型，而n型可以是第二导电类型。
在下面的详细描述中，参考附图，附图构成了本发明的一部分，并且在附图中通过图示的方式表示出了可以实施本发明的特定实施例。为了方便起见，在指定导电性或净杂质载流子类型(p或n)之后使用+或–通常指半导体材料内指定类型的净杂质载流子的相对浓度。一般而言，n+材料具有比n材料更高的n型净掺杂物(例如电子)浓度，并且n材料具有比n-材料更高的载流子浓度。类似地，p+材料具有比p材料更高的p型净掺杂物(例如空穴)浓度，并且p材料具有比p-材料更高的浓度。要注意的是，相关的是载流子的净浓度，而不一定是掺杂物。例如材料可以重掺杂n型掺杂物，但是如果材料也充分反掺杂p型掺杂物，则材料仍然具有相对低的净载流子浓度。如本文所用，小于约1016/cm3的掺杂物浓度可被视为“轻掺杂”，而大于约1017/cm3的掺杂物浓度可被视为“重掺杂”。
引言
根据本发明的各个方面，可通过创建具有连续栅极部分和沟道部分的集成平面沟道栅极来改善晶体管器件的间距。集成的平面沟道栅极允许更小的平面栅极尺寸，并减少RDS。先前的器件已经实现了由绝缘层分离并通过导线电耦合的平面栅极和沟道栅极的组合。这些先前的器件由大的深沟道制成，因此不可能形成在平面栅极部分和沟道栅极部分之间相连的具有平面栅极的集成栅极沟道。先前器件用绝缘层和导电层填充较大沟道导致栅极不够平坦。平面栅极和沟道栅极之间的中间绝缘层用于创建平面栅极。由于沟道栅极和平面栅极的对准困难，通过平面栅极和沟道栅极之间的绝缘层创建开口以电耦合两个栅极是不切实际的。因此，平面栅极和沟道栅极使用引线进行电气连接，而不是两个栅极的导电层之间的直接接触。现有器件中两个栅极的深沟道和间接连接增加了现有器件的复杂性，并且使得缩小现有器件的尺寸变得困难。
为了解决这个问题，设计了一种晶体管器件及其制造方法，该晶体管器件包括重掺杂第一导电类型的衬底和在衬底顶部轻掺杂第一导电类型的外延层。在外延层中形成掺杂有与第一导电类型相反的第二导电类型的本体区域，并且在外延层的本体区域中形成掺杂有第一导电类型的源极区域。该器件包括集成平面沟道栅极，该集成平面沟道栅极具有形成在外延层的表面上的平面栅极部分，该平面栅极部分与在外延层中的沟道中形成的沟道栅极部分相连。在一些实施方案中，该器件还可包括局部JFET注入区，该区域重掺杂有围绕沟道栅极部分的底部和侧面形成的第一导电类型。轻掺杂第一导电类型的外延层的区域可分离局部JFET注入物和本体区域。在一些实施方式中，沟道栅极部分可以形成在外延层的本体区域中。
在一些其它实施例中，衬底中沟道栅极部分的底部深度可小于本体区域的最低掺杂深度。在其他实施例中，沟道栅极部分可通过栅极沟道底部的厚绝缘层与外延层绝缘，该厚绝缘层比栅极沟道至少一侧的绝缘层厚。在又一个其它实施例中，外延层可进一步包括掺杂有第二导电类型的交替体区柱和轻掺杂有第一导电类型的形成所谓超结结构的外延层柱。在一些实施例中，装置的栅极沟道部分的沟道的侧壁可以与栅极沟道部分的沟道的底部以大于90度的角度相交。晶体管器件的栅极沟道部分的沟道深度可以在0.3到0.8微米之间。在本发明的一些实施例中，该器件的栅极沟道部分的沟道底部绝缘层的厚度可以是沟道一侧的绝缘层厚度的1.5到2倍。
器件
图1表示了根据本发明的各个方面，集成的平面沟道栅晶体管器件的侧面剖视图。如图所示，集成的平面沟道栅晶体管器件包括重掺杂有第一导电类型离子的衬底101。外延层102可以形成在衬底101的顶部。作为示例，而非限制，外延层102可使用外延生长在衬底101的表面上生长或以其他方式沉积在衬底的表面上。在外延层102中形成沟道103。在一些实施例中，沟道103的侧面和底部周围的区域可重掺杂第一导电类型的离子，形成局部JFET注入区域108。介电层106形成在衬底的表面上，以将集成平面沟道栅极的平面栅极部分107与外延层102电绝缘。介电层106还排列沟道103的侧壁和底部，为集成平面沟道栅极的沟道部分的侧壁105和底部104创建绝缘层。在一些实施方案中，沟道103底部104上的绝缘层的厚度可以是本文中称为厚底部绝缘体的沟道侧面103上的绝缘层的1.5到2倍。绝缘层可由诸如氧化硅的介电材料组成。平面栅极部分107可以通过图案化形成在绝缘层106的表面上的导电层而形成。导电层的一部分填充沟道103中未被介电层106占据的部分，并且通过沟道的侧壁105和底部104上的部分绝缘层与外延层102绝缘。导电层创建在栅极的平面部分107和栅极的沟道部分112之间连接的集成平面沟道栅极。导电层可由多晶硅或其他导电材料(例如氮化钛(TiN)或钨)组成。栅极触点113耦合到导电层107。由于栅极的平面栅极部分107和沟道栅极部分112的连续性，沟道部分112不具有单独的栅极接触。取而代之的是，沟道部分112由于与栅极的平面栅极部分107相连而保持在栅极电势水平。可以在外延层102中形成一个或多个本体区域109。源极区110可以形成在外延层102的主体109中。源触点111将源极区域耦合到源极，并且还可以包括本体短路触点。可在基板101的底部形成漏极金属114。漏极触点115可耦合到漏极金属114上。
在操作期间，栅极触点113处的栅极电势允许电流通过晶体管器件传导。例如，在不限制N型MOSFET配置的情况下，施加到漏极触点115的电流通过漏极金属114、衬底101和外延层102传导。来自外延层102的电荷载流子与本体区域109中的相反电荷空穴结合，从而允许电流传导到源极区域110和源极触点111。
图2表示根据本发明各个方面，集成的平面-沟道栅晶体管器件的可选实施例的侧面剖视图。在图2所示的实施例中，本体区域209接触一个局域化的结型场效应晶体管(JFET)注入区域208。此外，源极区210比在没有相交本体区域和集成的平面-沟道栅极的实施例中更靠近栅极沟道203。如图所示，两个本体区域209布置得非常靠近沟道203，使得区域在沟道203下方相交。集成的平面-沟道栅极的平面部分207比在沟道下方不包括相交本体区域的实施例中短。集成的平面沟道栅极和局部JFET植入物208允许晶体管器件的节距减小，其原因在于集成的平面-沟道栅极的平面部分207的宽度可以减小而不会显著影响器件的RDS。
图3表示根据本发明的各个方面，具有集成的平面-沟道栅极的超级结晶体管器件的侧面剖视图。如图所示，该器件的本体区域309包括掺杂有第二导电类型的离子的柱320，该第二导电类型的离子终止于衬底101附近。外延层302形成掺杂有第一导电类型的离子的柱。因此，掺杂体柱320和掺杂有第一导电性离子302的外延层区域的组合为超级结器件在外延层中分别创建掺杂有第一导电性类型和第二导电性类型的交替柱。
制备方法
图4A-4J表示根据本发明各个方面，制造集成的平面-沟道栅极晶体管器件的方法的侧面剖视图。图4A表示根据本发明的各个方面，重掺杂第一导电类型离子的衬底401和更轻掺杂的外延层402。衬底401可在1x1019和1x1020cm-3之间的离子浓度下掺杂。衬底可由例如但不限于硅、碳化硅、氮化镓或砷化镓组成。外延层402可以形成在衬底401的表面上。外延层402可以通过诸如气相外延之类的过程生长在外延层401的上表面上。外延层402可在形成期间或之后轻掺杂第一导电类型的离子。外延层402可在1x1017和6x1017 cm-3之间的离子浓度下掺杂。
图4B表示根据本发明的各个方面，用于集成平面沟道栅极晶体管器件的外延层402中沟道403的形成的侧面剖视图。最初，包括氧化硅层407、氮化硅层406、氧化硅层405堆栈的硬掩模可沉积在外延层402的表面上。氧化层407、405和氮化物层406可通过化学气相沉积技术(CVD)形成，以形成SiO2和氮化硅，或通过热氧化过程形成SiO2。在硬掩模的表面上形成掩模图案404。掩模图案404可使用光刻技术创建或通过机械掩模工艺应用。掩模图案404包括沟道间隙408。对掩模图案和硬掩模应用刻蚀工艺，例如使用磷酸或其他此类选择刻蚀剂的等离子体干法刻蚀或湿法刻蚀。硬掩模在沟道间隙408处刻蚀掉，在沟道间隙中暴露外延层402。外延层402随后可通过诸如深反应离子刻蚀(DRIE)的等离子体刻蚀技术经由沟道间隙408刻蚀至所需深度。所创建的沟道403的深度可以在外延层的0.3微米到0.8微米之间。或者，可以基于期望的器件特性来选择沟道的深度。对沟道深度的一般影响是，随着两个P型本体区域之间的间距减小，沟道深度增加。沟道403的侧面可以形成一定角度，使得沟道的侧面与沟道的底部以大于90度的角度相交。例如，在不受限制的情况下，沟道的一侧与沟道底表面形成的角度可以在101度和105度之间。
图4C表示根据本发明的方面的局部JFET植入区409的形成的侧剖视图。如图所示，可在围绕沟道403的底部和侧面的外延层402中形成局部JFET植入区409。在一些实施方案中，局部JFET注入区409可通过穿过图案掩模和硬掩模的离子注入410形成。局部JFET植入区411可重掺杂第一导电类型的离子。局部JFET注入区可以以2到3倍于外延层的离子浓度掺杂。局部JFET注入区可减少耗尽电荷载流子，因此有助于减少器件的RDS。
图4D表示根据本发明的各个方面，在沟道403底部形成厚底部绝缘层411的剖视图。厚底绝缘层411可通过诸如高密度等离子体(HDP)沉积或化学气相沉积技术(CVD)等沉积技术形成。厚的底部绝缘层可由氧化硅或氮化物或ONO(SiO2/氮化物/SiO2)薄膜组成。然后对沟道403的侧壁施加等离子体干刻蚀或湿刻蚀，以去除沉积在沟道侧面上的任何多余绝缘层。厚的底部绝缘层最初形成的厚度在1500和
Figure BDA0003596826250000081
之间。在一些实施例中，厚底部绝缘层的最终厚度为沟道侧壁绝缘层厚度的1.5至2倍，该最终厚度在沟道侧面和底部形成绝缘层后实现，如图4E所示。
图4E显示根据本发明的各个方面，具有平面部分412和沟道部分413的栅极绝缘层的形成的剖面侧视图。如图所示，在外延层402的表面上沉积绝缘层。外延层402表面上的绝缘层的平面部分412将形成集成平面沟道栅极的平面部分的一部分。绝缘层材料也沉积在沟道403的底部和侧壁413上。在实施方式中，具有厚的底部绝缘层的绝缘材料沉积在先前沉积的绝缘材料的顶部，形成厚的底部绝缘层411的最终厚度。绝缘层可由氧化硅组成。绝缘层的平面部分412和沟道403底部的沟道部分413的厚度可以大致相同，例如，在800到1000埃之间。
如图4F所示，导电层包括绝缘层的平面部分412上的平面部分415和沟道部分416。导电层可以沉积在绝缘层的表面上。导电层的沟道部分416填充沟道413中未被绝缘层部分占据的部分，包括厚底绝缘体(可选)411和沟道413侧面的绝缘层。导电层的平面部分415覆盖绝缘层的平面部分412。本文描述的技术在绝缘层的平面部分和沟道部分上创建导电层的极平坦表面，而不在平面部分和沟道部分之间形成中间绝缘层。
图4G表示根据本发明的各个方面，在将导电层图案化以形成具有相连平面栅极部分415和沟道栅极部分416的平面沟道栅极之后，形成集成平面沟道栅极的剖面侧视图。屏蔽并刻蚀导电层415，留下平面沟道栅极的最终尺寸。在移除掩模之后，平面栅极部分415随后可充当用于绝缘层的平面部分412的后续刻蚀的掩模。优选地，刻蚀导电层的过程对导电层的材料具有选择性，即以比导电层材料低得多的速率刻蚀绝缘层的材料。与之相反地，刻蚀绝缘层的过程对绝缘层的材料具有选择性，即以比绝缘层低得多的速率刻蚀导电层。
图4H表示根据本发明的各个方面，具有集成平面沟道栅极的晶体管器件的本体区域417的形成的剖面侧视图。可以在外延层的表面上形成掩模419，在本体区域417的位置上具有间隙。掩模可以是应用于外延层表面的光阻掩模。离子注入418可用于用第二导电类型的离子掺杂外延层402(例如如果第一导电类型为n型，则第二导电类型为p型)。在形成本体区域417之后，可以通过等离子体灰化和使用去除溶液或任何其他已知掩模去除技术(例如但不限于平面化或抛光)来去除掩模419。
在一些实施例中，本体区域可在形成沟道和集成平面沟道栅极之前形成。在这些实施方案中，沟道可以形成在外延层的本体区域中。然后，可通过反离子掺杂在本体区域中形成局部JFET注入区域。该方法的这种实现可用于产生图2中所示的装置。在又一实施例中，掺杂柱可形成在本体区域下。这些掺杂柱形成如图3所示的超级结器件。
图4I表示根据本发明的各个方面，具有集成平面沟道栅极的晶体管器件的源极区形成的剖面侧视图。源极掩模420可以形成在外延层的表面上，在源极区422的位置处具有间隙。一个或多个源极区422可以通过离子421通过源极掩模420中的开口注入而形成在外延层402的本体区417中。源极区422可掺杂浓度大于外延层的第一导电类型的离子。在形成源极区域422之后，可以通过等离子体灰化和使用任何其他已知掩模去除技术的去除溶液清洗来去除源掩模420，例如但不限于平面化或抛光。
图4J表示根据本发明的各个方面，集成平面沟道栅晶体管器件上其他结构的形成的剖面侧视图。在形成源极区422之后，在外延层402的表面上形成隔离层424。隔离层可以是例如但不限于沉积在外延层表面上的氧化硅。隔离层还可以覆盖423集成栅极沟道，完成栅极的绝缘层。源极接触掩模应用于外延层的源极区域422和本体区域417上方的隔离层424。将隔离层刻蚀掉并且在源极区422和本体区417上方的外延层402的表面上沉积源极接触金属426。栅极接触掩模被施加到栅极绝缘426，栅极接触被刻蚀掉并且栅极接触金属425沉积在栅极的导电层415上。栅极接触和源极接触的刻蚀可通过使用等离子体干刻蚀来执行，刻蚀后，栅极接触掩模和源极接触掩模可通过等离子体灰化和使用合适的掩模去除溶液或任何其他已知掩模去除技术(例如但不限于平面化或抛光)来去除。漏极导电层427可以形成在衬底401的背面。漏极导电层427可以是例如但不限于沉积在衬底401背面的金属。
尽管本发明关于某些较佳的版本已经做了详细的叙述，但是仍可能存在各种替代、修正和等效的其他版本。因此，本发明的范围不应由上述说明决定，与之相反，本发明的范围应参照所附的权利要求书及其全部等效内容。任何可选件(无论首选与否)，都可与其他任何可选件(无论首选与否)组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能，否则所附的权利要求书并不应认为是意义和功能的局限。所附的权利要求书不应被解释为包括手段加功能限制，除非在给定权利要求中使用短语“意义是”明确叙述了该限制。

Claims (9)

1.一种晶体管器件，其特征在于，包括：
一个重掺杂第一导电类型的衬底；
一个轻掺杂第一导电类型的外延层，形成在衬底上；
一个掺杂第二导电类型的本体区，形成在外延层中，其中第二导电类型与第一导电类型相反；一个掺杂第一导电类型的源极区，形成在外延层的本体区中；
一个集成平面-沟道栅极，其具有一平面栅极部分形成在外延层的表面上，与在外延层中的沟道中形成的沟道栅极部分相连，其中衬底中的沟道栅极部分底部的深度，小于本体区的最低掺杂深度。
2.如权利要求1所述的晶体管器件，其中沟道栅极部分形成在外延层的本体区中。
3.如权利要求1所述的晶体管器件，还包括一个局域化的JFET注入区，重掺杂第一导电类型，形成在沟道栅极部分的底部和边缘周围。
4.如权利要求3所述的晶体管器件，其中外延层的轻掺杂第一导电类型的区域，分隔局域化的JFET注入和本体区。
5.如权利要求1所述的晶体管器件，还包括一个在沟道底部的厚绝缘层，其中沟道底部的厚绝缘层，比沟道至少一边的绝缘层更厚。
6.如权利要求1所述的晶体管器件，其中外延层还包括可选的掺杂第二导电类型的本体区立柱，以及轻掺杂第一导电类型的外延层立柱。
7.如权利要求1所述的晶体管器件，其中所述栅极沟道部分的沟道侧壁与所述栅极沟道部分的沟道底面以大于90度的角度相交。
8.如权利要求1所述的晶体管器件，其中栅极沟道部分具有0.3至0.8微米之间的沟道深度。
9.如权利要求1所述的晶体管器件，其中在栅极沟道部分的沟道底部的绝缘层厚度，是在沟道边缘的绝缘层厚度的1.5至2倍。
CN202210390724.6A 2021-04-22 2022-04-14 集成的平面-沟道栅极功率mosfet Pending CN115241283A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/237,461 2021-04-22
US17/237,461 US11728423B2 (en) 2021-04-22 2021-04-22 Integrated planar-trench gate power MOSFET

Publications (1)

Publication Number Publication Date
CN115241283A true CN115241283A (zh) 2022-10-25

Family

ID=83668445

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210390724.6A Pending CN115241283A (zh) 2021-04-22 2022-04-14 集成的平面-沟道栅极功率mosfet

Country Status (3)

Country Link
US (1) US11728423B2 (zh)
CN (1) CN115241283A (zh)
TW (1) TWI803288B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116759461A (zh) * 2023-08-18 2023-09-15 深圳市冠禹半导体有限公司 一种高温稳定性的功率mosfet器件及其制备方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI223448B (en) * 2003-04-29 2004-11-01 Mosel Vitelic Inc DMOS device having a trenched bus structure
US8193580B2 (en) 2009-08-14 2012-06-05 Alpha And Omega Semiconductor, Inc. Shielded gate trench MOSFET device and fabrication
US8236651B2 (en) 2009-08-14 2012-08-07 Alpha And Omega Semiconductor Incorporated Shielded gate trench MOSFET device and fabrication
US7829947B2 (en) * 2009-03-17 2010-11-09 Alpha & Omega Semiconductor Incorporated Bottom-drain LDMOS power MOSFET structure having a top drain strap
US7800170B1 (en) 2009-07-31 2010-09-21 Alpha & Omega Semiconductor, Inc. Power MOSFET device with tungsten spacer in contact hole and method
US8138605B2 (en) 2009-10-26 2012-03-20 Alpha & Omega Semiconductor, Inc. Multiple layer barrier metal for device component formed in contact trench
US8431457B2 (en) 2010-03-11 2013-04-30 Alpha And Omega Semiconductor Incorporated Method for fabricating a shielded gate trench MOS with improved source pickup layout
US9252239B2 (en) 2014-05-31 2016-02-02 Alpha And Omega Semiconductor Incorporated Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
US8779510B2 (en) 2010-06-01 2014-07-15 Alpha And Omega Semiconductor Incorporated Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
US9048282B2 (en) 2013-03-14 2015-06-02 Alpha And Omega Semiconductor Incorporated Dual-gate trench IGBT with buried floating P-type shield
US9716167B2 (en) * 2011-02-22 2017-07-25 National Semiconductor Corporation Trench DMOS transistor with reduced gate-to-drain capacitance
US9281368B1 (en) 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide
US10020380B2 (en) 2015-01-23 2018-07-10 Alpha And Omega Semiconductor Incorporated Power device with high aspect ratio trench contacts and submicron pitches between trenches
US9691863B2 (en) 2015-04-08 2017-06-27 Alpha And Omega Semiconductor Incorporated Self-aligned contact for trench power MOSFET
JP2017118024A (ja) * 2015-12-25 2017-06-29 株式会社豊田中央研究所 炭化珪素半導体装置
US10896959B2 (en) * 2016-06-17 2021-01-19 HUNTECK SEMICONDUCTOR (SHANGHAI) CO. Ltd. Top structure of super junction MOSFETs and methods of fabrication
US10170559B1 (en) 2017-06-29 2019-01-01 Alpha And Omega Semiconductor (Cayman) Ltd. Reverse conducting IGBT incorporating epitaxial layer field stop zone and fabrication method
US10833021B2 (en) 2017-06-29 2020-11-10 Alpha And Omega Semiconductor (Cayman) Ltd. Method for precisely aligning backside pattern to frontside pattern of a semiconductor wafer
US10644102B2 (en) 2017-12-28 2020-05-05 Alpha And Omega Semiconductor (Cayman) Ltd. SGT superjunction MOSFET structure
CN110610994B (zh) * 2019-07-17 2023-03-31 成都芯源系统有限公司 一种横向双扩散金属氧化物半导体场效应晶体管
US10910478B1 (en) * 2020-03-04 2021-02-02 Shuming Xu Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116759461A (zh) * 2023-08-18 2023-09-15 深圳市冠禹半导体有限公司 一种高温稳定性的功率mosfet器件及其制备方法

Also Published As

Publication number Publication date
TW202308159A (zh) 2023-02-16
US20220344505A1 (en) 2022-10-27
TWI803288B (zh) 2023-05-21
US11728423B2 (en) 2023-08-15

Similar Documents

Publication Publication Date Title
TWI509809B (zh) 帶有自對準有源接觸的基於高密度溝槽的功率ｍｏｓｆｅｔ及其制備方法
US7714383B2 (en) Semiconductor device
US7394144B2 (en) Trench semiconductor device and method of manufacturing it
US8969953B2 (en) Method of forming a self-aligned charge balanced power DMOS
US7989886B2 (en) Alignment of trench for MOS
US9627526B2 (en) Assymetric poly gate for optimum termination design in trench power MOSFETs
US10636883B2 (en) Semiconductor device including a gate trench and a source trench
TW201216468A (en) Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
WO2006082568A2 (en) Method of manufacturing a lateral semiconductor device
US20220157989A1 (en) Mosfet device with shielding region and manufacturing method thereof
US11245016B2 (en) Silicon carbide trench semiconductor device
US8017494B2 (en) Termination trench structure for mosgated device and process for its manufacture
JP2003086800A (ja) 半導体装置及びその製造方法
US20190067427A1 (en) Inter-poly oxide in field effect transistors
EP1162665A2 (en) Trench gate MIS device and method of fabricating the same
CN107910268B (zh) 功率半导体器件及其制造方法
TWI803288B (zh) 集成的平面-溝道閘極功率mosfet
CN107910271B (zh) 功率半导体器件及其制造方法
CN115642088A (zh) 一种沟槽型SiC MOSFET器件结构及其制造方法
CN113241374B (zh) 功率晶体管结构及其制造方法
CN113284944A (zh) 嵌埋式柵极顶面接触的场效晶体管结构及其制造方法
TWI808856B (zh) 帶有遮罩電極的底部源極溝槽mosfet
WO2023247117A2 (en) Method for producing a semiconductor device and semiconductor device
CN113517334A (zh) 一种具有高k介电沟槽的功率mosfet器件及其制备方法
CN117690795A (zh) 一种新型屏蔽栅沟槽场效应晶体管及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination