CN113410136A - 一种碳化硅沟槽刻蚀方法 - Google Patents

一种碳化硅沟槽刻蚀方法 Download PDF

Info

Publication number
CN113410136A
CN113410136A CN202110663179.9A CN202110663179A CN113410136A CN 113410136 A CN113410136 A CN 113410136A CN 202110663179 A CN202110663179 A CN 202110663179A CN 113410136 A CN113410136 A CN 113410136A
Authority
CN
China
Prior art keywords
silicon carbide
oxide layer
etching
groove
etching method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110663179.9A
Other languages
English (en)
Inventor
张飞
杨鹏翮
孟晨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Microelectronics Technology Institute
Original Assignee
Xian Microelectronics Technology Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xian Microelectronics Technology Institute filed Critical Xian Microelectronics Technology Institute
Priority to CN202110663179.9A priority Critical patent/CN113410136A/zh
Publication of CN113410136A publication Critical patent/CN113410136A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • H01L21/30655Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明公开了一种碳化硅沟槽刻蚀方法,通过在碳化硅衬底材料上进行CVD形成氧化层,在氧化层上涂布光阻后按照设计版图进行光刻;在光刻区域采用干法刻蚀的方法去除氧化层;采用SF6和C4F8的混合气体对去除氧化层的碳化硅衬底进行刻蚀,能够发生化学反应生成聚合物,所生成的聚合物附着在图形的底部和侧壁上,能够对底部和侧壁,特别是图形沟槽产生保护作用,从而减弱反应离子对图形拐角处的刻蚀,有效地防止了微沟槽在图形拐角处形成,本发明工艺流程简单,形成的碳化硅沟槽侧壁光滑、沟槽底部没有微沟槽效应;其方法理论简单易于理解,有效提高碳化硅衬底材料的沟槽的刻蚀效率。

Description

一种碳化硅沟槽刻蚀方法
技术领域
本发明属于微电子制作工艺领域,具体为一种碳化硅沟槽刻蚀方法。
背景技术
SiC(碳化硅)材料具有禁带宽度大、击穿场强高、介电常数小等优点,在制备高温、高频、大功率、抗辐射的半导体器件及紫外光电探测器等方面具有极其广泛的应用,被誉为前景十分广阔的第三代半导体材料。刻蚀技术是SiC器件研制中的一项关键支撑技术,刻蚀工艺的刻蚀精度、刻蚀损伤以及刻蚀表面的残留物均对SiC器件的性能有重要影响。由于SiC材料硬度高、化学性质稳定,湿法刻蚀无法达到要求,因此目前对SiC的刻蚀常采用等离子体干法刻蚀工艺,干法刻蚀碳化硅衬底材料的沟槽一般采用CF4和O2为主,外加惰性气体相组合的刻蚀方法;然而采用上述气体刻蚀的方法得出的沟槽侧壁粗糙度较大且沟槽底部容易产生微沟槽,不能满足工艺需求。
发明内容
本发明的目的在于提供一种碳化硅沟槽刻蚀方法,以克服现有技术的不足。
为达到上述目的,本发明采用如下技术方案:
一种碳化硅沟槽刻蚀方法,包括以下步骤:
S1,在碳化硅衬底材料上进行CVD形成氧化层,在氧化层上涂布光阻后按照设计版图进行光刻;
S2,在光刻区域采用干法刻蚀的方法去除氧化层;
S3,采用SF6和C4F8的混合气体对去除氧化层的碳化硅衬底进行刻蚀,然后采用湿法去除光阻和氧化层,得到碳化硅器件,完成碳化硅沟槽刻蚀。
进一步的,CVD氧化层厚度为800nm~1500nm。
进一步的,在光刻区域采用干法刻蚀去除氧化层直至露出碳化硅衬底。
进一步的,干法刻蚀具体采用物理性刻蚀、化学性刻蚀或物理化学性刻蚀。
进一步的,物理性刻蚀刻蚀功率为1000W~1500W。
进一步的,采用感应耦合等离子刻蚀机对裸露出的碳化硅衬底进行刻蚀。
进一步的,SF6和C4F8流量比为3:1。
进一步的,去除光阻的湿法采用浓硫酸,温度为140-150℃。
进一步的,去除光阻的湿法采用浓硫酸的温度为145℃。
进一步的,去除氧化层的湿法采用氢氟酸,温度为40-45℃。
与现有技术相比,本发明具有以下有益的技术效果:
本发明一种碳化硅沟槽刻蚀方法,通过在碳化硅衬底材料上进行CVD形成氧化层,在氧化层上涂布光阻后按照设计版图进行光刻;在光刻区域采用干法刻蚀的方法去除氧化层;采用SF6和C4F8的混合气体对去除氧化层的碳化硅衬底进行刻蚀,能够发生化学反应生成聚合物,所生成的聚合物附着在图形的底部和侧壁上,能够对底部和侧壁,特别是图形沟槽产生保护作用,从而减弱反应离子对图形拐角处的刻蚀,有效地防止了微沟槽在图形拐角处形成,本发明工艺流程简单,形成的碳化硅沟槽侧壁光滑、沟槽底部没有微沟槽效应;其方法理论简单易于理解,有效提高碳化硅衬底材料的沟槽的刻蚀效率。
进一步的,除光阻的湿法采用浓硫酸的温度为145℃时,能够得到光滑的沟槽结构。
附图说明
图1为本发明实施例中碳化硅沟槽刻蚀方法流程图。
图2为现有方法刻蚀中侧壁粗糙图。
图3为现有方法刻蚀中底部微沟槽图。
图4为本发明实施例中中侧壁光滑图。
图5为本发明实施例中底部没有微沟槽图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述;以下实施例仅仅是本发明一部分的实施例,而不是全部的实施例,不用来限制本发明的范围。
参见图1,本发明一种碳化硅沟槽刻蚀方法,包括以下步骤:
S1,在碳化硅衬底材料上进行CVD(Chemical Vapor Deposition)形成氧化层,在氧化层上涂布光阻后按照设计版图进行光刻;
CVD氧化层厚度为800nm~1500nm。
S2,在光刻区域采用干法刻蚀的方法去除氧化层,露出光阻下面的碳化硅衬底;
干法刻蚀具体采用物理性刻蚀、化学性刻蚀或物理化学性刻蚀;物理性刻蚀刻蚀功率为1000W~1500W。
S3,采用感应耦合等离子刻蚀机,对上述步骤S2中裸露出的碳化硅衬底进行刻蚀,刻蚀气体包括SF6和C4F8;SF6和C4F8流量比为3:1;
本发明采用SF6和C4F8混合气体,能够发生化学反应生成聚合物,所生成的聚合物附着在图形的底部和侧壁上,能够对底部和侧壁,特别是图形沟槽产生保护作用,从而减弱反应离子对图形拐角处的刻蚀,有效地防止了微沟槽在图形拐角处形成。
S4,刻蚀完成之后,采用湿法的方法去除光阻和氧化层,得到碳化硅器件,所得碳化硅器件上其沟槽具侧壁光滑、沟槽底部没有微沟槽。
去除光阻的湿法采用浓硫酸,温度为140-150℃;去除氧化层的湿法采用氢氟酸,温度为40-45℃。
下面结合附图对本发明做进一步详细描述:采用此优化后工艺方法完成了碳化硅沟槽刻蚀,具体如下:
SF6和C4F8刻蚀工艺及结果如表1所示:
采用现有方法及本发明方法针对碳化硅衬底材料的侧壁和底部微沟槽进行刻蚀,刻蚀出满足工艺需求的沟槽及侧壁,在碳化硅衬底材料上进行CVD形成氧化层,在氧化层上涂布光阻后按照设计版图进行光刻,CVD氧化层厚度为800nm,然后在光刻区域采用物理性刻蚀去除氧化层,露出光阻下面的碳化硅衬底,采用感应耦合等离子刻蚀机对裸露出的碳化硅衬底进行刻蚀,刻蚀完成之后,采用湿法的方法去除光阻和氧化层,具体采用145℃的浓硫酸去除光阻,试验结果如图2-图5所示,可以看出其结果侧壁光滑、底部没有微沟槽,试验数据见表2:
表1SF6和C4F8刻蚀参数表
Press(mT) SF<sub>6</sub>(sccm) C<sub>4</sub>F<sub>8</sub>(sccm) RF1(W) RF2(W) Time(s)
12 60 20 1000 10 1800
以上所述是一种沟槽的试验结果,并未对试验中各种可能的特征要求进行全面的组合;针对具体的设备和工艺要求,工艺技术人员可以作出类似的调整,然而这些在理论上均是可行的。
以上内容仅为说明本发明的技术思想,不能以此限定本发明的保护范围,凡是按照本发明提出的技术思想,在技术方案基础上所做的任何改动,均落入本发明权利要求书的保护范围之内。

Claims (10)

1.一种碳化硅沟槽刻蚀方法,其特征在于,包括以下步骤:
S1,在碳化硅衬底材料上进行CVD形成氧化层,在氧化层上涂布光阻后按照设计版图进行光刻;
S2,在光刻区域采用干法刻蚀的方法去除氧化层;
S3,采用SF6和C4F8的混合气体对去除氧化层的碳化硅衬底进行刻蚀,然后采用湿法去除光阻和氧化层,得到碳化硅器件,完成碳化硅沟槽刻蚀。
2.根据权利要求1所述的一种碳化硅沟槽刻蚀方法,其特征在于,CVD氧化层厚度为800nm~1500nm。
3.根据权利要求1所述的一种碳化硅沟槽刻蚀方法,其特征在于,在光刻区域采用干法刻蚀去除氧化层直至露出碳化硅衬底。
4.根据权利要求1所述的一种碳化硅沟槽刻蚀方法,其特征在于,干法刻蚀具体采用物理性刻蚀、化学性刻蚀或物理化学性刻蚀。
5.根据权利要求4所述的一种碳化硅沟槽刻蚀方法,其特征在于,物理性刻蚀刻蚀功率为1000W~1500W。
6.根据权利要求1所述的一种碳化硅沟槽刻蚀方法,其特征在于,采用感应耦合等离子刻蚀机对裸露出的碳化硅衬底进行刻蚀。
7.根据权利要求1所述的一种碳化硅沟槽刻蚀方法,其特征在于,SF6和C4F8流量比为3:1。
8.根据权利要求1所述的一种碳化硅沟槽刻蚀方法,其特征在于,去除光阻的湿法采用浓硫酸,温度为140-150℃。
9.根据权利要求8所述的一种碳化硅沟槽刻蚀方法,其特征在于,去除光阻的湿法采用浓硫酸的温度为145℃。
10.根据权利要求1所述的一种碳化硅沟槽刻蚀方法,其特征在于,去除氧化层的湿法采用氢氟酸,温度为40-45℃。
CN202110663179.9A 2021-06-15 2021-06-15 一种碳化硅沟槽刻蚀方法 Pending CN113410136A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110663179.9A CN113410136A (zh) 2021-06-15 2021-06-15 一种碳化硅沟槽刻蚀方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110663179.9A CN113410136A (zh) 2021-06-15 2021-06-15 一种碳化硅沟槽刻蚀方法

Publications (1)

Publication Number Publication Date
CN113410136A true CN113410136A (zh) 2021-09-17

Family

ID=77684024

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110663179.9A Pending CN113410136A (zh) 2021-06-15 2021-06-15 一种碳化硅沟槽刻蚀方法

Country Status (1)

Country Link
CN (1) CN113410136A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113571414A (zh) * 2021-09-24 2021-10-29 广州粤芯半导体技术有限公司 半导体器件的制造方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915911A (zh) * 2012-09-24 2013-02-06 中国电子科技集团公司第五十五研究所 一种改善碳化硅台面底部的刻蚀方法
CN104733324A (zh) * 2015-03-20 2015-06-24 电子科技大学 一种碳化硅器件的栅槽制作方法
CN105405749A (zh) * 2015-11-02 2016-03-16 株洲南车时代电气股份有限公司 一种刻蚀碳化硅的方法
CN106504982A (zh) * 2015-09-07 2017-03-15 北京北方微电子基地设备工艺研究中心有限责任公司 一种基片的刻蚀方法
CN106816372A (zh) * 2015-11-30 2017-06-09 北京北方微电子基地设备工艺研究中心有限责任公司 一种碳化硅衬底的刻蚀方法
US20180065844A1 (en) * 2016-09-07 2018-03-08 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Material Structure and Method for Deep Silicon Carbide Etching
CN109148378A (zh) * 2017-06-19 2019-01-04 台湾积体电路制造股份有限公司 沟槽结构
CN109243973A (zh) * 2018-10-31 2019-01-18 秦皇岛京河科学技术研究院有限公司 一种刻蚀碳化硅的方法
CN109461648A (zh) * 2018-10-31 2019-03-12 秦皇岛京河科学技术研究院有限公司 一种碳化硅器件制造方法
CN110957214A (zh) * 2018-09-26 2020-04-03 株洲中车时代电气股份有限公司 一种沟槽及其蚀刻方法
CN111128717A (zh) * 2018-10-30 2020-05-08 株洲中车时代电气股份有限公司 一种碳化硅沟槽结构的制造方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915911A (zh) * 2012-09-24 2013-02-06 中国电子科技集团公司第五十五研究所 一种改善碳化硅台面底部的刻蚀方法
CN104733324A (zh) * 2015-03-20 2015-06-24 电子科技大学 一种碳化硅器件的栅槽制作方法
CN106504982A (zh) * 2015-09-07 2017-03-15 北京北方微电子基地设备工艺研究中心有限责任公司 一种基片的刻蚀方法
CN105405749A (zh) * 2015-11-02 2016-03-16 株洲南车时代电气股份有限公司 一种刻蚀碳化硅的方法
CN106816372A (zh) * 2015-11-30 2017-06-09 北京北方微电子基地设备工艺研究中心有限责任公司 一种碳化硅衬底的刻蚀方法
US20180065844A1 (en) * 2016-09-07 2018-03-08 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Material Structure and Method for Deep Silicon Carbide Etching
CN109148378A (zh) * 2017-06-19 2019-01-04 台湾积体电路制造股份有限公司 沟槽结构
CN110957214A (zh) * 2018-09-26 2020-04-03 株洲中车时代电气股份有限公司 一种沟槽及其蚀刻方法
CN111128717A (zh) * 2018-10-30 2020-05-08 株洲中车时代电气股份有限公司 一种碳化硅沟槽结构的制造方法
CN109243973A (zh) * 2018-10-31 2019-01-18 秦皇岛京河科学技术研究院有限公司 一种刻蚀碳化硅的方法
CN109461648A (zh) * 2018-10-31 2019-03-12 秦皇岛京河科学技术研究院有限公司 一种碳化硅器件制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113571414A (zh) * 2021-09-24 2021-10-29 广州粤芯半导体技术有限公司 半导体器件的制造方法

Similar Documents

Publication Publication Date Title
TWI713116B (zh) 圖案化低介電常數介電膜之方法
JP2010503207A (ja) 高アスペクト比のフィーチャを形成するための選択的化学エッチングおよび関連構造
KR20110011571A (ko) 마이크로-로딩을 저감시키기 위한 플라즈마 에칭 방법
JP2019530230A (ja) 高アスペクト比構造のためのストリッププロセス
CN110211919B (zh) 浅沟槽隔离结构的形成方法及半导体器件的形成方法
CN100468652C (zh) 在半导体基底的金属结构表面去除残余物的方法
CN113410136A (zh) 一种碳化硅沟槽刻蚀方法
CN108364867A (zh) 深硅刻蚀方法
CN117219506B (zh) 一种消除刻蚀负载效应的方法
KR980012063A (ko) 기판으로부터의 유기 반사 방지 코팅물 에칭 방법
WO2022001487A1 (zh) 半导体结构的处理方法及形成方法
TWI570803B (zh) A deep silicon etch method
US20230053945A1 (en) Methods for processing semiconductor structures and methods for forming semiconductor structures
TWI495009B (zh) A Plasma Etching Method with Silicon Insulating Layer
CN115547825A (zh) 衬底沟槽刻蚀方法
JPH04237125A (ja) ドライエッチング方法
KR101711647B1 (ko) 도전성 라인 사이의 유전 물질 제거 방법
JP7411818B2 (ja) 半導体構造の処理方法及び形成方法
CN111584357B (zh) 一种深沟槽刻蚀方法
KR102713031B1 (ko) 반도체 구조의 처리 방법 및 형성 방법
TW421825B (en) Method of cleaning after etching of gate in integrated circuit
CN103839870B (zh) 用于tsv刻蚀中改善硅通孔侧壁粗糙度的方法
TWI442469B (zh) A plasma etching method for carbon - containing layer
KR20090067596A (ko) 반도체 소자 제조 방법
US7268082B2 (en) Highly selective nitride etching employing surface mediated uniform reactive layer films

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210917

RJ01 Rejection of invention patent application after publication