經濟部中央標準局員工消費合作社印製 421825 A7 B7 五、發明説明（/ ) 詳細說明： 發明之技術領域： 本發明係關於一種積體電路中閘極(gate)蝕刻後之清 洗方法，特別是關於電晶體進行閘極蝕刻後，消弭其清 洗過程中所產生閘氧化層(gate oxide)受到傷害的方法。 發明背景= 電晶體是積體電路中最重要的元件，一個電晶體包含 有閘極、汲極和源極，閘極和基板之間更包括有一層閘氧 化層。積體電路的製程中，乾蝕刻(dry etch)過程中’通常 其中之溴化氫(HBr)會和複晶砍(poly gate)反應而生成高分 子聚合物，所述高分子聚合物會沉積在閘氧化層及矽薄膜 的側壁而形成保護層，以避免微渠溝的發生。由於去光阻 時並不能把上述之保護層去除，習用濕式清洗法去除所述 之保護層，通常使用稀氫氟酸(HF+H20)或稀氫氧化銨 (NH4〇H+H20)做爲清洗液，但在清洗過程中常會造成閘 氧化層受傷害而降低了其崩潰電壓，嚴重影響產品的良 率〇 請參閱圖一，習知技術中，形成電晶體中的閘極時， 在成長閘氧化層2於半導體基板表面後，隨即沈積複晶矽 3、抗反射層4與光阻劑5(photoresist)，接著，利用微影技 術定義出閘極之光阻圖案5a位置，再使用乾蝕刻技術蝕刻 晶片上未被光阻圖案所保護之抗反射層、複晶矽及閘氧化 層，在此所使用的乾蝕刻是採用電漿方式進行，以氟碳化 物當反應氣體。在蝕刻的同時，爲預防微溝渠(Micm- 2 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閎讀背面之注意事頃再填寫本頁) li衣' -訂 42 1825 ， a? __B7 五、發明説明（J )Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 421825 A7 B7 V. Description of the invention (/) Detailed description: Technical field of the invention: The present invention relates to a cleaning method after gate etching in integrated circuits, especially The method for eliminating the damage to the gate oxide generated in the cleaning process of the transistor after the gate etching is performed. Background of the Invention = A transistor is the most important component in an integrated circuit. A transistor contains a gate, a drain, and a source. A gate oxide layer is included between the gate and the substrate. During the fabrication of integrated circuits, in the dry etch process, usually hydrogen bromide (HBr) will react with poly gate to form a polymer, which will be deposited. A protective layer is formed on the gate oxide layer and the side wall of the silicon film to prevent the occurrence of microchannels. Since the above protective layer cannot be removed when removing the photoresist, the wet protective method is used to remove the protective layer. Dilute hydrofluoric acid (HF + H20) or dilute ammonium hydroxide (NH4〇H + H20) is usually used. It is a cleaning liquid, but the gate oxide layer is often damaged during the cleaning process, which reduces its breakdown voltage, which seriously affects the yield of the product. Please refer to Figure 1. In the conventional technology, when the gate electrode in the transistor is formed, After the gate oxide layer 2 is grown on the surface of the semiconductor substrate, the polycrystalline silicon 3, the anti-reflection layer 4 and the photoresist 5 are then deposited. Then, the position of the photoresist pattern 5a of the gate is defined by lithography technology, and then used The dry etching technology etches the anti-reflection layer, polycrystalline silicon, and gate oxide layer on the wafer that are not protected by the photoresist pattern. The dry etching used here is performed by plasma, with fluorocarbon as the reaction gas. At the same time of etching, in order to prevent micro-ditches (Micm- 2 paper wave scales apply Chinese National Standard (CNS) A4 specifications (210X297 mm) (please read the notes on the back before filling out this page) li yi-order 42 1825, a? __B7 V. Description of the invention (J)
Trench)的產生，通常是在乾蝕刻的過程中加入溴化氫 (HBr)使之與閘氧化層2和複晶矽3a的側壁反應，而生成高 分子聚合物200，所述之高分子聚合物會沉積在矽薄膜的 側壁與閘氧化層而形成保護層，以避免微渠溝的發生。除 此外，在乾蝕刻的同時，用來保護閘極位置的光阻圖案 5a，不可避免地與電漿作用會有局部硬塊(veil)lOO的產 生。 請參閱圖一，在習用技術中，在定義__極之後，接 續使用如氧氣當反應氣體的電漿(02光阻圖 案，但其並不能除去所述之高分子聚合局部硬塊 100，因此必須再加入氫氟酸(HF)或氫氯化銨(NH4〇H)用 以除去局部硬塊100及高分子聚合物g但值得注意的 是，如圖二所示，在使用稀氫氟酸(hf+h2o)或稀氫氧化 銨(NH4〇H+H20)做爲清洗液時，所述之兩種溶液皆會造 成閘氧化層2a傷害，最後再加入一般所謂的1^人(^八-1 : NH4〇H/H202/H20, RCA-2 : HC1/H202/H20)溶液，進行 進一歩的清洗過程。所述之稀氫氟酸溶液通常會使閘氧化 層減少約20-40埃，而在利用稀氬氧化銨其閘氧化層減少 約10-20埃，而當積體電路進入次微米或深次微米的製程 以後，記憶元件的集積度大幅增加，而各層的厚度也大幅 減小，因此當閘氧化層厚度小於30埃時，不論使用稀氫氟 酸或稀氫氧化鞍溶液，皆會造成的閘氧化層的大量流失。 本紙張尺度適用中國國家標準（CNS ) A4规格（2丨0>^297公釐） 421825 五、發明説明（)） 爲解決上述的問題，本發明揭露了一種在積體電路中 進行閘極蝕刻後之清洗方法，將可大幅減低閘氧化層受到 傷害的程度，以改善習知技術中的問題。 發明之簡要說明： 本發明的主要目的，是提供一種在積體電路中進行閘 極蝕刻後之清洗方法，以期解決在清洗過程中閘氧化層受 到傷害的問題。 本發明的次要目的是提供一種乾式清洗法，能夠提供 較高的清洗效率，並且是較無污染與安全的清洗過程。 本發明係利用如下的製程而達成上述的目的：首先形 成閘氧化層，並陸續沉積一層矽薄膜、抗反射層與光阻 劑。其後，利用微影技術定義出閘極位置後，接著進行閘 極的蝕刻，使用含氟化合物做爲反應氣體，進行乾蝕刻， 接著，使用二階段的乾式清洗方式除去晶片上當保護層之 光阻、高分子聚合物及在乾蝕刻時所形成位於光阻上的局 部硬塊。首先，先利用以氧氣當反應氣體的電漿，可將爲 保護層之光阻除掉，接著將氣體換成氧氣、氮氣及氫氣或 氧氣、氮氣和含氟之混合氣體做爲電漿的反應氣體來清除 聚合物與局部硬塊。最後，再加一道濕式清洗步驟，確定 晶片上所有之不潔物被去除後，即可進行源極和汲極的製 作。 本發明的重點在於以二階段電漿方式’去除在蝕刻時 所產生的高分子聚合物及光阻上在乾触刻時所產生的局部 硬塊，除可避免閘氧化層的流失外，由於採用電漿方式清 本紙張尺度中國國家標準（CNS > Λ4規格（210X4297公釐> 經濟部中央標準為貝工消費合作社印製 ά^Ι 825 ‘ Α7 _Β7__ 五、發明説明（& ) 洗，使得前段清洗歩驟皆暴露在電漿下，只需改變反應氣 體之來源，不需改變任何製程環境，如此可顯著減低清洗 時間及提高清洗效率。 圖示之簡要說明： 圖一爲習知技藝中進行微影蝕刻後的製程剖面示意圖。 圖二爲習知技藝中進行去光阻、矽薄膜側壁的高分子聚 合物及光阻表面之硬塊的製程剖面圖。 圖三(AHC)爲本發明實施例中，的製程剖面示意圖。 圖號說明： 1 半導體基板 3 矽薄膜 5 光阻 100硬塊 200高分子聚合物 發明詳細說明 第一實施例 請參閱圖三A，首先在半導體基板上1形成閘氧化層2， 並陸續沉積一層複晶矽3、抗反射層4和光阻劑5。所述閘氧 化層2通常係利用熱氧化法所形成，其厚度介於20埃到150 埃之間，所述複晶矽3係以同步摻雜(in situ)的低壓化學氣相 沉積法(LPCVD)，但也可先形成未摻雜的低壓化學氣相沉積 法沈積複晶矽後再使用熱擴散(thermal diffiision)或離子植入 (ion implantation)方式，將憐(P)或砷(As)滲入複晶矽中，其 (锖先閱讀背面之注意事項再本頁) -裝- 2 閘氧化層 4抗反射層 10閘極 訂 線 本紙張尺度適用中國國家標準（CMS ) A4規格(210X297公釐） 421825 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（j* ) 厚度介於1000埃到3^埃之間，所述之抗反射層4通常是氮 鎢或是複晶砂，目前也有使用有機高 分子物質(BARC)來代 請參考圖三B ’以微影技術定義出閘極位置後，接著， 以乾蝕刻技術進行抗反射層4afP複晶矽3a的蝕刻，形成輪廓 良好的閘極10 ’再利用二階段電漿方g去在乾蝕刻時所 產生光阻局部硬塊100及高分子聚合用以代替傳統使 用的稀氫氟酸或稀氫氧化銨溶液，接著^反應室(chamber) 中取出晶片，以清洗液溶液再次清洗晶片，即可進行源極 及汲極的製作，形成積體電路中基本的電晶體結構。 所述之乾蝕刻係用含氟或含氯等做爲反應氣體#述 之二階段電漿方式清除局洁硬塊100及高分子聚合物|步 驟，是本發明之重點所在，第一階段以氧氣當反應源，其 流量爲ί〇〇〇至3000sccm之間，反應時間爲60至120sec之間將 光阻軟化，第二階段係用氧氣(02)、氮氣(N2)與氫氣(H2)做 爲電漿氣體，其比例分別爲60 : 9 : 1至40 : 9 : 1的環境反 應40至80 sec下操作之。 第二實施例 本發明亦可以第二實施例操作之，圖式中相同的圖號 代表與第一實施例相同之層次。 請參閱圖三A，首先，依舊在半導體基板上1形成閘氧 化層2，並陸續沉積一層複晶矽3、抗反射層4和光阻劑5。 如圖三B所示，以微影技術定義出閘極位置後，接著，以乾 蝕刻技術進行抗反射層4成1複晶矽3a的蝕刻，形成輪廓良好 (#先聞讀背面之注意事項再本頁) ,裝· 訂· -線'- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 42 182 A7 B7 五、發明説明（A ) 的閘極10，再利用二階段電漿方^去在乾蝕刻時所產生 光阻局部硬塊1 〇〇及高分子聚合物Ϊ 4述之二階段電漿方式清除局_塊100及高分子聚合 步驟，是本發明之重點所在，第一階段氧氣當反應 源，其反應時間爲30至60sec之間將光阻軟化，第二階段 係用氧氣(〇2)、氮氣(N2)與含氟(F)之氣體所組成之混合氣 體，其中氧氣(〇2)與含氟(F)之氣體比例爲5 : 1至20 : 1 之間，而氮氣(N2)與氧氣(02)之氣體比例約10%，反應10至 40sec之間下操作之，而其中含氟氣體源可爲CF4、C2F6或 NF3 ° 經上述電漿方式遺洗步驟後，如圖三C所示，局部硬塊Trench) is usually produced by adding hydrogen bromide (HBr) during the dry etching process to react with the side walls of the gate oxide layer 2 and the polycrystalline silicon 3a to form a polymer 200. The polymer is polymerized. Objects are deposited on the sidewalls of the silicon film and the gate oxide layer to form a protective layer to prevent microchannels. In addition, during the dry etching, the photoresist pattern 5a used to protect the gate position will inevitably produce localized veil 100 due to the interaction with the plasma. Please refer to FIG. 1. In the conventional technology, after the __ pole is defined, a plasma (02 photoresist pattern) such as oxygen is used as a reaction gas, but it cannot remove the polymer polymer local hard block 100, so it must be used. Then add hydrofluoric acid (HF) or ammonium hydrochloride (NH4OH) to remove the local hard mass 100 and high molecular polymer g. But it is worth noting that, as shown in Figure 2, when using dilute hydrofluoric acid (hf + h2o) or dilute ammonium hydroxide (NH4〇H + H20) as the cleaning solution, both of the solutions mentioned above will cause the gate oxide layer 2a to damage, and finally add the so-called 1 ^ person (^ 八 -1 : NH4〇H / H202 / H20, RCA-2: HC1 / H202 / H20) solution for further cleaning. The dilute hydrofluoric acid solution usually reduces the gate oxide layer by about 20-40 angstroms, and After dilute ammonium oxide is used, the gate oxide layer is reduced by about 10-20 angstroms. When the integrated circuit enters the sub-micron or deep sub-micron process, the accumulation degree of the memory element is greatly increased, and the thickness of each layer is also greatly reduced. Therefore, when the thickness of the oxide layer of the gate is less than 30 angstroms, no matter whether the diluted hydrofluoric acid or dilute hydroxide solution is used, A large amount of oxide layer is lost. This paper size is in accordance with Chinese National Standard (CNS) A4 specification (2 丨 0 > ^ 297mm) 421825 5. Description of the invention ()) In order to solve the above problems, the present invention discloses a The cleaning method after gate etching in the circuit can greatly reduce the degree of damage to the gate oxide layer, so as to improve the problems in the conventional technology. Brief description of the invention: The main object of the present invention is to provide a cleaning method after gate etching in a integrated circuit, in order to solve the problem that the gate oxide layer is damaged during the cleaning process. A secondary object of the present invention is to provide a dry cleaning method, which can provide higher cleaning efficiency, and is a pollution-free and safe cleaning process. The present invention uses the following process to achieve the above-mentioned object: firstly, a gate oxide layer is formed, and a silicon film, an anti-reflection layer and a photoresist are successively deposited. After that, the gate position is defined by lithography, and then gate etching is performed, and dry etching is performed using a fluorine-containing compound as a reaction gas. Then, a two-stage dry cleaning method is used to remove the light as a protective layer on the wafer. Resists, high molecular polymers and local hard blocks formed on the photoresist during dry etching. First of all, the plasma that uses oxygen as the reaction gas can be used to remove the photoresist as a protective layer, and then the gas is replaced with oxygen, nitrogen and hydrogen or a mixed gas of oxygen, nitrogen and fluorine as the plasma reaction. Gas to remove polymer and local lumps. Finally, a wet cleaning step is added to confirm that all the impurities on the wafer have been removed, and then the source and drain can be fabricated. The focus of the present invention is to use a two-stage plasma method to 'remove the high molecular polymer produced during the etching and the local hard blocks generated during the dry contact etch on the photoresist, in addition to avoiding the loss of the gate oxide layer, due to the use of Plasma method Chinese paper standard (CNS > Λ4 specification (210X4297 mm)> The central standard of the Ministry of Economic Affairs is printed for Shellfish Consumer Cooperatives ^ 825 'Α7 _Β7__ 5. Description of the invention (&) The front-stage cleaning steps are all exposed to the plasma, and only the source of the reaction gas needs to be changed without changing any process environment, which can significantly reduce the cleaning time and improve the cleaning efficiency. Brief description of the diagram: Figure 1 is a conventional technique Figure 2 is a schematic cross-sectional view of the process after lithographic etching is performed. Figure 2 is a cross-sectional view of the process of removing photoresist, polymer on the sidewall of the silicon film and hard blocks on the surface of the photoresist in conventional techniques. Figure 3 (AHC) is the present invention In the embodiment, a schematic cross-sectional view of the manufacturing process is shown in the figure. Explanation of the number: 1 semiconductor substrate 3 silicon film 5 photoresistor 100 hard block 200 polymer polymer Detailed description of the first embodiment Referring to FIG. 3A, a gate oxide layer 2 is first formed on a semiconductor substrate 1, and a layer of polycrystalline silicon 3, an anti-reflection layer 4 and a photoresist 5 are successively deposited. The gate oxide layer 2 is usually formed by a thermal oxidation method. Its thickness is between 20 Angstroms and 150 Angstroms. The polycrystalline silicon 3 is formed by simultaneous low-pressure chemical vapor deposition (LPCVD), but an undoped low-pressure chemical gas may be formed first. Phase deposition method is used to deposit polycrystalline silicon and then use thermal diffiision or ion implantation to infiltrate P (P) or arsenic (As) into the polycrystalline silicon. (Please read the note on the back first Matters are on this page)-Installed-2 gate oxide layer 4 anti-reflective layer 10 gate electrode binding This paper size is applicable to Chinese National Standard (CMS) A4 specification (210X297 mm) 421825 A7 B7 5. Description of the invention (j *) The thickness is between 1000 angstroms and 3 angstroms. The anti-reflection layer 4 is usually nitrogen tungsten or polycrystalline sand. Currently, organic polymer substances (BARC) are also used. Please refer to Figure 3B 'after defining the gate position by lithography technology, and then, The etching process is performed on the anti-reflection layer 4afP polycrystalline silicon 3a to form a good-profile gate 10 ', and then a two-stage plasma cube is used to replace the photoresist local hard mass 100 and polymer polymerization during dry etching to replace the traditional Use the dilute hydrofluoric acid or dilute ammonium hydroxide solution, and then take out the wafer from the chamber, and then clean the wafer again with the cleaning solution, and then the source and drain can be fabricated to form the basic in integrated circuit. The crystal structure. The dry etching system uses fluorine or chlorine as the reaction gas. The two-stage plasma method to remove the localized hard mass 100 and the high molecular polymer is the key point of the present invention. In the first stage, oxygen is used as the reaction source, and the flow rate is between 1000 and 3000 sccm. The reaction time is between 60 and 120 sec to soften the photoresist. The second stage uses oxygen (02), nitrogen (N2), and hydrogen ( H2) as the plasma gas, the ratio of which is 60: 9: 1 to 40: 9: 1, the environmental reaction is operated at 40 to 80 sec. Second Embodiment The present invention can also be operated in the second embodiment. The same reference numerals in the drawings represent the same levels as the first embodiment. Referring to FIG. 3A, first, a gate oxide layer 2 is still formed on the semiconductor substrate 1, and a layer of polycrystalline silicon 3, an anti-reflection layer 4 and a photoresist 5 are successively deposited. As shown in FIG. 3B, after the gate position is defined by the lithography technology, the anti-reflection layer is then etched into a polycrystalline silicon 3a by a dry etching technique to form a good profile (# 先 闻 读 NOTE on the back side (Re-page), binding, binding, -line'- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 42 182 A7 B7 V. Gate 10 of the invention description (A), then reused in two stages Plasma treatment ^ removing the photoresist local hard masses 100 and polymer polymers produced during dry etching is a two-stage plasma method to remove the local block 100 and polymer polymerization steps, which is the focus of the present invention. In the first stage, oxygen is used as the reaction source. Its reaction time is between 30 and 60 sec to soften the photoresist. The second stage is a mixed gas composed of oxygen (02), nitrogen (N2), and fluorine (F) -containing gas. Among them, the ratio of oxygen (〇2) and fluorine (F) gas is between 5: 1 to 20: 1, and the ratio of nitrogen (N2) and oxygen (02) gas is about 10%, and the reaction is between 10 to 40sec. The following operations are performed, and the fluorine-containing gas source can be CF4, C2F6, or NF3 ° After the plasma washing method is performed, as shown in FIG. 3C Local lumps
100及高分子聚合; 被徹底清除，形成輪廓良好之閘 先 意 事 項100 and polymer polymerization; completely removed, forming a good profile gate
訂 極，且其閘氧化層2U流失量已從40〜20埃減低至10埃以 下，這在閘氧化層厚度小於30埃時，對於晶片良率之提升 有極大幫助。而所改善後之步驟，可大大減低反應時間(乾 式清洗法只需60〜150sec)，因此增加清洗效率。所述之清洗 溶液可如傳統製程中所使用RCA或只使用二次去離子水(D, I. Water)進行清洗過程後，即可進行接續的製程。 以上所述係利用較佳實例詳細敘述本發明，而非限制本 發明的範圍，而且熟知此技術領域人士皆能明瞭，適當而細 微的改變與調整，能將不失本發明的要義所在，故都應視爲 本發明進一步實施狀況。 ^•張尺度適用中國國家標準（CNS > A4規格（2丨0¾297公釐） 線 經濟部t央標準局員工消費合作社印製And the 2U loss of the gate oxide layer has been reduced from 40 to 20 angstroms to less than 10 angstroms. This will greatly improve the yield of the wafer when the gate oxide thickness is less than 30 angstroms. The improved steps can greatly reduce the reaction time (the dry cleaning method only needs 60 ~ 150sec), thus increasing the cleaning efficiency. The cleaning solution can be used in the conventional process after performing the cleaning process using RCA or using only secondary deionized water (D, I. Water). The above is a detailed description of the present invention using preferred examples, rather than limiting the scope of the present invention, and those skilled in the art will understand that appropriate and subtle changes and adjustments will not lose the essence of the present invention, so Should be considered as the status of further implementation of the present invention. ^ • Zhang's scale applies to Chinese national standards (CNS > A4 size (2 丨 0¾297 mm) Line Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs