CN113228178A - 调节存储器系统的读取速度方法、比较电路及存储器系统 - Google Patents

调节存储器系统的读取速度方法、比较电路及存储器系统 Download PDF

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Publication number
CN113228178A
CN113228178A CN201980006437.7A CN201980006437A CN113228178A CN 113228178 A CN113228178 A CN 113228178A CN 201980006437 A CN201980006437 A CN 201980006437A CN 113228178 A CN113228178 A CN 113228178A
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China
Prior art keywords
signal
delay
memory system
comparison result
memory
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CN201980006437.7A
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English (en)
Inventor
邝仁德
张一平
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Chengdu Haiguang Integrated Circuit Design Co Ltd
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Chengdu Haiguang Integrated Circuit Design Co Ltd
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Application filed by Chengdu Haiguang Integrated Circuit Design Co Ltd filed Critical Chengdu Haiguang Integrated Circuit Design Co Ltd
Publication of CN113228178A publication Critical patent/CN113228178A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)

Abstract

一种生成指示存储系统的输出延迟与基准延迟之间的差的范围的比较结果信号的方法包括：生成与所述输出延迟相关联的高低电平交替出现的交替序列信号(S901)；生成具有预定频率和所述基准延迟的基准信号(S902)；以及基于所述交替序列信号和所述基准信号生成所述比较结果信号(S903)。通过确定指示当前输出延迟与基准延迟的差的范围的比较结果信号，按照需要调节存储器系统的读取速度，降低存储器系统的不必要的功耗，以及提高存储器系统的良率。

Description

PCT国内申请，说明书已公开。

Claims (26)

  1. PCT国内申请，权利要求书已公开。
CN201980006437.7A 2019-12-30 2019-12-30 调节存储器系统的读取速度方法、比较电路及存储器系统 Pending CN113228178A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/129936 WO2021134221A1 (zh) 2019-12-30 2019-12-30 调节存储器系统的读取速度方法、比较电路及存储器系统

Publications (1)

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CN113228178A true CN113228178A (zh) 2021-08-06

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US (1) US11373693B2 (zh)
CN (1) CN113228178A (zh)
WO (1) WO2021134221A1 (zh)

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US11811567B1 (en) * 2022-09-09 2023-11-07 Apple Inc. Serial data receiver with decision feedback equalizer with feed forward technique

Citations (5)

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CN1277490A (zh) * 1999-06-15 2000-12-20 三菱电机株式会社 延迟电路、时钟生成电路及相位同步电路
CN1402259A (zh) * 2001-08-03 2003-03-12 尔必达存储器股份有限公司 校准方法和存储系统
KR100575003B1 (ko) * 2005-01-05 2006-05-02 삼성전자주식회사 레이턴시 회로를 구비하는 반도체 메모리 장치 및 그데이터 출력 제어 방법
CN101154434A (zh) * 2006-09-29 2008-04-02 海力士半导体有限公司 半导体存储器件及其操作方法
CN101727412A (zh) * 2008-10-30 2010-06-09 恩益禧电子股份有限公司 存储器接口和存储器接口的操作方法

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KR100866958B1 (ko) * 2007-02-08 2008-11-05 삼성전자주식회사 고속 ｄｒａｍ의 정확한 독출 레이턴시를 제어하는 방법 및장치
EP2267898A1 (en) * 2008-04-11 2010-12-29 Fujitsu Limited Phase controller, phase controlling printed circuit board and controlling method
JP5407551B2 (ja) * 2009-05-22 2014-02-05 富士通セミコンダクター株式会社 タイミング調整回路及びタイミング調整方法
KR101179462B1 (ko) 2010-11-30 2012-09-07 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그를 포함하는 반도체 메모리 시스템
US8976596B1 (en) 2013-08-23 2015-03-10 Kabushiki Kaisha Toshiba Controller
KR102378520B1 (ko) * 2015-08-26 2022-03-25 에스케이하이닉스 주식회사 반도체 장치 및 시스템

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1277490A (zh) * 1999-06-15 2000-12-20 三菱电机株式会社 延迟电路、时钟生成电路及相位同步电路
CN1402259A (zh) * 2001-08-03 2003-03-12 尔必达存储器股份有限公司 校准方法和存储系统
KR100575003B1 (ko) * 2005-01-05 2006-05-02 삼성전자주식회사 레이턴시 회로를 구비하는 반도체 메모리 장치 및 그데이터 출력 제어 방법
CN101154434A (zh) * 2006-09-29 2008-04-02 海力士半导体有限公司 半导体存储器件及其操作方法
CN101727412A (zh) * 2008-10-30 2010-06-09 恩益禧电子股份有限公司 存储器接口和存储器接口的操作方法

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US11373693B2 (en) 2022-06-28
WO2021134221A1 (zh) 2021-07-08
US20210398575A1 (en) 2021-12-23

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