WO2021134221A1 - 调节存储器系统的读取速度方法、比较电路及存储器系统 - Google Patents

调节存储器系统的读取速度方法、比较电路及存储器系统 Download PDF

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WO2021134221A1
WO2021134221A1 PCT/CN2019/129936 CN2019129936W WO2021134221A1 WO 2021134221 A1 WO2021134221 A1 WO 2021134221A1 CN 2019129936 W CN2019129936 W CN 2019129936W WO 2021134221 A1 WO2021134221 A1 WO 2021134221A1
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Prior art keywords
signal
delay
memory system
comparison result
output
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PCT/CN2019/129936
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English (en)
French (fr)
Inventor
邝仁德
张一平
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成都海光集成电路设计有限公司
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Priority to CN201980006437.7A priority Critical patent/CN113228178B/zh
Priority to PCT/CN2019/129936 priority patent/WO2021134221A1/zh
Priority to US17/254,241 priority patent/US11373693B2/en
Publication of WO2021134221A1 publication Critical patent/WO2021134221A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits

Definitions

  • the present disclosure generally relates to storage, and more specifically, to a method of generating a comparison result signal indicating the range of the difference between the output delay of a memory system and a reference delay, a comparison circuit, a method of adjusting the reading speed of a memory system, and a memory System and method of operating the memory system.
  • a method for generating a comparison result signal indicating a range of a difference between an output delay of a memory system and a reference delay including: generating a high and low level alternation associated with the output delay The alternating sequence signal appears; a reference signal having a predetermined frequency and the reference delay is generated; and the comparison result signal is generated based on the alternating sequence signal and the reference signal.
  • a method for adjusting the read speed of a memory system including: generating an alternating sequence signal with high and low levels alternately associated with the output delay of the memory system; generating a signal with a predetermined frequency And a reference signal delayed from a reference; generate a comparison result signal indicating the range of the difference between the output delay and the reference delay based on the alternating sequence signal and the reference signal; and determine the value indicated by the comparison result signal Whether it is a predetermined value to adjust the reading speed of the memory system based on the determination result.
  • a memory system including: a memory including a plurality of storage units, and the memory outputs an alternating sequence signal with an output delay; a reference signal generating circuit that generates a signal with a predetermined frequency and a reference delay A reference signal; a comparison circuit that receives an alternating sequence signal of alternating high and low levels associated with the output delay and the reference signal, and generates a comparison result signal based on the alternating sequence signal and the reference signal, the The comparison result signal indicates the range of the difference between the output delay and the reference delay; and a delay control signal generating circuit, based on the comparison result signal, generates a delay control signal for adjusting the output delay of the memory system, Wherein, the memory receives the delay control signal.
  • a method for adjusting the read speed of a memory system including: connecting the memory system with a comparison circuit; and adjusting the read speed of the memory system until the comparison result signal
  • the indicated value is a predetermined value; wherein, the comparison circuit receives an alternating sequence signal of alternating high and low levels associated with the output delay of the memory system and a reference signal with a reference delay, and based on the alternating sequence signal and the The reference signal generates a comparison result signal indicating the range of the difference between the output delay and the reference delay; and wherein the reference signal is a signal having a predetermined frequency.
  • a method of operating the foregoing memory system including: determining whether the memory system is in one of the following predetermined conditions: a data reading state that is about to be in a non-speed adjustment reading state; The voltage change rate at the power input terminal of the power supply is greater than the predetermined rate threshold; the voltage at the power input terminal of the power supply is outside the voltage range corresponding to the current output delay; and the time from the current moment to the previous moment when the read speed of the memory system was last adjusted The time period is greater than the predetermined time period threshold.
  • a comparison circuit for generating a comparison result signal indicating a range of a difference between an output delay of a memory system and a reference delay
  • the comparison circuit is configured to receive a comparison with the output Delay the associated alternating sequence signal of alternating high and low levels, receive a reference signal with a predetermined frequency and the reference delay, and generate the comparison result signal based on the alternating sequence signal and the reference signal, wherein When the memory system performs a read operation, the memory system outputs a data signal with the output delay.
  • FIG. 1 is an exemplary block diagram of a memory system according to an embodiment of the present disclosure
  • FIG. 2 shows a method for adjusting the reading of a memory system according to an embodiment of the present disclosure. During the adjustment, a schematic diagram of changes in related signals and parameters over time;
  • Fig. 3 is a schematic diagram of a comparison circuit according to an embodiment of the present disclosure.
  • Fig. 4 is a schematic diagram of a comparison circuit according to an embodiment of the present disclosure.
  • Fig. 5 is a schematic diagram of a comparison circuit according to an embodiment of the present disclosure.
  • FIG. 6 is an exemplary block diagram of a memory system according to an embodiment of the present disclosure.
  • FIG. 7 is an exemplary block diagram of a memory system according to an embodiment of the present disclosure.
  • FIG. 8 is an exemplary block diagram of a memory system according to an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a method of generating a comparison result signal according to an embodiment of the present disclosure.
  • FIG. 10 shows the main steps of a method for adjusting the read speed of a memory system according to an embodiment of the present disclosure
  • FIG. 11 is a flowchart of a method of adjusting the read speed of a memory system according to an embodiment of the present disclosure
  • FIG. 12 is a flowchart of a method of operating a memory system according to an embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a method of adjusting the read speed of a memory system according to an embodiment of the present disclosure.
  • the objectives of the present disclosure include, but are not limited to: generating a comparison result signal indicating the range of the difference between the output delay of the memory system and the reference delay, and adjusting the read speed of the memory system as needed.
  • the inventor found through research that it is beneficial to adjust the read speed of the memory system according to the needs; by adjusting the read speed of the memory system, the appropriate power can be maintained, the yield of the product is improved, the accuracy of the output data is improved, and the yield is achieved. And the trade-off between dynamic power and reading speed. Based on the foregoing concept, the inventor designed the technical solution of the present disclosure.
  • the technical solution of the present disclosure can achieve at least one of the following effects: determine the comparison result signal indicating the range of the difference between the current output delay and the reference delay, adjust the reading speed of the memory system, reduce the power consumption of the memory system, and improve the performance of the memory system. Reading speed, improving the yield of the memory system, and realizing the trade-off between reading speed and yield and dynamic power.
  • a memory system with adjustable read speed may include, for example, a cache, a memory stick, a flash memory card, and a solid state drive.
  • the memory system is described below with reference to FIG. 1.
  • FIG. 1 is an exemplary block diagram of a memory system 100 according to an embodiment of the present disclosure.
  • the memory system 100 includes a memory 101, a reference signal generation circuit 103, and a comparison circuit 105.
  • the memory 101 includes a plurality of storage units and a control logic unit.
  • the storage unit is, for example, a semiconductor storage unit of the SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) type.
  • the memory system 100 may also have a memory controller (not shown in the figure).
  • FIG. 2 shows a schematic diagram of changes in related signals and parameters over time when adjusting the reading speed of the method for adjusting the reading of a memory system according to an embodiment of the present disclosure.
  • the signals received by the memory 101 include an operation command Op, an address signal Sadd, a clock signal Clk, and a delay control signal Dly.
  • the memory 101 includes a plurality of storage units.
  • FIG. 1 schematically shows a plurality of storage units with a plurality of blocks. Each storage unit has a corresponding address Add. After issuing a read instruction Op to read the memory cell corresponding to the address Add to the memory 101, and after a certain delay time, the memory 101 responds to the read instruction and outputs data indicating the stored data in the memory cell corresponding to the address Add signal.
  • the alternating sequence signal Sout has an inverted portion Sf of level inversion (see FIG. 2).
  • the output delay can be determined based on the inverted portion Sf.
  • a storage unit may refer to a storage bit that stores one binary bit. Two kinds of data can be stored in the storage bit: data "0" and data "1". It is shown in FIG. 1 that the signal input to the memory 101 includes an address signal Sadd. The memory 101 also receives a clock signal Clk to synchronize the memory.
  • the clock signal Clk may be a square wave with a fixed period p and a duty ratio of 50%.
  • the clock signal Clk has a rising edge and a falling edge, which respectively correspond to the rising and falling times of inversion.
  • the delay control signal Dly can determine the output delay tod.
  • the output delay tod of the memory 101 is controlled by the delay control signal Dly in its input signal, that is, different delay control signals Dly lead to different output delay tod.
  • the reference signal generating circuit 103 can be configured to generate a reference signal Sref having a predetermined frequency and a reference delay trd.
  • the reference signal Sref may be a square wave with a fixed period and a duty cycle of 50%.
  • the period of the reference signal Sref is, for example, 2p or np, and n is an integer greater than 2.
  • the reference delay trd can be defined as the time period corresponding to the difference between the turning time of the reference signal (for example, the rising turning time) and the turning time of the clock signal Clk.
  • the comparison circuit 105 can receive the alternating sequence signal Sout associated with the output delay tod of the memory system.
  • the comparison circuit 105 can also receive the reference signal Sref.
  • the comparison circuit 105 can also generate a comparison result signal Sc corresponding to the difference Dta between the output delay tod of the memory system and the reference delay trd of the reference output signal Sref based on the alternating sequence signal Sout and the reference signal Sref.
  • the time period corresponding to the difference Dta (take Dta1, Dta2, and Dta3 as examples) is shown in Figure 2. The length of this time period corresponds to the width of the rectangular pulse in the signal. When the absolute value of Dta is close to zero and too small, the figure The rectangular pulse is no longer shown.
  • the difference Dta may also correspond to the phase difference between the comparison signal and the reference signal.
  • the memory when a predetermined memory cell sequence in the memory 101 is read, the memory outputs an alternating sequence signal Sout with an output delay tod.
  • the alternating sequence signal Sout is composed of alternating high and low data signals.
  • tod t1-t0, where t0 is the time when the clock signal Clk indicates the start of reading (for example, the time corresponding to the rising edge), and t1 is the memory data The time at which a signal corresponding to the read data of the memory cell begins to appear at the output.
  • the delay control signal Dly will be described below.
  • the adjusted delay control signal Dly is generated based on the comparison result signal Sc so that the corresponding adjusted output delay tod approaches the reference delay trd or enters the predetermined range. For example, make the output delay tod close enough to the reference delay trd.
  • the delay control signal Dly is adjusted to change the output delay corresponding to the alternating sequence signal Sout, so that the difference Dta is Zero approach, that is, the output delay tod approaches the reference delay trd or enters the predetermined range.
  • the adjustment delay control signal Dly may be generated based on the control code Cc. That is, an appropriate control code Cc is generated based on the comparison result signal Sc, and the delay control signal Dly is generated using the control code Cc.
  • the delay control signal input to the memory may be generated by a control signal generator integrated in the memory system 100, for example.
  • FIG. 2 An example of generating the control code Cc is shown in FIG. 2, the adjustment parameter n is determined based on the comparison result signal Sc, and the control code Cc for generating the delay control signal is determined based on the adjustment parameter n.
  • the adjustment parameter n When the adjustment parameter n is zero, it indicates that the current output delay tod has met the predetermined reading speed requirement, the current control code Cc can be stored, and the reading speed adjustment operation is stopped (for example, the comparison circuit is instructed to stop working). After obtaining the control code Cc that meets the predetermined reading speed requirement, conventional data reading can be performed at the reading speed determined by the stored control code Cc.
  • the variation of the difference Dta, the adjustment parameter n and the control code Cc has been shown in FIG. 2.
  • Fig. 1 also shows a memory cell set Sm composed of a predetermined memory cell sequence.
  • the memory cell set Sm is used to adjust the reading speed.
  • a plurality of storage units including the first storage unit C1 and the first storage unit C1 and the first storage unit C1 in the storage unit set Sm for adjusting the reading speed of the memory system in the memory 101 can be set.
  • the storage data of the second storage unit C2) is such that when the multiple storage units in the storage unit set Sm are sorted according to the predetermined storage unit sequence, the data sequence of the corresponding storage data in the multiple storage units alternately appears in the first binary number and the second A second binary number that is different from the binary number.
  • the first storage cell C1 and the second storage cell C2 are adjacent, and the binary numbers stored in the first storage cell C1 and the second storage cell C2 are different from each other.
  • the storage unit set Sm is a column of storage units in the memory 101, and a predetermined storage unit sequence is formed in order from top to bottom.
  • a predetermined storage unit sequence is formed in order from top to bottom.
  • each storage unit of the storage unit set Sm is read in the order of the predetermined storage unit sequence, 0, 1 Alternate data sequence.
  • the alternating sequence signal Sout corresponds to a data sequence in which 0 and 1 appear alternately. It can be seen that the alternating sequence signal Sout can be generated by directly adjacently reading two storage bits in the memory system with different storage data in time.
  • the storage units in the storage unit set Sm may be ordinary storage units. In addition to adjusting the reading speed, these storage units can also be used to store general data. In this way, it is beneficial to increase the effective storage capacity of the memory.
  • multiple storage units in the storage unit set Sm may also be reserved storage units dedicated to adjusting the operating parameters of the memory system, and these reserved storage units are not used to store general data.
  • Such a memory cell set Sm may have been set when the memory is produced or tested.
  • the first binary number and the second binary number can be alternately stored in the corresponding storage unit in a predetermined sequence of storage units.
  • the read and write cycle of the reserved storage unit is the same or substantially the same as the read and write cycles of other storage units in the memory.
  • the read operation can be performed on the memory sequentially according to a predetermined unit sequence.
  • the read and write cycle of the reserved storage unit is the same or substantially the same as the read and write cycles of other storage units in the memory.
  • the reference signal Sref can be generated by a digital signal generator, or by a memory controller integrated with the digital signal generator, and the controller can control the operation of the memory.
  • comparison circuit various implementations of the comparison circuit of the present disclosure can be designed.
  • various flip-flops such as D flip-flops can be used to implement the comparison circuit.
  • FIG. 3 is a schematic diagram of a comparison circuit 305 according to an embodiment of the present disclosure.
  • the comparison circuit 305 includes five D flip-flops: D flip-flop D0, D flip-flop D1, D flip-flop D2, D flip-flop D3 and D flip-flop D4.
  • the output signals of the five D flip-flops are respectively : Out ⁇ 0>, Out ⁇ 1>, Out ⁇ 2>, Out ⁇ 3>, Out ⁇ 4>.
  • the comparison circuit 305 also includes a plurality of identical delay units DL, wherein each delay unit can delay the input signal and output by a delay time T (for example, 2 picoseconds). T can be used as a unit to measure the length of the output delay, and T is a positive value. As shown in FIG.
  • each D flip-flop receives the alternating sequence signal Sout or the delayed signal of the alternating sequence signal Sout; the second input terminal of each D flip-flop receives the reference output signal Sref or the reference output signal Sref. Delay the signal.
  • the comparison circuit 305 can be configured to generate a comparison result signal Sc, where the comparison result signal Sc indicates the range of the difference Dta between the output delay tod of the alternating sequence signal Sout and the reference delay trd of the reference output signal Sref.
  • the permutation and combination signals Out ⁇ 4:0> of the outputs Out ⁇ 4>, Out ⁇ 3>, Out ⁇ 2>, Out ⁇ 1> and Out ⁇ 0> of the 5 D flip-flops can be used as comparison Result signal Sc.
  • Table 1 shows the permutation and combination signals Out ⁇ 4:0> in the case of different difference Dta. It can be seen from Table 1 that different ranges of difference Dta correspond to different permutation and combination signals Out ⁇ 4:0>. Therefore, the delay control signal generation circuit that generates the delay control signal input to the memory can generate the delay control signal Dly based on the permutation and combination signal Out ⁇ 4:0> to adjust the read speed of the memory system.
  • the difference Dta is between 0 and -T, it is considered that the current output delay tod meets the requirement, and the current delay control signal Dly (corresponding to the current output delay tod) can be used to perform the data reading operation.
  • T is referred to as a predetermined time period in the present disclosure
  • -T is referred to as a predetermined negative value in the present disclosure.
  • n is an integer adjustment parameter, and different adjustment parameters n have a corresponding relationship with different comparison result signals Sc and different ranges.
  • the output delay tod may be adjusted based on the comparison result signal Sc, and a delay control signal Dly that causes the output delay adjusted based on the comparison result signal Sc is generated.
  • an adjusted delay control signal can be generated based on the comparison result signal each time so that the output delay is always reduced or increased for a predetermined period of time; or, during the adjustment period, n It is changed, so that the output delay corresponding to the adjusted delay control signal differs from the previous output delay by n times the predetermined time period, where n is an integer and n ⁇ 1.
  • n It is equal to the value obtained by rounding up Dta; when the difference Dta is within the boundary range (for example, the boundary range in Table 1: below -2T and above 2T), n is equal to the predetermined minimum or maximum adjustment parameter, that is, the difference Dta When in the upper boundary range, let n be equal to the predetermined maximum adjustment parameter (for example, 3 in Table 1), and when the difference Dta is in the lower boundary range, make n equal to the predetermined minimum adjustment parameter (for example, -2 in Table 1).
  • the current output delay tod is not adjusted.
  • the delay control signal Dly can be generated in a manner that satisfies the following conditions: the current output delay tod corresponding to the delay control signal Dly is different from the previous output delay tod' by a predetermined amount An integer multiple of a negative value, which is related to the difference Dta and the comparison result signal Sc, and is specifically selected as the adjustment parameter n.
  • more flip-flops are used in the comparison circuit 305, which is beneficial for adjusting the output delay to a predetermined target faster.
  • FIG. 4 is a schematic diagram of a comparison circuit 405 according to an embodiment of the present disclosure.
  • the comparison circuit 405 includes three D flip-flops: D flip-flop D8, D flip-flop D7, D flip-flop D6.
  • the output signals of the three D flip-flops are: Out ⁇ 0>, Out ⁇ 1> And Out ⁇ 2>.
  • the comparison circuit 405 also includes two identical delay units DL, where each delay unit can delay the input signal by a delay time T and output it.
  • the first input terminal of each D flip-flop receives the alternating sequence signal Sout or the delayed signal of the alternating sequence signal Sout; the second input terminal of each D flip-flop receives the reference output signal Sref or the reference output signal Sref. Delay the signal.
  • the comparison circuit 405 can be configured to generate a comparison result signal Sc, where the comparison result signal Sc indicates the range of the difference Dta between the output delay tod of the alternating sequence signal Sout and the reference delay trd of the reference output signal Sref.
  • the permutation and combination signal Out ⁇ 2:0> of the outputs Out ⁇ 2>, Out ⁇ 1>, and Out ⁇ 0> of the three D flip-flops can be used as the comparison result signal Sc.
  • Table 2 shows the permutation and combined signal Out ⁇ 2:0> in the case of different difference Dta. It can be seen from Table 2 that different ranges of difference Dta correspond to different permutation and combination signals Out ⁇ 2:0>. Therefore, the delay control signal generating circuit can generate the delay control signal Dly based on the permutation and combination signal Out ⁇ 2:0> to adjust the reading speed of the memory system.
  • the n in Table 2 is an integer adjustment parameter, which corresponds to the comparison result signal Sc one-to-one, and the adjustment parameter n can indicate the range of the difference Dta.
  • FIG. 5 is a schematic diagram of a comparison circuit 505 according to an embodiment of the present disclosure.
  • the comparison circuit 505 includes two D flip-flops: D flip-flop D10 and D flip-flop D9.
  • the output signals of the two D flip-flops are respectively: Out ⁇ 0> and Out ⁇ 1>.
  • the comparison circuit 505 also includes a delay unit DL, where the delay unit can delay the input signal by a delay time T and output it.
  • the first input terminal of each D flip-flop receives the alternating sequence signal Sout or the delayed signal of the alternating sequence signal Sout; the second input terminal of each D flip-flop receives the reference output signal Sref.
  • the comparison circuit 505 can generate a comparison result signal Sc, where the comparison result signal Sc indicates the range of the difference Dta between the output delay tod of the alternating sequence signal Sout and the reference delay trd of the reference output signal Sref.
  • the permutation and combination signal Out ⁇ 1:0> of the outputs Out ⁇ 1> and Out ⁇ 0> of the two D flip-flops can be used as the comparison result signal Sc.
  • Table 3 shows the permutation and combination signals Out ⁇ 1:0> in the case of different difference Dta. It can be seen from Table 3 that different ranges of difference Dta correspond to different permutation and combination signals Out ⁇ 1:0>. Therefore, the delay control signal generating circuit can generate the delay control signal Dly based on the permutation and combination signal Out ⁇ 1:0> to adjust the reading speed of the memory system.
  • n is an integer adjustment parameter, which corresponds to the comparison result signal Sc one-to-one, and n can indicate the range of the difference Dta.
  • each range of Dta includes the end value can be freely set, provided that each Dta can fall into a unique range.
  • the three ranges of Dta can be defined as: Dta>0, -T ⁇ Dta ⁇ 0 and Dta ⁇ -T; or Dta ⁇ 0, -T ⁇ Dta ⁇ 0 and Dta ⁇ -T.
  • the comparison circuit in the present disclosure may include at least two flip-flops.
  • the second input terminal of each flip-flop receives the reference output signal or the delayed signal of the reference output signal.
  • the first input terminal of each flip-flop receives the data output signal or the delayed signal of the data output signal.
  • the delay signal is generated by the delay unit.
  • the delay time of each delay unit can be T or different. Considering scalability and simplifying the operation logic, optionally, delay units with the same delay time can be used. Although the multiple delay units in FIGS. 3, 4, and 5 have the same delay amount, the present disclosure is not limited to this situation.
  • the delay unit used in the comparison circuit can also have different delay amounts, for example, one The delay unit realizes the delay effect of two series-connected delay units DL.
  • the memory system 100 can also be modified.
  • an example of a memory system obtained by deforming the memory system 100 will be described with reference to FIGS. 6, 7 and 8.
  • FIG. 6 is an exemplary block diagram of a memory system 600 according to an embodiment of the present disclosure.
  • the components of the memory system 600 that are the same as those of the memory system 100 in FIG. 1 will not be repeated.
  • the memory system 600 has a delay control signal generating circuit 607.
  • the delay control signal generating circuit 607 can generate different delay control signals Dly by using different control codes Cc, thereby causing different output delays tod. In this way, the delay control signal Dly can be updated according to the comparison result signal Sc, so as to obtain the expected output delay tod, and then the read speed of the memory system (also referred to as the read speed of the memory) can be adjusted.
  • the delay control signal generation circuit 607 can be realized by, for example, a digital z-transform filter. For example, a 1/(1-z-1) type digital z-transform filter or a 1/(1-0.5z-1-0.5z-2) type digital z-transform filter.
  • FIG. 7 is an exemplary block diagram of a memory system 700 according to an embodiment of the present disclosure.
  • the components of the memory system 700 that are the same as those of the memory system 600 in FIG. 6 will not be repeated.
  • the memory system 700 has an alternating sequence generator 709, and when adjusting the read speed of the memory system, the memory cell set Sm is no longer needed.
  • the third storage unit C3 may be a reserved storage location for adjusting the reading speed of the memory, and may have been preset to a predetermined binary number during production.
  • the data stored in the third storage unit C3 may be a first binary number (for example, "1") or a second binary number (for example, "0").
  • the alternating sequence generator 709 receives the additional signal Rd with a predetermined timing and the data signal Sd when reading the third memory cell C3 of the memory.
  • the alternate sequence generator 709 is configured so that when the read speed of the memory system is adjusted, the alternate sequence generator 709 outputs an alternate sequence signal Sout.
  • the alternate sequence signal Sout is high in the first clock cycle and is Low level.
  • the alternating sequence generator 709 includes an RS flip-flop, the S terminal of the RS flip-flop is connected to the data output signal Sd, the R terminal of the RS flip-flop is connected to the additional signal Rd, and the data stored in the third storage unit C3 is "1", then By setting the timing of the additional signal Rd, the alternating sequence signal Sout is at a high level in the first clock period and is at a low level in the second clock period.
  • the memory and the alternating sequence generator shown as an example in FIG. 7 are separate, alternatively, the alternating sequence generator may also be integrated in the memory.
  • the memory system 800 according to the present disclosure is described below with reference to FIG. 8, which can adjust the read speed of the memory system.
  • FIG. 8 is an exemplary block diagram of a memory system 800 according to an embodiment of the present disclosure.
  • the parts of the memory system 800 that are the same as those of the memory system 700 in FIG. 7 will not be repeated.
  • the memory system 800 has a delay control signal generation circuit 607.
  • the delay control signal generation circuit 607 generates a delay control signal Dly, and the output delay of the alternating sequence signal Sout caused by the delay control signal Dly can be a specified value.
  • the delay control signal Dly may be determined by the control code Cc stored in the delay control signal generating circuit 607, or may be given by the memory controller, for example.
  • the initial control code Cc can be a stored value or a value received from other components.
  • the delay control signal generating circuit 607 generates an adjusted delay control based on the comparison result signal Sc when the value indicated by the comparison result signal Sc is not a predetermined value (for example, the zero point of the adjustment parameter n, for example, 00111 in Table 1) Signal so that the corresponding adjusted output delay approaches or enters the predetermined range.
  • the adjustment parameter n is obtained from the comparison result signal Sc
  • Cc' is the current control code
  • the updated control code will cause the adjusted delay control Signal, and cause the corresponding adjusted output delay, the adjusted output delay can approach or enter the range trd to trd-T.
  • the conversion unit converts and arranges the combined signal Out ⁇ m:0>, and uses the converted signal as the comparison result signal Sc.
  • the permutation and combination signal "11111" is converted to "-2" and provided to the unit that generates the delay control signal.
  • the conversion unit may be realized by, for example, a digital multiplexer, in which the alternating sequence signal permutation combined signal Out ⁇ m:0> is used as the digital multiplexer control signal.
  • the memory system of the present disclosure includes a comparison circuit.
  • the comparison circuit can be used to adjust the read speed of the memory system.
  • the adjustment method can generally include the following steps: issuing a read instruction to the memory; generating a reference output signal Sref; generating a comparison result signal by the comparison circuit; determining an adjustment parameter n based on the comparison result signal Sc; determining a delay control signal based on the adjustment parameter n
  • the variation of the difference Dta, the adjustment parameter n and the control code Cc has been
  • An aspect of the present disclosure also provides a method of generating a comparison result signal. The method will be described below with reference to an example of the accompanying drawings.
  • FIG. 9 is a flowchart of a method 900 of generating a comparison result signal for adjusting the read speed of a memory system according to an embodiment of the present disclosure.
  • an alternating sequence signal Sout is generated. Specifically, an alternating sequence signal Sout in which high and low levels alternately appear in association with the output delay of the memory system is generated.
  • the alternating sequence signal can be generated by directly adjacently reading two storage bits in the memory system with different storage data in time. It is also possible to generate an alternating sequence signal by receiving an additional signal with a predetermined timing and a data signal when reading the storage bit of the memory system, which can be realized by an alternating sequence generator.
  • a reference signal Sref is generated. Specifically, a reference signal Sref of a square wave pattern having a predetermined frequency and a reference delay is generated. As shown in FIG. 2, the reference delay trd is an attribute parameter of the reference signal Sref.
  • a comparison result signal Sc is generated. Specifically, the comparison result signal Sc indicating the range of the difference between the output delay and the reference delay is generated based on the alternating sequence signal and the reference signal. This can be achieved through a comparison circuit.
  • the comparison circuit can be integrated in the memory system, or the comparison circuit can be designed as a separate device from the memory system. When an appropriate output delay needs to be determined, the comparison circuit is connected to the memory of the memory system.
  • An aspect of the present disclosure also provides a method of adjusting the read speed of a memory system. An exemplary description of this method will be made below with reference to the relevant drawings.
  • FIG. 10 shows the main steps of a method 1000 for adjusting the read speed of a memory system according to an embodiment of the present disclosure.
  • the method 1000 includes steps S1001, S1002, S1003, and S1004, wherein the steps S1001, S1002, and S1003 are the same as the steps S901, S902, and S903 in the method 900, respectively.
  • the comparison result signal is obtained according to step S1003, various subsequent steps can be used to adjust the reading speed of the memory system.
  • step S1004 it is determined whether the value indicated by the comparison result signal is a predetermined value, so as to adjust the reading speed of the memory system based on the determination result.
  • FIG. 11 is a flowchart of a method 1100 for adjusting the read speed of a memory system according to an embodiment of the present disclosure.
  • the method 1100 may be executed. After the method 1100 is over, a control code that is determined to meet the expected output delay tod will be obtained.
  • the control code can be used to generate a suitable delay control signal Dly, that is, the delay control signal Dly can cause the alternating sequence signal Sout when normal data is read.
  • the output delay is to meet the desired output delay, so as to achieve the read operation to meet the desired speed.
  • the storage data is set. In the case of using a storage unit set, set the storage data in multiple storage units in the storage unit set for adjusting the read speed of the memory system in the memory, so that when the multiple storage units are arranged in a predetermined storage unit sequence, more The data sequence of the corresponding stored data of the two storage units alternately presents a first binary number and a second binary number different from the first binary number.
  • the foregoing multiple storage units may be reserved storage units or Ordinary storage unit; in the case of using the third storage unit, the storage data of the third storage unit can be set to a predetermined value.
  • the third storage unit may be a reserved storage unit or a common storage unit.
  • an alternating sequence signal Sout is generated, which is an alternating sequence signal of alternating high and low levels associated with the output delay of the memory system.
  • the alternate sequence signal Sout can be realized by reading the memory cell set Sm, where the memory cells are read according to a predetermined memory cell sequence to obtain an alternate sequence signal Sout that alternates between high and low levels.
  • the alternating sequence signal Sout can be realized by an alternating sequence generator.
  • a reference signal Sref is generated.
  • the signal is a reference signal of a square wave pattern having a predetermined frequency and a reference delay.
  • the reference delay, an attribute parameter of the reference signal Sref, can be set to a predetermined value, that is, a desired output delay.
  • a comparison result signal Sc is generated.
  • a comparison result signal Sc indicating the range of the difference between the output delay and the reference delay is generated based on the alternating sequence signal and the reference signal.
  • the comparison result signal Sc can be, for example, the permutation and combination signal Out ⁇ 4:0> in Table 1. It can be understood that the arrangement and combination of the outputs of the triggers may also be other ways, for example, the arrangement and combination are in the order of Out ⁇ 0>, Out ⁇ 1>, Out ⁇ 2>, Out ⁇ 3>, Out ⁇ 4>.
  • step S1105 it is determined whether the value indicated by the comparison result signal is a predetermined value, for example, "00111" in Table 1.
  • the predetermined value corresponds to the zero point of the adjustment parameter n. It should be noted that although in Table 1, rounding up is used when determining the adjustment parameters, resulting in 00111 corresponding to the zero point of n, rounding down can also be used (that is, the positive direction of the number axis is taken as upward, and the adjacent The lower nearest integer of Dta), so that 00011 is regarded as the zero point of the adjustment parameter n.
  • step S1105 If it is determined at step S1105 that the value indicated by the comparison result signal Sc is a predetermined value, then proceed to step S1106.
  • the current control code is stored for use in subsequent normal data reading (relative to data reading when the reading speed is adjusted).
  • the control code can determine the output delay tod corresponding to the delay control signal Dly.
  • step S1107 the output delay control signal is adjusted.
  • the delay control signal is adjusted based on the alternating sequence signal so that the adjusted output delay approaches or enters a predetermined range.
  • the relationship between the control code Cc and the adjustment parameter n can be other reasonable forms, and their functional relationship can be determined according to actual conditions.
  • Cc Cc'+sign(n)
  • step S1107 After executing step S1107, return to step S1102 to generate a new alternating sequence signal.
  • Table 4 shows the changes of various parameters when the reading speed is adjusted.
  • the initial output delay is 8.6T
  • the reference delay is 4.0T
  • the comparison circuit used is the comparison circuit 305.
  • the adjustment parameter n becomes zero, that is, the value indicated by the comparison result signal Sc becomes the predetermined value "00111".
  • the changes of related signals and parameters over time in Fig. 2 correspond to Table 4.
  • the output delay tod is adjusted , And output the delay control signal Dly corresponding to the adjusted output delay.
  • the solution of the present disclosure is not limited to adjusting the output delay at the falling edge.
  • the exemplary choice is to adjust the read speed of the memory system every two clock cycles, that is, to adjust the output delay tod every two clock cycles.
  • the technical solution of the present disclosure is not limited to adjusting the read speed of the memory system once every two clock cycles.
  • the output delay tod can be adjusted every three clock cycles or more.
  • the present disclosure also provides a method of operating the aforementioned memory system. The method will be described below with reference to FIG. 12.
  • Figure 12 is a flowchart of a method 1200 of a memory system operating in accordance with the present disclosure.
  • step S1201 it is determined whether the memory system is in one of the following predetermined conditions: a) the data reading state to be in the non-speed adjustment read state; b) the voltage change rate at the power input end of the memory system is greater than the predetermined rate Threshold; c) the voltage at the power input terminal of the power supply is outside the voltage range corresponding to the current output delay; and d) the time period from the current time to the previous time when the read speed of the memory system was last adjusted is greater than the predetermined time period threshold.
  • the purpose is to adjust the reading speed before each ordinary reading, which is relative to the speed adjustment reading when adjusting the reading speed of the memory system.
  • the reading speed of the memory system can be adjusted by the voltage or the voltage change rate at the power input end of the memory.
  • step S1203 is executed to adjust the reading speed of the memory system.
  • step S1201 If the result of the determination at step S1201 is "No", the method 1200 ends.
  • the present disclosure also provides a method for adjusting the read speed of the memory system. The method will be described below with reference to FIG. 13.
  • FIG. 13 is a flowchart of a method 1300 for adjusting the read speed of a memory system according to an embodiment of the present disclosure.
  • the memory system is connected to the comparison circuit of the present disclosure.
  • the read speed of the memory system is adjusted by the connected comparison circuit until the value indicated by the comparison result signal is a predetermined value.
  • step S1305 the control code determining the delay control signal is stored.
  • the method 1300 is particularly suitable for the case where the memory system does not have a built-in comparison circuit of the present disclosure.
  • a comparison circuit that generates a comparison result signal indicating the range of the difference between the output delay of a memory system and the reference delay, and the comparison circuit is capable of receiving high and low level alternations associated with the output delay.
  • the appearing alternating sequence signal receives a reference signal of a square wave pattern with a predetermined frequency and a reference delay, and generates a comparison result signal corresponding to the difference between the output delay and the reference delay of the reference signal based on the number alternating sequence signal and the reference signal.
  • An example of a comparison circuit may be the comparison circuit 105 in FIG. 1.
  • the device for adjusting the reading speed of the memory system can achieve at least one of the following effects: determine the comparison result signal indicating the range of the difference between the current output delay and the reference delay, adjust the read speed of the memory system, reduce the power consumption of the memory system, increase the read speed of the memory system, and Improve the yield of the memory system (or memory) and realize the automatic trade-off between dynamic power and yield.
  • the methods of the present disclosure are not limited to being executed in the time sequence described in the specification, and if feasible in principle, they can also be executed in other time sequences, in parallel or independently. Therefore, the execution order of the methods described in this specification does not limit the scope of the present disclosure.

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Abstract

一种生成指示存储系统的输出延迟与基准延迟之间的差的范围的比较结果信号的方法包括：生成与所述输出延迟相关联的高低电平交替出现的交替序列信号（S901）；生成具有预定频率和所述基准延迟的基准信号（S902）；以及基于所述交替序列信号和所述基准信号生成所述比较结果信号（S903）。通过确定指示当前输出延迟与基准延迟的差的范围的比较结果信号，按照需要调节存储器系统的读取速度，降低存储器系统的不必要的功耗，以及提高存储器系统的良率。

Description

调节存储器系统的读取速度方法、比较电路及存储器系统 技术领域
本公开内容总体上涉及存储，更具体地，涉及生成指示存储器系统的输出延迟与基准延迟之间的差的范围的比较结果信号的方法、比较电路、调节存储器系统的读取速度的方法、存储器系统及操作该存储器系统的方法。
背景技术
近年来，为了提高信息处理设备的数据处理速度，存储器系统的工作频率越来越高。这意味着存储器系统的读取速度越来越快，数据输出信号的输出延迟越来越小，并且导致存储器系统的功耗越来越大。
发明内容
根据本公开内容的一个方面，提供了一种生成指示存储器系统的输出延迟与基准延迟的之间差的范围的比较结果信号的方法，包括：生成与所述输出延迟相关联的高低电平交替出现的交替序列信号；生成具有预定频率和所述基准延迟的基准信号；以及基于所述交替序列信号和所述基准信号生成所述比较结果信号。
根据本公开内容的一个方面，提供了一种调节存储器系统的读取速度的方法，包括：生成与所述存储器系统的输出延迟相关联的高低电平交替出现的交替序列信号；生成具有预定频率和基准延迟的基准信号；基于所述交替序列信号和所述基准信号生成指示所述输出延迟与所述基准延迟之间的差的范围的比较结果信号；以及确定所述比较结果信号指示的值是否为预定值以基于确定结果调节所述存储器系统的读取速度。
根据本公开内容的一个方面，提供了一种存储器系统，包括：存储器，包括多个存储单元，并且所述存储器输出具有输出延迟的交替序列信号；基准信号生成电路，生成具有预定频率和基准延迟的基准信号；比较电路，接收与所述输出延迟相关联的高低电平交替出现的交替序列信号和所述基准信号，并基于所述交替序列信号和所述基准信号生成比较结果信号，所述比较结果信号指示所述输出延迟与所述基准延迟之间的差的范围；以及延迟控制 信号生成电路，基于所述比较结果信号，生成用于调节所述存储器系统的输出延迟的延迟控制信号，其中，所述存储器接收所述延迟控制信号。
根据本公开内容的一方面，提供了一种调节存储器系统的读取速度的方法，包括：将所述存储器系统与比较电路连接；以及调节所述存储器系统的读取速度直到所述比较结果信号指示的值为预定值；其中，所述比较电路接收与存储器系统的输出延迟相关联的高低电平交替出现的交替序列信号和具有基准延迟的基准信号，以及基于所述交替序列信号和所述基准信号生成比较结果信号，所述比较结果信号指示所述输出延迟与所述基准延迟之间的差的范围；并且其中，所述基准信号为具有预定频率的信号。
根据本公开内容的一方面，提供了一种操作前述存储器系统的方法，包括：确定存储器系统是否处于以下预定情况中的一个：将要处于非速度调节读取状态的数据读取状态；存储器系统的电源电力输入端处的电压变化速率大于预定速率阈值；电源电力输入端处的电压在当前输出延迟对应的电压范围之外；以及从当前时刻到上次调节存储器系统的读取速度的先前时刻的时间段大于预定时间段阈值。
根据本公开内容的另一方面，提供了一种用于生成指示存储器系统的输出延迟与基准延迟之间的差的范围的比较结果信号的比较电路，该比较电路被配置成接收与所述输出延迟相关联的高低电平交替出现的交替序列信号，接收具有预定频率和所述基准延迟的基准信号，以及基于所述交替序列信号和所述基准信号生成所述比较结果信号，其中，在对所述存储器系统进行读取操作时，所述存储器系统以所述输出延迟输出数据信号。
附图说明
参照附图下面说明本公开内容的实施例，这将有助于更加容易地理解本公开内容的以上和其他目的、特点和优点。附图只是为了示出本公开内容的原理。在附图中不必依照比例绘制出单元的尺寸和相对位置。在附图中：
图1是根据本公开内容的一个实施例的存储器系统的示例性框图；
图2示出了根据本公开内容的一个实施例的调节存储器系统的读取的方法，在调节时，相关信号、参数随时间的变化的示意图；
图3是根据本公开内容的一个实施例的比较电路的示意图；
图4是根据本公开内容的一个实施例的比较电路的示意图；
图5是根据本公开内容的一个实施例的比较电路的示意图；
图6是根据本公开内容的一个实施例的存储器系统的示例性框图；
图7是根据本公开内容的一个实施例的存储器系统的示例性框图；
图8是根据本公开内容的一个实施例的存储器系统的示例性框图；
图9是根据本公开内容的一个实施例的生成比较结果信号的方法的流程图；
图10示出了根据本公开内容的一个实施例的调节存储器系统的读取速度的方法的主要步骤；
图11是根据本公开内容的一个实施例的调节存储器系统的读取速度的方法的流程图；
图12是根据本公开内容的一个实施例的操作存储器系统的方法的流程图；以及
图13是根据本公开内容的一个实施例的调节存储器系统的读取速度的方法的流程图。
具体实施方式
在下文中将结合附图对本公开内容的示例性实施例进行描述。为了清楚和简明起见，在说明书中并未描述实际实施例的所有特征。然而，应该了解，在开发任何这种实际实施例的过程中可以做出很多特定于实施例的决定，以便实现开发人员的具体目标，并且这些决定可能会随着实施例的不同而有所改变。
在此，还需要说明的一点是，为了避免因不必要的细节而模糊了本公开内容，在附图中仅仅示出了与根据本公开内容的方案密切相关的特征，而省略了与本公开内容关系不大的其他细节。
应理解的是，本公开内容并不会由于如下参照附图的描述而只限于所描述的实施形式。在本文中，在可行的情况下，实施例可以相互组合、一些步骤的顺序可以互换，不同实施例之间的特征替换或借用、在一个实施例中省略一个或多个特征，以上改变均应落在本公开的保护范围中。
存储器系统过高的读取速度，将导致存储器系统的功耗过大。在有些情 况下，并不需要过高的读取速度，因此希望读取速度是可调的。并且，过高的读取速度还会降低存储器系统的良率。本公开内容的目标包括但不限于：生成指示存储器系统的输出延迟与基准延迟之差的范围的比较结果信号，以及根据需要调节存储器系统的读取速度。
发明人经研究发现：根据需要调节存储器系统的读取速度是有益的；通过调节存储器系统的读取速度，可以维持适当的功率，提高产品的良率，改善输出数据的准确度，实现良率和动态功率与读取速度的折衷。基于前述构思，发明人设计了本公开内容的技术方案。
本公开内容的技术方案至少能实现如下效果之一：确定指示当前输出延迟与基准延迟的差的范围的比较结果信号，调节存储器系统的读取速度，降低存储器系统的功耗，提高存储器系统的读取速度、提高存储器系统的良率、实现读取速度与良率和动态功率的折衷。
根据本公开内容的一个方面，提供一种读取速度可调的存储器系统。存储器系统可以包括，例如，缓存、内存条、闪存卡、固态硬盘。下面参考图1描述该存储器系统。
图1是根据本公开内容的一个实施例的存储器系统100的示例性框图。存储器系统100包括存储器101、基准信号生成电路103、比较电路105。存储器101包括：多个存储单元和控制逻辑单元。存储单元例如为诸如SRAM(静态随机存取存储器)或DRAM(动态随机存取存储器)型的半导体存储单元。存储器系统100还可以具有存储器控制器(图中未示出)。
图2示出了根据本公开内容的一个实施例的调节存储器系统的读取的方法，在调节读取速度时，相关信号、参数随时间的变化的示意图。
如图1所示，存储器101接收的信号包括操作指令Op、地址信号Sadd、时钟信号Clk和延迟控制信号Dly。存储器101包括多个存储单元。图1中用多个方框示意性示出了多个存储单元。每个存储单元具有对应的地址Add。在向存储器101发出读取地址Add对应的存储单元的读取指令Op，并经过一定的延迟时间后，存储器101响应于该读取指令，输出指示地址Add对应的存储单元中的存储数据的数据信号。如果在时间上直接相邻地读取存储数据交替地为二进制“0”、“1”的预定存储单元序列，则可以得到由“0”数据信号、“1”数据信号交替出现(即高低电平交替出现)的交替序列信号 Sout，相应的，交替序列信号Sout具有电平翻转的翻转部分Sf(参见图2)。可以基于翻转部分Sf确定输出延迟。在本公开内容中，存储单元可以是指存储一个二进制位的存储位。存储位中可以存储两种数据：数据“0”和数据“1”。图1中示出了输入存储器101的信号包括地址信号Sadd。存储器101还接收时钟信号Clk以同步存储器。参见图2，时钟信号Clk可以为方波，具有固定的周期p，占空比为50％。时钟信号Clk具有上升沿和下降沿，分别对应上升翻转时刻和下降翻转时刻。延迟控制信号Dly能够决定输出延迟tod。存储器101的输出延迟tod是由其输入信号中的延迟控制信号Dly控制，即不同的延迟控制信号Dly导致不同的输出延迟tod。
基准信号生成电路103能够成生成具有预定频率和基准延迟trd的基准信号Sref。参见图2，基准信号Sref可以为方波，具有固定的周期，占空比为50％。基准信号Sref的周期例如为2p或np，n为大于2的整数。参见图2，可以将基准延迟trd定义为：基准信号的翻转时刻(例如，上升翻转时刻)与时钟信号Clk的翻转时刻的差所对应的时间段。
比较电路105能够接收与存储器系统的输出延迟tod相关联的交替序列信号Sout。比较电路105还能够接收基准信号Sref。比较电路105还能够基于交替序列信号Sout和基准信号Sref生成存储器系统的输出延迟tod与基准输出信号Sref的基准延迟trd之间的差Dta所对应的比较结果信号Sc。差Dta(以Dta1、Dta2、Dta3为例)所对应的时间段已在图2中示出，该时间段的长度对应信号中矩形脉冲的宽度，当Dta绝对值接近零且过小时，图中不再示出矩形脉冲。另外，能够理解的是，差Dta也可以与比较信号和基准信号之间的相位差对应。在图1中，在对存储器101中的预定存储单元序列进行读取操作时，存储器以输出延迟tod输出交替序列信号Sout。例如，当所读取的存储单元中存储的数据为第一二进制数(例如，“1”)时，则数据信号的波形呈现高电平状态，当所读取的存储单元中存储的数据为第二二进制数(例如“0”)时，则数据信号的波形呈现低电平状态。在本实施例中，交替序列信号Sout由交替的高低电平的数据信号构成。一种示例性的输出延迟tod的定义是：参见图2，tod＝t1-t0，其中，t0为时钟信号Clk指示读取开始的时刻(例如，上升沿对应的时刻)，t1为存储器的数据输出端开始出现对应所读取的存储单元的数据的信号的时刻。
下面对延迟控制信号Dly做出说明。在比较结果信号Sc指示的值不为预定值的情况下，基于比较结果信号Sc生成经调节的延迟控制信号Dly以使得相应的经调节的输出延迟tod靠近基准延迟trd或进入预定范围。例如，使输出延迟tod与基准延迟trd足够接近。如图2中所示，基于对应不同差Dta(Dta1,Dta2,Dta3)的比较结果信号Sc，调节延迟控制信号Dly，使交替序列信号Sout所对应的输出延迟发生变化，从而，使差Dta向零靠近，即输出延迟tod靠近基准延迟trd或进入预定范围。调节延迟控制信号Dly可以基于控制码Cc来生成。即，基于比较结果信号Sc生成合适的控制码Cc，利用控制码Cc生成延迟控制信号Dly。输入存储器的延迟控制信号，例如，可以由集成在存储器系统100的控制信号发生器生成。
生成控制码Cc的一个例子如图2所示，基于比较结果信号Sc确定调节参数n，基于调节参数n确定用于生成延迟控制信号的控制码Cc。例如，Cc＝Cc’+n，其中Cc’代表当前控制码。当前控制码Cc’＝5时，调节参数n＝3，则下一个控制码Cc＝5+3＝8。从图2可以看到，差Dta趋向于越来越小，调节参数n相应地越来越小。当调节参数n为零时，表明当前的输出延迟tod已满足预定读取速度需求，可以存储当前控制码Cc，并停止调节读取速度操作(例如，指示比较电路停止工作)。获得了满足预定读取速度需求的控制码Cc后，可以以由存储的控制码Cc确定的读取速度执行常规的数据读取。图2中已示出了差Dta、调节参数n和控制码Cc的变化。
图1中还示出了由预定存储单元序列构成的存储单元集Sm。存储单元集Sm用于调节读取速度。在进行调节读取速度期间，在进行读取操作前，可以设置存储器101中的用于调节存储器系统的读取速度的存储单元集Sm中的多个存储单元(包括第一存储单元C1和第二存储单元C2)的存储数据，使得按预定存储单元序列排序存储单元集Sm中的多个存储单元时，多个存储单元中相应存储数据的数据序列交替出现第一二进制数和与第一二进制数不同的第二二进制数。例如，按预定存储单元序列，第一存储单元C1和第二存储单元C2相邻，则第一存储单元C1和第二存储单元C2存储的二进制数彼此不同。例如，存储单元集Sm为存储器101中的一列存储单元，按从上到下排列顺序构成预定存储单元序列，在按预定存储单元序列顺序读取存储单元集Sm的各存储单元时，得到0、1交替出现的数据序列。参见图2中 具有翻转部分Sf的交替序列信号Sout，交替序列信号Sout对应0、1交替出现的数据序列。可见，可以通过在时间上直接相邻地读取存储器系统中的存储数据不同的两个存储位生成交替序列信号Sout。
存储单元集Sm中的存储单元可以为普通存储单元，这些存储单元除了用于调节读取速度，还可以用于存储一般的数据。采用这样的方式，有利于提高存储器的有效存储容量。可选地，存储单元集Sm中的多个存储单元也可以为专用于调节存储器系统的工作参数的预留存储单元，这些预留存储单元不用于存储一般的数据。这样的存储单元集Sm可以在生产或检测存储器时已被设定。为了调节存储器系统的读取速度，可以按预定存储单元序列顺序，交替地在相应存储单元中存储第一二进制数和第二二进制数。预留存储单元的读写周期与存储器中的其他存储单元的读写周期相同或基本相同。采用这样的方式，有利于减少调节读取速度的耗时。在调节存储器系统的读取速度时，可以按照预定单元序列顺序对存储器执行读取操作。预留存储单元的读写周期与存储器中的其他存储单元的读写周期相同或基本相同。
基准信号Sref可以由数字信号发生器产生，或者由集成有数字信号发生器的存储器控制器产生，控制器可以控制存储器的操作。
能够理解，根据上面对比较电路的描述，可以为本公开内容的比较电路设计出各种实现方式。作为一种示例性实现方式，可以使用诸如D触发器的各种触发器实现比较电路。
下面将对一种使用五个D触发器的比较电路进行描述。
图3是根据本公开内容的一个实施例的比较电路305的示意图。在图3中，比较电路305包括5个D触发器：D触发器D0、D触发器D1、D触发器D2、D触发器D3和D触发器D4。5个D触发器的输出信号分别为：Out<0>、Out<1>、Out<2>、Out<3>、Out<4>。比较电路305还包括多个相同的延迟单元DL，其中，每个延迟单元能够以延迟时间T(例如，2皮秒)延迟输入信号并输出。T可以作为衡量输出延迟的时间长度的单位，T为正值。如图3中所示，各D触发器的第一输入端接收交替序列信号Sout或交替序列信号Sout的延迟信号；各D触发器的第二输入端接收基准输出信号Sref或基准输出信号Sref的延迟信号。比较电路305能够成生成比较结果信号Sc，其中，比较结果信号Sc指示交替序列信号Sout的输出延迟tod与基准输出信号Sref 的基准延迟trd之间的差Dta的范围。在图3中，可以将5个D触发器的输出Out<4>、Out<3>、Out<2>、Out<1>和Out<0>的排列组合信号Out<4:0>作为比较结果信号Sc。
表1 比较结果信号
Out<4:0> Dta范围 n
11111 -2T以下(例如-2.5T) -2
01111 -T至-2T之间(例如-1.5T) -1
00111 0至-T之间(例如-0.5T) 0
00011 0至T之间(例如0.5T) 1
00001 T至2T之间(例如1.5T) 2
00000 2T以上(例如2.5T) 3
表1示出了不同差Dta情况下的排列组合信号Out<4:0>。从表1可知，不同的差Dta范围对应不同的排列组合信号Out<4:0>。从而，产生输入存储器的延迟控制信号的延迟控制信号生成电路可以基于排列组合信号Out<4:0>生成延迟控制信号Dly以调节存储器系统的读取速度。当差Dta在0至-T之间时，认为当前输出延迟tod满足需要，可以采用当前延迟控制信号Dly(对应当前输出延迟tod)进行数据读取操作。其中，T在本公开内容中被称为预定时间段，-T在本公开内容中称为预定负值。表1中的n为整数型调节参数，不同调节参数n与不同比较结果信号Sc及不同的范围有对应关系。在比较结果信号Sc指示的值不为预定值(例如，00111)的情况下，可以基于比较结果信号Sc调节输出延迟tod，并生成导致基于比较结果信号Sc调节后的输出延迟的延迟控制信号Dly。生成的延迟控制信号Dly所对应的输出延迟tod满足：tod＝tod’-nT，tod’为先前输出延迟。即，以预定时间段T为最小调节步长，调节输出延迟。调节输出延迟时，根据所用的比较电路的不同，可以每次基于比较结果信号生成经调节的延迟控制信号以使得总是将输出延迟减小或增大预定时间段；或者，在调节期间，n是变化的，使得经调节的延迟控制信号所对应的输出延迟与先前输出延迟相差预定时间段的n倍，n为整数且n≥1。当差Dta在边界范围之间的中间范围时(例如， 表1中的中间范围：-T至-2T之间、0至-T之间、0至T之间、T至2T之间)，n等于对Dta向上取整得到的值；当差Dta在边界范围内时(例如，表1中边界范围：-2T以下、2T以上)，n等于预定的最小调节参数或最大调节参数，即，当差Dta在上边界范围内时，使n等于预定的最大调节参数(例如表1中的3)，当差Dta在下边界范围内时，使n等于预定的最小调节参数(例如表1中的-2)。在本公开内容中，n＝0时，不对当前输出延迟tod进行调节。当先前输出延迟tod’过大时(例如，tod’＝8.6T,trd＝4.0T，Dta＝4.6T)，以减小方式调节输出延迟(例如，tod＝tod’-3T＝1.6T，n＝3)；当先前输出延迟tod’过小时(例如，tod’＝2.6T,trd＝4.0T，Dta＝-1.6T)，以增大方式调节输出延迟(例如，tod＝tod’-(-T)＝3.6T，n＝-1)。即，在差Dta在零至-T的范围之外的情况下，可以以满足以下条件的方式生成延迟控制信号Dly：延迟控制信号Dly所对应的当前输出延迟tod与先前输出延迟tod’相差预定负值的整数倍，该整数与差Dta及比较结果信号Sc相关，具体选择为调节参数n。在该例子中，比较电路305中使用的触发器较多，有利于较快地将输出延迟调节到预定目标。
作为另一个例子，下面将对一种使用三个D触发器的比较电路进行描述。
表2 比较结果信号
Out<2:0> Dta范围 n
111 -T以下(例如-1.5T) -1
011 0至-T之间(例如-0.5T) 0
001 0至T之间(例如0.5T) 1
000 T以上(例如1.5T) 2
图4是根据本公开内容的一个实施例的比较电路405的示意图。在图4中，比较电路405包括3个D触发器：D触发器D8、D触发器D7、D触发器D6。3个D触发器的输出信号分别为：Out<0>、Out<1>和Out<2>。比较电路405还包括两个相同的延迟单元DL，其中，每个延迟单元能够以延迟时间T延迟输入信号并输出。如图4中所示，各D触发器的第一输入端接收交替序列信号Sout或交替序列信号Sout的延迟信号；各D触发器的第二输入端接收基准输出信号Sref或基准输出信号Sref的延迟信号。比较电路405能够成生成比较结果信号Sc，其中，比较结果信号Sc指示交替序列信号Sout 的输出延迟tod与基准输出信号Sref的基准延迟trd之间的差Dta的范围。在图4中，可以将三个D触发器的输出Out<2>、Out<1>和Out<0>的排列组合信号Out<2:0>作为比较结果信号Sc。
表2示出了不同差Dta情况下的排列组合信号Out<2:0>。从表2可知，不同的差Dta范围对应不同的排列组合信号Out<2:0>。从而，延迟控制信号生成电路可以基于排列组合信号Out<2:0>生成延迟控制信号Dly以调节存储器系统的读取速度。表2中的n为整数型调节参数，与比较结果信号Sc一一对应，调整参数n可以指示差Dta所在的范围。与比较电路305相同，同样可以使用比较电路405依据等式tod＝tod’-nT调节存储器系统的读取速度。与图3所示的比较电路305相比，比较电路405结构比较简单，节约成本，但将输出延迟调节到预定目标的速度较慢。
作为另一个例子，下面将对一种使用两个D触发器的比较电路进行描述。
表3 比较结果信号
Out<1:0> Dta范围 n
11 -T以下(例如-1.5T) -1
01 0至-T之间(例如-0.5T) 0
00 0以上(例如0.5T) 1
图5是根据本公开内容的一个实施例的比较电路505的示意图。在图5中，比较电路505包括2个D触发器：D触发器D10、D触发器D9。2个D触发器的输出信号分别为：Out<0>、Out<1>。比较电路505还包括1个延迟单元DL，其中，延迟单元能够以延迟时间T延迟输入信号并输出。如图5中所示，各D触发器的第一输入端接收交替序列信号Sout或交替序列信号Sout的延迟信号；各D触发器的第二输入端接收基准输出信号Sref。比较电路505能够成生成比较结果信号Sc，其中，比较结果信号Sc指示交替序列信号Sout的输出延迟tod与基准输出信号Sref的基准延迟trd之间的差Dta的范围。在图5中，可以将两个D触发器的输出Out<1>和Out<0>的排列组合信号Out<1:0>作为比较结果信号Sc。
表3示出了不同差Dta情况下的排列组合信号Out<1:0>。从表3可知，不同的差Dta范围对应不同的排列组合信号Out<1:0>。从而，延迟控制信号生成电路可以基于排列组合信号Out<1:0>生成延迟控制信号Dly以调节存储 器系统的读取速度。表3中的n为整数型调节参数，与比较结果信号Sc一一对应，n可以指示差Dta所在的范围。与比较电路305相同，同样可以使用比较电路505依据等式tod＝tod’-nT调节存储器系统的读取速度。与比较电路305和比较电路405相比，比较电路505更加简单，在节约成本方面有优势。
能够理解，Dta的每个范围是否包括端值可以自由设定，前提是保证每个Dta都能落入唯一的范围。例如，对图5中的比较电路505，Dta的三个范围可以定义为：Dta>0、-T<Dta≤0以及Dta≤-T；或者Dta≥0、-T≤Dta<0以及Dta<-T。
根据上述描述，能够理解，本公开内容中的比较电路可以包括至少两个触发器。每个触发器的第二输入端接收基准输出信号或基准输出信号的延迟信号。每个触发器的第一输入端收数据输出信号或数据输出信号的延迟信号。延迟信号由延迟单元产生。每个延迟单元的延迟时间可以都为T，也可以不同。考虑到可扩展性，简化操作逻辑，可选地，可以使用具有相同延迟时间的延迟单元。虽然，图3、4、5中的多个延迟单元具有相同延迟量，但本公开内容并不限于这种情形，比较电路中使用的延迟单元也可以具有不同的延迟量，例如，使用1个延迟单元实现2个串联的延迟单元DL的延迟效果。
还可以对存储器系统100进行变形。下面参照图6、图7和图8描述通过对存储器系统100进行变形得到的存储器系统的例子。
图6是根据本公开内容的一个实施例的存储器系统600的示例性框图。存储器系统600具有的与图1中的存储器系统100相同的部件不再赘述。存储器系统600有延迟控制信号生成电路607。延迟控制信号生成电路607可以通过使用不同的控制码Cc来产生不同的延迟控制信号Dly，从而导致不同的输出延迟tod。由此，可以根据比较结果信号Sc更新延迟控制信号Dly，从而得到预期的输出延迟tod，进而可以调节存储器系统的读取速度(也可以称为：存储器的读取速度)。延迟控制信号生成电路607可以例如由数字z变换滤波器来实现。例如，1/(1-z-1)型数字z变换滤波器或1/(1-0.5z-1-0.5z-2)型数字z变换滤波器。
图7是根据本公开内容的一个实施例的存储器系统700的示例性框图。
存储器系统700具有的与图6中的存储器系统600相同的部件不再赘述。 存储器系统700具有交替序列生成器709，并且在调节存储器系统的读取速度时，不再需要存储单元集Sm。在调节存储器系统的读取速度时，对一个存储单元(在图7中示出为第三存储单元C3)进行读取即可。第三存储单元C3可以为用于调节存储器读取速度的预留存储位，可以在生产时已被预置为预定二进制数。第三存储单元C3存储的数据可以是第一二进制数(例如“1”)或第二二进制数(例如“0”)。交替序列生成器709接收具有预定时序的附加信号Rd以及读取存储器的第三存储单元C3时的数据信号Sd。配置交替序列生成器709使得在调节存储器系统的读取速度时，交替序列生成器709输出交替序列信号Sout，例如，交替序列信号Sout在第一时钟周期为高电平，在第二时钟周期为低电平。例如，交替序列生成器709包括RS触发器，RS触发器的S端接数据输出信号Sd，RS触发器的R端接附加信号Rd，第三存储单元C3存储的数据为“1”，则可以通过设置附加信号Rd的时序，使得交替序列信号Sout在第一时钟周期为高电平，在第二时钟周期为低电平。
虽然图7中作为例子示出的存储器与交替序列生成器是分立的，但是可选的，交替序列生成器也可以集成在存储器中。
下面参考图8描述根据本公开内容的存储器系统800，其能够调节存储器系统的读取速度。
图8是根据本公开内容的一个实施例的存储器系统800的示例性框图。存储器系统800具有的与图7中的存储器系统700相同的部分不再赘述。存储器系统800有延迟控制信号生成电路607。在正常数据读取时，延迟控制信号生成电路607生成延迟控制信号Dly，该延迟控制信号Dly导致的交替序列信号Sout的输出延迟可以为指定值。延迟控制信号Dly例如可以由延迟控制信号生成电路607存储的控制码Cc确定，或者由存储器控制器给出。延迟控制信号生成电路607启动后，初始控制码Cc可以为其存储的值或从其他部件接收到的值。延迟控制信号生成电路607在比较结果信号Sc指示的值不为预定值(例如，调节参数n的零点，例如，表1中的00111)的情况下，生成基于比较结果信号Sc经调节的延迟控制信号，以使得相应的调节后的输出延迟靠近或进入预定范围。例如，由比较结果信号Sc得到调节参数n，由调节参数n得到更新的控制码Cc，即Cc＝Cc’+n，Cc’为当前控制码，更新后的控制码将导致经调节的延迟控制信号，并导致相应的调节后的输出 延迟，该调节后的输出延迟可以靠近或进入范围trd至trd-T。
需要说明的是，如果排列组合信号Out<m:0>(m为触发器的最大编号，且编号从0开始)不能被延迟控制信号生成电路直接使用，可以在本公开内容的存储器系统中设置转换单元，以转换排列组合信号Out<m:0>，并将转换后得到的信号作为比较结果信号Sc。例如，将排列组合信号“11111”转换为“-2”，并提供给生成延迟控制信号的单元。转换单元例如可以由数字多路复用器来实现，其中，将交替序列信号排列组合信号Out<m:0>用作数字多路复用器控制信号。
返回至图1。输出延迟tod越小，存储器系统100中的存储器101的工作速度越快，功耗越大。标称的输出延迟tod越小，存储器的良率会越差。调节输出延迟tod可以实现调节存储器的工作速度和功耗，从而结合实际需要，选择合适的工作速度和功耗。
基于上述目的，本公开内容的存储器系统包括比较电路。从而可以使用比较电路调节存储器系统的读取速度。调节方式大体上可以包括以下步骤：向存储器发出读取指令；生成基准输出信号Sref；比较电路生成比较结果信号；基于比较结果信号Sc确定调节参数n；基于调节参数n确定用于生成延迟控制信号的控制码Cc，例如，Cc＝Cc’+n，其中Cc’为当前控制码；当调节参数n为零时，表明当前的输出延迟tod已满足预定读取速度需求，可以存储当前控制码Cc，并停止调节读取速度操作(例如，指令比较电路停止工作)。获得了满足预定读取速度需求的控制码Cc后，可以以由存储的控制码Cc确定的读取速度执行常规的数据读取。图2中已示出了差Dta、调节参数n和控制码Cc的变化。
本公开内容的一个方面还提供一种生成比较结果信号的方法。下面将参照附图的例子对该方法进行描述。
图9是根据本公开内容的一个实施例的生成用于调节存储器系统的读取速度的比较结果信号的方法900的流程图。
在步骤S901，生成交替序列信号Sout。具体而言，生成与存储器系统的输出延迟相关联的高低电平交替出现的交替序列信号Sout。可以通过在时间上直接相邻地读取存储器系统中的存储数据不同的两个存储位生成交替序列信号。也可以通过接收具有预定时序的附加信号和读取存储器系统的存储位 时的数据信号来生成交替序列信号，这可以由交替序列生成器来实现。
在步骤S902，生成基准信号Sref。具体而言，生成具有预定频率和基准延迟的方波样式的基准信号Sref。如图2中所示，基准延迟trd是基准信号Sref的一个属性参数。
在步骤S903，生成比较结果信号Sc。具体而言，基于交替序列信号和基准信号生成指示输出延迟与基准延迟之间的差的范围的比较结果信号Sc。这可以通过比较电路来实现。比较电路可以集成在存储器系统中，也可以将比较电路设计为与存储器系统分立的装置，在需要确定合适的输出延迟时，将比较电路与存储器系统的存储器连接。
本公开内容的一个方面还提供一种调节存储器系统的读取速度的方法。下面将参照相关附图该方法的做出示例性描述。
图10示出了根据本公开内容的一个实施例的调节存储器系统的读取速度的方法1000的主要步骤。方法1000包括步骤S1001、S1002、S1003和S1004，其中，步骤S1001、S1002和S1003分别与方法900中的步骤S901、S902、S903相同。根据步骤S1003得到比较结果信号后，可以使用各种后续步骤调节存储器系统的读取速度。例如，在方法1000中，在步骤S1004，确定比较结果信号指示的值是否为预定值，以基于确定结果来调节所述存储器系统的读取速度。
图11是根据本公开内容的一个实施例的调节存储器系统的读取速度的方法1100的流程图。
在接收到调节存储器系统读取指令后，可以执行方法1100。方法1100结束后，会得到确定满足期望的输出延迟tod的控制码，使用该控制码可以生成合适的延迟控制信号Dly，即，该延迟控制信号Dly能导致正常数据读取时，交替序列信号Sout的输出延迟为满足期望的输出延迟，从而实现以满足期望的速度进行读取操作。
在步骤S1101处，设置存储数据。在使用存储单元集的情况下，设置存储器中的用于调节存储器系统的读取速度的存储单元集中的多个存储单元中的存储数据，使得多个存储单元按预定存储单元序列排列时，多个存储单元的相应存储数据的数据序列交替地呈第一二进制数和与第一二进制数不同的第二二进制数，前述多个存储单元可以为预留存储单元也可以为普通存储单 元；在使用第三存储单元的情况下，可以将第三存储单元的存储数据设定为预定值。第三存储单元可以为预留存储单元也可以为普通存储单元。在步骤S1101处，如果设置所针对的存储单元为预留存储单元，则可以选择在存储器生产时，预留存储单元的存储数据已被设置。
在步骤S1102，生成交替序列信号Sout，该信号是与存储器系统的输出延迟相关联的高低电平交替出现的交替序列信号。交替序列信号Sout可以通过读取存储单元集Sm的方式实现，其中，按预定存储单元序列读取存储单元，以得到高低电平交替出现的交替序列信号Sout。可选的，交替序列信号Sout可以通过交替序列生成器来实现。
在步骤S1103，生成基准信号Sref，作为例子，该信号是具有预定频率和基准延迟的方波样式的基准信号。可以将基准信号Sref的属性参数——基准延迟设定为预定值，即，期望的输出延迟。
在步骤S1104，生成比较结果信号Sc。基于交替序列信号和基准信号生成指示输出延迟与基准延迟之间的差的范围的比较结果信号Sc。比较结果信号Sc可以例如为表1中的排列组合信号Out<4:0>。能够理解，各触发器的输出的排列组合方式还可以是其他方式，例如，以Out<0>、Out<1>、Out<2>、Out<3>、Out<4>顺序排列组合。
在步骤S1105，确定比较结果信号指示的值是否为预定值，例如，表1中的“00111”。该预定值与调节参数n的零点对应。需要说明的是，虽然在表1中，确定调整参数时用的是向上取整，导致00111对应n的零点，但是也可以采用向下取整(即，将数轴正方向取为向上，取邻近Dta的下近邻侧整数)，从而将00011当作调节参数n的零点。
如果在步骤S1105处，确定比较结果信号Sc指示的值为预定值，则进行至步骤S1106。在步骤S1106处，存储当前的控制码，以在后续的正常数据读取(相对于调节读取速度时的数据读取)时使用。该控制码能够确定延迟控制信号Dly所对应的输出延迟tod。
如果在步骤S1105处，确定比较结果信号Sc指示的值不为预定值，则进行至步骤S1107。在步骤S1107处，调节输出延迟控制信号。基于交替序列信号调节延迟控制信号以使得调节后的输出延迟靠近或进入预定范围。这里延迟控制信号的控制码Cc与调节参数n的关系不限于Cc＝Cc’+n。控制 码Cc与调节参数n的关系可以为其他合理形式，能够根据实际情况确定它们的函数关系。例如，Cc＝Cc’+sign(n)，sign(n)为正负性判断函数，n为正数时，sign(n)＝1，n为负数时，sign(n)＝-1，n为0时，sign(n)＝0，在这种情况下，tod＝tod’-sign(n)*T，即，在比较结果信号指示的值不为预定值的情况下，输出延迟总是被增大或减小预定时间段，其中，当n为正值时，减小输出延迟，当n为负值时，增大输出延迟。
执行完步骤S1107，返回步骤S1102以生成新的交替序列信号。
表4 调节读取速度时，各参数的变化
tod trd Dta n Cc
8.6T 4.0T 4.6T 3 5
5.6T 4.0T 1.6T 2 8
3.6T 4.0T -0.4T 0 10
为了便于理解，表4示出了调节读取速度时，各参数的变化，其中，示例性的，初始的输出延迟为8.6T，基准延迟为4.0T，使用的比较电路是比较电路305。在表4的示例中，调节了2次后，调节参数n变为零，即比较结果信号Sc指示的值成为预定值“00111”。图2中各相关信号、参数随时间的变化与表4对应。
返回到图2，在图2的示例中，在调节存储单元的读取速度时，在交替序列信号Sout和基准输出信号Sref的下降沿中较慢的一个所对应的时刻之后，调节输出延迟tod，并输出对应经调节的输出延迟的延迟控制信号Dly。但本公开内容的方案不限于在下降沿调节输出延迟。
在图2中，示例性的选择每两个时钟周期调节一次存储器系统的读取速度，即每两个时钟周期调节一次输出延迟tod。但是本公开内容的技术方案不限于每两个时钟周期调节一次存储器系统的读取速度。可以每三个时钟周期或更多时钟周期调节一次输出延迟tod。
本公开内容还提供一种操作前述存储器系统的方法。下面将参照图12对该方法进行描述。
图12是根据本公开内容的操作的存储器系统的方法1200的流程图。
在步骤S1201处，确定存储器系统是否处于以下预定情况中的一个：a)将要处于非速度调节读取状态的数据读取状态；b)存储器系统的电源电力输 入端处的电压变化速率大于预定速率阈值；c)电源电力输入端处的电压在当前输出延迟对应的电压范围之外；以及d)从当前时刻到上次调节存储器系统的读取速度的先前时刻的时间段大于预定时间段阈值。对情况a，目的是在每次要进行普通读取前，先调节读取速度，该普通读取是相对于调节存储器系统的读取速度时的速度调节读取而言的。对情况b，对应电源波动过大，为了保证读出数据的准确性和读取速度，调节读取速度。对情况c，认为读取速度与电源电压相关，当电源电压变化到另一范围内时，相应的也调节读取速度。对情况d，其可以实现定期调节读取速度。另外，可选的，可以存储器的电力输入端处的电压或电压变化率调节存储器系统的读取速度。
如果在步骤S1201处确定结果为“是”，则执行步骤S1203，调节存储器系统的读取速度。
如果在步骤S1201处确定结果为“否”，则方法1200结束。
本公开内容还提供一种调节存储器系统的读取速度的方法。下面将参照图13对该方法进行描述。
图13是根据本公开内容的一个实施例的调节存储器系统的读取速度的方法1300的流程图。
在步骤S1301处，将存储器系统与本公开内容的比较电路连接。
在步骤S1303处，利用连接的比较电路调节存储器系统的读取速度直到比较结果信号指示的值为预定值。
在步骤S1305处，存储确定延迟控制信号的控制码。
方法1300尤其适用于存储器系统未内置本公开内容的比较电路的情况。
根据本公开内容的一个方面，提供一种生成指示存储器系统的输出延迟与基准延迟之间的差的范围的比较结果信号的比较电路，该比较电路能够接收与输出延迟相关联的高低电平交替出现的交替序列信号，接收具有预定频率和基准延迟的方波样式的基准信号，以及基于数交替序列信号和基准信号生成输出延迟与基准信号的基准延迟之间的差所对应的比较结果信号。一种比较电路的示例可以是图1中的比较电路105。
根据上面对本公开内容的具体实施例的描述，本领域技术人员能够理解，本公开内容的调节存储器系统的读取速度的装置、存储器系统、调节存储器系统的读取速度的方法及操作该存储器系统的方法至少能实现如下效果之 一：确定指示当前输出延迟与基准延迟的差的范围的比较结果信号，调节存储器系统的读取速度，降低存储器系统的功耗，提高存储器系统的读取速度以及提高存储器系统(或存储器)的良率，实现动态功率与良率的自动折衷。
应该理解，术语“包括”在本文使用时指特征、整件、步骤或组件的存在，但并不排除一个或多个其他特征、整件、步骤或组件的存在或附加。
应该理解，在不偏离本公开内容的精神的情况下，针对一个实施例描述和/或示出的特征可以以相同或类似的方式在一个或多个其他实施例中使用，与其他实施例中的特征相组合，或替代其他实施例中的特征。
此外，本公开内容的方法不限于按照说明书中描述的时间顺序来执行，如果从原理上说可行，也可以按照其他的时间顺序地、并行地或独立地执行。因此，本说明书中描述的方法的执行顺序不对本公开内容的范围构成限制。
以上结合具体的实施例对本公开内容进行了描述，但本领域技术人员应该清楚，这些描述都是示例性的，并不是对本公开内容的保护范围的限制。本领域技术人员可以根据本公开内容的精神和原理对本公开内容做出各种变型和修改，这些变型和修改也在本公开内容的范围内。

Claims (26)

  1. 一种生成指示存储系统的输出延迟与基准延迟之间的差的范围的比较结果信号的方法，包括：
    生成与所述输出延迟相关联的高低电平交替出现的交替序列信号；
    生成具有预定频率和所述基准延迟的基准信号；以及
    基于所述交替序列信号和所述基准信号生成所述比较结果信号。
  2. 根据权利要求1所述的方法，其中，通过在时间上直接相邻地读取所述存储器系统中的存储数据不同的两个存储位生成所述交替序列信号。
  3. 根据权利要求2所述的方法，其中，所述两个存储位为专用于调节所述存储器系统的工作参数的预留存储位。
  4. 根据权利要求1所述的方法，其中，基于具有预定时序的附加信号和读取所述存储器系统的存储位时的数据信号来生成所述交替序列信号。
  5. 根据权利要求4所述的方法，其中，所述存储位为专用于调节所述存储器系统的工作参数的预留存储位。
  6. 一种调节存储器系统的读取速度的方法，包括：
    生成与所述存储器系统的输出延迟相关联的高低电平交替出现的交替序列信号；
    生成具有预定频率和基准延迟的基准信号；
    基于所述交替序列信号和所述基准信号生成指示所述输出延迟与所述基准延迟之间的差的范围的比较结果信号；以及
    确定所述比较结果信号指示的值是否为预定值以基于确定结果调节所述存储器系统的读取速度。
  7. 根据权利要求6所述的方法，还包括：在所述比较结果信号指示的值不为预定值的情况下，基于所述比较结果信号生成经调节的延迟控制信号以使得相应的经调节的输出延迟靠近或进入预定范围。
  8. 根据权利要求7所述的方法，其中，基于所述比较结果信号生成经调节的延迟控制信号以使得相应的经调节的输出延迟靠近或进入预定范围包括：
    基于所述比较结果信号调节用于所述延迟控制信号的控制码；以及
    基于经调节的延迟控制信号的控制码生成新的交替序列信号。
  9. 根据权利要求7所述的方法，其中，基于所述交替序列信号和所述基准信号生成指示所述输出延迟与所述基准延迟之间的差的范围的比较结果信号包括：
    延迟所述基准信号和或所述交替序列信号预定时间段的第一整数倍。
  10. 根据权利要求9所述的方法，其中，在所述比较结果信号指示的值不为预定值的情况下，基于所述比较结果信号生成经调节的延迟控制信号以使得相应的经调节的输出延迟靠近或进入预定范围包括以满足以下条件的方式生成所述经调节的延迟控制信号：所述经调节的延迟控制信号所对应的输出延迟与先前输出延迟相差所述预定时间段的第二整数倍。
  11. 根据权利要求10所述的方法，其中，基于所述比较结果信号生成经调节的延迟控制信号以使得相应的经调节的输出延迟靠近或进入预定范围包括：基于所述比较结果信号生成经调节的延迟控制信号以使得总是将所述输出延迟减小或增大所述预定时间段。
  12. 根据权利要求6所述的方法，还包括：在所述比较结果信号指示的值为预定值的情况下，存储当前用于所述延迟控制信号的控制码。
  13. 根据权利要求6所述的方法，其中，所述存储器系统的存储器的输入信号包括具有时钟周期的时钟信号，并且每两个或更多个所述时钟周期调节一次所述延迟控制信号。
  14. 一种存储器系统，包括：
    存储器，包括多个存储单元，并且所述存储器输出具有输出延迟的交替序列信号；
    基准信号生成电路，生成具有预定频率和基准延迟的基准信号；
    比较电路，接收与所述输出延迟相关联的高低电平交替出现的交替序列信号和所述基准信号，并基于所述交替序列信号和所述基准信号生成比较结果信号，所述比较结果信号指示所述输出延迟与所述基准延迟之间的差的范围；以及
    延迟控制信号生成电路，基于所述比较结果信号，生成用于调节所述存储器系统的输出延迟的延迟控制信号，
    其中，所述存储器接收所述延迟控制信号。
  15. 根据权利要求14所述的存储器系统，其中，所述延迟控制信号生成 电路，在所述比较结果信号指示的值不为预定值的情况下，基于所述比较结果信号生成经调节的延迟控制信号，以使得相应的经调节的输出延迟靠近或进入预定范围。
  16. 根据权利要求15所述的存储器系统，其中，所述延迟控制信号生成电路基于所述比较结果信号调节用于所述延迟控制信号的控制码。
  17. 根据权利要求14所述的存储器系统，还包括：
    交替序列生成器，接收具有预定时序的附加信号和读取所述存储器系统的存储单元时的数据输出信号并生成所述交替序列信号。
  18. 根据权利要求14所述的存储器系统，其中，所述比较电路包括至少两个触发器；
    所述至少两个触发器中的每个的第二输入端接收所述基准信号或所述基准信号的延迟信号；并且
    所述至少两个触发器中的每个的第一输入端接收所述交替序列信号或所述交替序列信号的延迟信号。
  19. 根据权利要求18所述的存储器系统，其中，所述比较电路包括多个延迟单元，并且所述多个延迟单元具有相同的延迟时间。
  20. 一种调节存储器系统的读取速度的方法，包括：
    将所述存储器系统与比较电路连接；以及
    调节所述存储器系统的读取速度直到所述比较结果信号指示的值为预定值；
    其中，所述比较电路接收与存储器系统的输出延迟相关联的高低电平交替出现的交替序列信号和具有基准延迟的基准信号，以及基于所述交替序列信号和所述基准信号生成比较结果信号，所述比较结果信号指示所述输出延迟与所述基准延迟之间的差的范围；并且
    其中，所述基准信号为具有预定频率的信号。
  21. 根据权利要求20所述的方法，还包括：
    存储确定延迟控制信号的控制码。
  22. 一种操作权利要求14所述存储器系统的方法，包括：
    确定所述存储器系统是否处于以下预定情况中的一个：
    将要处于非速度调节读取状态的数据读取状态；
    所述存储器系统的电源电力输入端处的电压变化速率大于预定速率阈值；
    所述电源电力输入端处的电压在当前输出延迟对应的电压范围之外；以及
    从当前时刻到上次调节所述存储器系统的读取速度的先前时刻的时间段大于预定时间段阈值。
  23. 根据权利要求22所述的方法，还包括：
    在确定结果为是的情况下，调节所述存储器系统的读取速度。
  24. 一种用于生成指示存储器系统的输出延迟与基准延迟之间的差的范围的比较结果信号的比较电路，被配置成接收与所述输出延迟相关联的高低电平交替出现的交替序列信号，接收具有预定频率和所述基准延迟的基准信号，以及基于所述交替序列信号和所述基准信号生成所述比较结果信号；
    其中，在对所述存储器系统进行读取操作时，所述存储器系统以所述输出延迟输出数据信号。
  25. 根据权利要求24所述的比较电路，包括至少两个触发器；
    其中，所述至少两个触发器中的每个的第二输入端被配置成接收所述基准信号或所述基准信号的延迟信号；并且
    所述至少两个触发器中的每个的第一输入端被配置成接收所述数据输出信号或所述数据输出信号的延迟信号。
  26. 根据权利要求25所述的比较电路，其中，所述比较电路包括多个延迟单元，并且所述多个延迟单元具有相同的延迟时间。
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