CN113130410A - 覆晶接合结构及其线路基板 - Google Patents
覆晶接合结构及其线路基板 Download PDFInfo
- Publication number
- CN113130410A CN113130410A CN202010554734.XA CN202010554734A CN113130410A CN 113130410 A CN113130410 A CN 113130410A CN 202010554734 A CN202010554734 A CN 202010554734A CN 113130410 A CN113130410 A CN 113130410A
- Authority
- CN
- China
- Prior art keywords
- width
- branch
- along
- bump
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1405—Shape
- H01L2224/14051—Bump connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
本发明是一种覆晶接合结构及其线路基板。该覆晶接合结构具有线路基板、芯片及焊料层,该芯片设置于该线路基板的内接合区,该焊料层位于该线路基板及该芯片之间,用以将凸块接合于该内接合区内的多个内引脚及T型线路,该T型线路具有主线段、连接段及支线段,该连接段连接该主线段及该支线段,该主线段沿着横向方向延伸,该支线段沿着纵向方向朝向该内接合区延伸,该连接段的宽度小于该主线段的宽度,以避免该焊料层溢流至该支线段而造成桥接短路。
Description
技术领域
本发明关于一种覆晶接合结构,特别是一种具有T型线路的覆晶接合结构。
背景技术
覆晶封装技术大多使用热压合方式,使焊料受热软化以接合芯片及基板,于热压合过程中,软化的焊料会沿着线路朝向凸块流动,然而当凸块邻近线宽较宽的线路时,线路上的焊料会以较快的速度受热软化而流向凸块,导致凸块周围发生焊料过量而溢流的情形,甚至发生桥接短路而降低良率。
发明内容
本发明的目的在于提供一种具有T型线路的覆晶接合结构,借由缩小T型线路连接段的宽度,有效避免因焊料溢流而桥接短路的情形发生。
本发明揭露一种覆晶接合结构,其包含线路基板、芯片及焊料层,该线路基板具有载板、多个内引脚及至少一个T型线路,该载板的表面定义有内接合区,该内接合区包含第一内接合区及第二内接合区,所述内引脚位于该第一内接合区,该T型线路位于该第二内接合区,该T型线路具有主线段、连接段及支线段,该主线段连接该连接段并沿着横向方向延伸,该支线段连接该连接段并沿着纵向方向朝向该第一内接合区延伸,该主线段沿着该纵向方向具有第一宽度,该连接段沿着该纵向方向具有第二宽度,该第二宽度小于该第一宽度,该芯片设置于该内接合区且具有多个第一凸块及至少一个第二凸块,该焊料层位于该线路基板及该芯片之间,所述第一凸块借由该焊料层接合于所述内引脚,该第二凸块借由该焊料层接合于该支线段。
较佳地,其中该支线段沿着该纵向方向朝向其中之一该内引脚延伸。
较佳地,其中该支线段沿着该纵向方向延伸至相邻两个该内引脚之间。
较佳地,其中该支线段具有第一端及第二端,该第一端连接该连接段,该第二端接合该第二凸块,该第一端的线宽大于该第二端的线宽。
较佳地,其中该支线段沿着该横向方向具有第三宽度,该第二宽度与该第三宽度的比值不小于0.5。
较佳地,其中该第二凸块沿着该横向方向具有第四宽度,该第二宽度与该第四宽度的比值小于2。
较佳地,其中该第二宽度及该第四宽度相同。
较佳地,其中该连接段沿着该横向方向具有第一长度,该第二凸块沿着该纵向方向具有第二长度,该第一长度与该第二长度的比值不小于4。
较佳地,其中该连接段至该第二凸块之间具有直线距离,该直线距离与该第二宽度的比值不小于3。
较佳地,其中该焊料层的厚度不大于0.30μm。
本发明另揭露一种线路基板,其包含载板、多个内引脚及至少一个T型线路,该载板具有表面,该表面定义有内接合区,该内接合区包含第一内接合区及第二内接合区,所述内引脚位于该第一内接合区,该T型线路位于该第二内接合区,该T型线路具有主线段、连接段及支线段,该主线段连接该连接段并沿着横向方向延伸,该支线段连接该连接段并沿着纵向方向朝向该第一内接合区延伸,该支线段用以接合凸块,该主线段沿着该纵向方向具有第一宽度,该连接段沿着该纵向方向具有第二宽度,该第二宽度小于该第一宽度。
较佳地,其中该支线段沿着该纵向方向朝向其中之一该内引脚延伸。
较佳地,其中该支线段沿着该纵向方向延伸至相邻两个该内引脚之间。
较佳地,其中该支线段具有第一端及第二端,该第一端连接该连接段,该第二端用以接合该凸块,该第一端的线宽大于该第二端的线宽。
较佳地,其中该支线段沿着该横向方向具有第三宽度,该第二宽度与该第三宽度的比值不小于0.5。
较佳地,其另包含焊料层,该焊料层形成于该支线段,该支线段借由该焊料层与该凸块接合。
较佳地,其中该焊料层的厚度不大于0.30μm。
当接合该线路基板及该芯片时,该焊料层会受热软化而从不同方向流向该支线段上的凸块接合处,因此本发明缩小该连接段宽度,减少自该连接段流向该支线段的焊料量,以避免焊料自凸块接合处向外溢流而导致桥接短路。
附图说明
图1:依据本发明之一较佳实施例,载板的俯视图。
图2:依据本发明之一较佳实施例,覆晶接合结构的俯视图。
图3:依据本发明之一较佳实施例,线路基板的内接合区的局部俯视图。
图4:依据本发明之一较佳实施例,线路基板的内接合区的局部俯视图。
图5:依据本发明之一较佳实施例,线路基板的内接合区的局部俯视图。
图6:依据本发明之一较佳实施例,线路基板的内接合区的局部俯视图。
图7:依据本发明之一较佳实施例,线路基板的内接合区的局部俯视图。
图8:沿图7A-A剖线的剖视图。
【主要元件符号说明】
100:线路基板 110:载板
111:表面 112:外接合区
113:内接合区 113a:第一内接合区
113b:第二内接合区 120:外引脚
130:内引脚 140:T型线路
141:主线段 142:连接段
143:支线段 143a:第一端
143b:第二端 200:芯片
210:第一凸块 220:第二凸块
300:防焊层 400:焊料层
500:封装胶体 D1:横向方向
D2:纵向方向 I:覆晶接合结构
L1:第一长度 L2:第二长度
LD:直线距离 W1:第一宽度
W2:第二宽度 W3:第三宽度
W4:第四宽度
具体实施方式
请参阅图1至图3,本发明揭露一种覆晶接合结构I,其可为薄膜覆晶封装结构(Chip on Film,COF)、玻璃覆晶封装结构(Chip on Glass,COG)或其他覆晶封装结构,该覆晶接合结构I包含线路基板100及芯片200,该线路基板100具有载板110、多个外引脚120及多个内引脚130,该载板110可由聚酰亚胺(polyimide,PI)、聚对苯二甲酸乙二酯(polyethylene terephthalate,PET)、玻璃、陶瓷、金属或其他材料所制成,该载板110具有表面111,所述外引脚120及所述内引脚130形成于该表面111,该表面111定义有二个外接合区112及内接合区113,所述外接合区112分别位于该载板110的两侧,该内接合区113位于所述外接合区112之间,所述外引脚120位于所述外接合区112内,所述内引脚130位于该内接合区113内。
请参阅图2及图3,较佳地,该覆晶接合结构I另具有防焊层300,该防焊层300覆盖该载板110的该表面111,并显露所述外接合区112及该内接合区113,该芯片200设置于该内接合区113,在本实施例中,该芯片200是借由热压合技术接合于所述内引脚130上,所述外引脚120用以接合外部装置(图未绘出)。
请参阅图3及图4,该内接合区113包含第一内接合区113a及第二内接合区113b,所述内引脚130位于该第一内接合区113a,该线路基板100另具有至少一个T型线路140,该T型线路140位于该第二内接合区113b,该T型线路140与所述内引脚130之间无电性连接,是用以接地或接电源,较佳地,该内接合区113包含二个第一内接合区113a,所述第一内接合区113a位于两侧,该第二内接合区113b位于所述第一内接合区113a之间,所述内引脚130沿着该内接合区113两侧边缘排列,该T型线路140位于两侧的所述内引脚130之间,较佳地,所述内引脚130及该T型线路140是经由图案化铜箔基材所形成。
请参阅图3及图4,其为本发明之一实施例,该T型线路140具有主线段141、连接段142及支线段143,该主线段141连接该连接段142并沿着横向方向D1延伸,该支线段143连接该连接段142并沿着纵向方向D2朝该第一内接合区113a延伸,该支线段143用以接合该芯片200的凸块,在本实施例中,该连接段142与该支线段143相互垂直,但本发明不以此为限制,该连接段142及该支线段143之间的夹角可大于、小于或等于90度。
较佳地,该线路基板100具有多个T型线路140,各该T型线路140的该主线段141沿着该横向方向D1相互连接,各该T型线路140的该支线段143沿着该纵向方向D2分别朝向该第一内接合区113a延伸。
图5、图6及图7为不同实施例的该支线段143,图5所示的该支线段143是沿着该纵向方向D2朝向其中之一该内引脚130延伸,但未连接该内引脚130,图6所示的该支线段143是沿着该纵向方向D2延伸至相邻两个该内引脚130之间,图7所示的该支线段143具有第一端143a及第二端143b,该第一端143a连接该连接段142,该第二端143b用以接合该芯片200的凸块,其中该第一端143a的线宽大于该第二端143b的线宽,以避免该连接段142与该支线段143之间发生断裂,较佳地,该第二端143b位于相邻两个该内引脚130之间。
请参阅图3至图8,该芯片200具有多个第一凸块210及至少一个第二凸块220,该覆晶接合结构I另具有焊料层400,该焊料层400位于该线路基板100及该芯片200之间,所述第一凸块210借由该焊料层400接合于所述内引脚130,该第二凸块220借由该焊料层400接合于该支线段143,较佳地,该焊料层400的厚度不大于0.30μm,更佳地,该焊料层400的厚度不大于0.20μm,在本实施例中,该线路基板100包含该焊料层400,该焊料层400形成于所述内引脚130及该T型线路140的该主线段141、该连接段142及该支线段143,其厚度为0.16μm±0.4μm,当接合该芯片200及该线路基板100时,所述内引脚130借由该焊料层400与所述第一凸块210接合,该支线段143借由该焊料层400与该第二凸块220接合。
请参阅图7,在本实施例中,该支线段143的该第二端143b是用以接合该第二凸块220,因此当该芯片200接合于该线路基板100时,该第二端143b借由该焊料层400接合该第二凸块220。
请参阅图8,较佳地,该覆晶接合结构I另具有封装胶体500,该封装胶体500填充于该线路基板100及该芯片200之间,该封装胶体500可为底部填充胶(underfill),但本发明不以此为限制。
该焊料层400于热压合过程中会受热软化而具有流动性,当该第二凸块220接合于该支线段143时,位于该T型线路140上的该焊料层400会从不同方向流向该第二凸块220的接合处而增加溢流的发生率,为了避免发生桥接短路,本发明针对该T型线路140进行布线设计。
请参阅图4,该主线段141沿着该纵向方向D2具有第一宽度W1,该连接段142沿着该纵向方向D2具有第二宽度W2,该第二宽度W2小于该第一宽度W1,借由缩小该连接段142宽度,有效降低从该连接段142流向该支线段143的焊料量,因此可避免过多的焊料流向该第二凸块220而发生溢流,较佳地,该支线段143沿着该横向方向D1具有第三宽度W3,该第二宽度W2与该第三宽度W3的比值不小于0.5其中当比值介于0.5及1时 表示该第二宽度W2小于该第三宽度W3,当比值等于1时表示该第二宽度W2等于该第三宽度W3,当比值大于1时表示该第二宽度W2大于该第三宽度W3,在本实施例中,该支线段143的线宽与所述内引脚130的线宽相同。
请参阅图5,该第二凸块220沿着该横向方向D1具有第四宽度W4,该第二宽度W2与该第四宽度W4的比值小于2其中比值可介于1及2之间即该第二宽度W2大于该第四宽度W4,但小于两倍的该第四宽度W4,比值可等于1使该第二宽度W2及该第四宽度W4相同,比值亦可介于0及1之间使该第二宽度W2小于该第四宽度W4,布线设计时可根据该第二凸块220的宽度决定该连接段142的宽度,使该第二宽度W2与该第四宽度W4的比值小于2。
请参阅图6,该连接段142沿着该横向方向D1具有第一长度L1,该第二凸块220沿着该纵向方向D2具有第二长度L2,该第一长度L1与该第二长度L2的比值不小于4使该连接段142长度不小于4倍的该第二凸块220长度,因此可根据该第二凸块220的长度决定需要缩小宽度的该连接段142长度,在本实施例中,该支线段143位于该连接段142中央,即该支线段143至该连接段142两端的最短距离相同,但本发明不以此为限制,该支线段143可根据不同布线设计需求选择性地偏向该连接段142的其中一端。
请参阅图6,该连接段142边缘至该第二凸块220边缘之间具有直线距离LD,该直线距离LD为该连接段142与该第二凸块220之间的最短距离,当该焊料层400的厚度增加时,需要提高该直线距离LD与该第二宽度W2的比值,也就是该直线距离LD与该第二宽度W2的比值必须与该焊料层400的厚度成正比,以避免过多的焊料于热压合过程中流动至该支线段143与该第二凸块220的接合处,而造成桥接短路,较佳地,当该焊料层400的厚度为0.16μm时,该直线距离LD与该第二宽度W2的比值须不小于3使该直线距离LD大于或等于3倍的该第二宽度W2,当该焊料层400的厚度为0.18μm时,该直线距离LD与该第二宽度W2的比值须不小于4使该直线距离LD大于或等于4倍的该第二宽度W2。
为了避免过多的该焊料层400自该T型线路140流向该第二凸块220,本发明缩小该连接段142的宽度,借此减少自该连接段142流向该支线段143的焊料量,并可根据不同需求,选择性地调整该连接段142的宽度、长度及其与该第二凸块220之间的距离,以大幅降低因焊料溢流而桥接短路的发生率,有效提升产品良率。
本发明的保护范围当视申请专利范围所界定者为准,任何熟知此项技艺者,在不脱离本发明的精神和范围内所作的任何变化与修改,均属于本发明的保护范围。
Claims (17)
1.一种覆晶接合结构,其特征在于,其包含:
线路基板,具有载板、多个内引脚及至少一个T型线路,该载板的表面定义有内接合区,该内接合区包含第一内接合区及第二内接合区,所述内引脚位于该第一内接合区,该T型线路位于该第二内接合区,该T型线路具有主线段、连接段及支线段,该主线段连接该连接段并沿着横向方向延伸,该支线段连接该连接段并沿着纵向方向朝该第一内接合区延伸,该主线段沿着该纵向方向具有第一宽度,该连接段沿着该纵向方向具有第二宽度,该第二宽度小于该第一宽度;
芯片,设置于该内接合区,该芯片具有多个第一凸块及至少一个第二凸块;以及
焊料层,位于该线路基板及该芯片之间,所述第一凸块借由该焊料层接合于所述内引脚,该第二凸块借由该焊料层接合于该支线段。
2.根据权利要求1所述的覆晶接合结构,其特征在于,其中该支线段沿着该纵向方向朝向其中之一该内引脚延伸。
3.根据权利要求1所述的覆晶接合结构,其特征在于,其中该支线段沿着该纵向方向延伸至相邻两个该内引脚之间。
4.根据权利要求1所述的覆晶接合结构,其特征在于,其中该支线段具有第一端及第二端,该第一端连接该连接段,该第二端接合该第二凸块,该第一端的线宽大于该第二端的线宽。
5.根据权利要求1所述的覆晶接合结构,其特征在于,其中该支线段沿着该横向方向具有第三宽度,该第二宽度与该第三宽度的比值不小于0.5。
6.根据权利要求1所述的覆晶接合结构,其特征在于,其中该第二凸块沿着该横向方向具有第四宽度,该第二宽度与该第四宽度的比值小于2。
7.根据权利要求6所述的覆晶接合结构,其特征在于,其中该第二宽度及该第四宽度相同。
8.根据权利要求6所述的覆晶接合结构,其特征在于,其中该连接段沿着该横向方向具有第一长度,该第二凸块沿着该纵向方向具有第二长度,该第一长度与该第二长度的比值不小于4。
9.根据权利要求1所述的覆晶接合结构,其特征在于,其中该连接段至该第二凸块之间具有直线距离,该直线距离与该第二宽度的比值不小于3。
10.根据权利要求1所述的覆晶接合结构,其特征在于,其中该焊料层的厚度不大于0.30μm。
11.一种线路基板,其特征在于,其包含:
载板,具有表面,该表面定义有内接合区,该内接合区包含第一内接合区及第二内接合区;
多个内引脚,位于该第一内接合区;以及
至少一个T型线路,位于该第二内接合区,该T型线路具有主线段、连接段及支线段,该主线段连接该连接段并沿着横向方向延伸,该支线段连接该连接段并沿着纵向方向朝该第一内接合区延伸,该支线段用以接合凸块,该主线段沿着该纵向方向具有第一宽度,该连接段沿着该纵向方向具有第二宽度,该第二宽度小于该第一宽度。
12.根据权利要求11所述的线路基板,其特征在于,其中该支线段沿着该纵向方向朝向其中之一该内引脚延伸。
13.根据权利要求11所述的线路基板,其特征在于,其中该支线段沿着该纵向方向延伸至相邻两个该内引脚之间。
14.根据权利要求11所述的线路基板,其特征在于,其中该支线段具有第一端及第二端,该第一端连接该连接段,该第二端用以接合该凸块,该第一端的线宽大于该第二端的线宽。
15.根据权利要求11所述的线路基板,其特征在于,其中该支线段沿着该横向方向具有第三宽度,该第二宽度与该第三宽度的比值不小于0.5。
16.根据权利要求11所述的线路基板,其特征在于,其另包含焊料层,该焊料层形成于该支线段,该支线段借由该焊料层与该凸块接合。
17.根据权利要求16所述的线路基板,其特征在于,其中该焊料层的厚度不大于0.30μm。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108148760A TWI711347B (zh) | 2019-12-31 | 2019-12-31 | 覆晶接合結構及其線路基板 |
TW108148760 | 2019-12-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113130410A true CN113130410A (zh) | 2021-07-16 |
Family
ID=74202524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010554734.XA Pending CN113130410A (zh) | 2019-12-31 | 2020-06-17 | 覆晶接合结构及其线路基板 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11581283B2 (zh) |
JP (1) | JP6989653B2 (zh) |
KR (1) | KR102408726B1 (zh) |
CN (1) | CN113130410A (zh) |
TW (1) | TWI711347B (zh) |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2655112B2 (ja) * | 1994-12-22 | 1997-09-17 | 日本電気株式会社 | 光モジュールの実装方法および構造 |
JP3886659B2 (ja) * | 1999-01-13 | 2007-02-28 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置 |
TW551011B (en) * | 2002-12-10 | 2003-09-01 | Silicon Integrated Sys Corp | High-density circuit board without bonding pad design and the manufacturing method thereof |
JP2004296718A (ja) * | 2003-03-26 | 2004-10-21 | Fuji Photo Film Co Ltd | プリント配線板、及び駆動回路基板の製造方法 |
TWI226111B (en) * | 2003-11-06 | 2005-01-01 | Himax Tech Inc | Semiconductor packaging structure |
JP2007266070A (ja) * | 2006-03-27 | 2007-10-11 | Fujikura Ltd | プリント回路基板及びプリント回路基板接続構造 |
US7394164B2 (en) * | 2006-07-28 | 2008-07-01 | Ultra Chip, Inc. | Semiconductor device having bumps in a same row for staggered probing |
JP5547594B2 (ja) * | 2010-09-28 | 2014-07-16 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
US20120261689A1 (en) * | 2011-04-13 | 2012-10-18 | Bernd Karl Appelt | Semiconductor device packages and related methods |
US8548848B1 (en) * | 2011-06-21 | 2013-10-01 | Google Inc. | Mobile interstitial ads |
JP5809500B2 (ja) * | 2011-09-16 | 2015-11-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8633588B2 (en) * | 2011-12-21 | 2014-01-21 | Mediatek Inc. | Semiconductor package |
US9659893B2 (en) * | 2011-12-21 | 2017-05-23 | Mediatek Inc. | Semiconductor package |
US9553040B2 (en) * | 2012-03-27 | 2017-01-24 | Mediatek Inc. | Semiconductor package |
JP6028908B2 (ja) * | 2012-07-27 | 2016-11-24 | セイコーエプソン株式会社 | 半導体装置 |
TW201603227A (zh) * | 2014-07-15 | 2016-01-16 | 頎邦科技股份有限公司 | 微間距圖案之佈線結構 |
KR102219296B1 (ko) * | 2014-08-14 | 2021-02-23 | 삼성전자 주식회사 | 반도체 패키지 |
US9520853B2 (en) * | 2015-03-09 | 2016-12-13 | Raytheon Company | Radio frequency (RF) series attenuator module for bridging two RF transmission lines on adjacent circuit substrates |
TWI657545B (zh) * | 2018-03-12 | 2019-04-21 | 頎邦科技股份有限公司 | 半導體封裝結構及其線路基板 |
TWI712136B (zh) * | 2020-02-26 | 2020-12-01 | 頎邦科技股份有限公司 | 覆晶接合結構及其線路基板 |
-
2019
- 2019-12-31 TW TW108148760A patent/TWI711347B/zh active
-
2020
- 2020-06-17 CN CN202010554734.XA patent/CN113130410A/zh active Pending
- 2020-06-17 KR KR1020200073577A patent/KR102408726B1/ko active IP Right Grant
- 2020-06-17 JP JP2020104396A patent/JP6989653B2/ja active Active
- 2020-06-24 US US16/910,461 patent/US11581283B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US11581283B2 (en) | 2023-02-14 |
TWI711347B (zh) | 2020-11-21 |
JP6989653B2 (ja) | 2022-01-05 |
JP2021111771A (ja) | 2021-08-02 |
KR102408726B1 (ko) | 2022-06-13 |
US20210202422A1 (en) | 2021-07-01 |
TW202127966A (zh) | 2021-07-16 |
KR20210086935A (ko) | 2021-07-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7193328B2 (en) | Semiconductor device | |
US7477523B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
JP2002026072A (ja) | 半導体装置の製造方法 | |
US8889483B2 (en) | Method of manufacturing semiconductor device including filling gap between substrates with mold resin | |
KR102375544B1 (ko) | 플립칩 접합 구조 및 그 회로 기판 | |
CN113130410A (zh) | 覆晶接合结构及其线路基板 | |
US8072069B2 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
CN107924847B (zh) | 安装结构以及模块 | |
US8050049B2 (en) | Semiconductor device | |
US7687321B2 (en) | Method for manufacturing semiconductor device | |
TWI582929B (zh) | 晶片封裝結構 | |
CN113133183A (zh) | 覆晶接合结构及其线路基板 | |
TWI773257B (zh) | 可撓性線路基板及薄膜覆晶封裝結構 | |
CN214279951U (zh) | 半导体封装结构 | |
US20230197666A1 (en) | Chip packaging structure and method for preparing the same, and method for packaging semiconductor structure | |
CN220796738U (zh) | 封装结构 | |
CN115249681A (zh) | 薄膜覆晶封装结构 | |
KR20240040509A (ko) | 칩 온 필름 패키지 및 이를 포함하는 디스플레이 장치 | |
JP3687674B2 (ja) | 半導体装置、半導体チップ、電子モジュール並びに電子機器 | |
CN116613133A (zh) | 电子封装件及其基板结构 | |
JP2014027126A (ja) | 半導体装置 | |
JP2009170684A (ja) | 半導体装置、配線基板、半導体装置の製造方法、及び配線基板の製造方法 | |
KR20090022777A (ko) | 반도체 패키지 제조용 스트립 레벨 기판 | |
JPH08330714A (ja) | 半導体フラットパッケージの表面実装方法及び半導体フラットパッケージ用実装配線板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |