CN1130801A - 电容器制造方法 - Google Patents

电容器制造方法 Download PDF

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CN1130801A
CN1130801A CN95120211A CN95120211A CN1130801A CN 1130801 A CN1130801 A CN 1130801A CN 95120211 A CN95120211 A CN 95120211A CN 95120211 A CN95120211 A CN 95120211A CN 1130801 A CN1130801 A CN 1130801A
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capacitor
dielectric
metal
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deck
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约瑟夫·鲁道夫·拉多斯维奇
兰比尔·辛格
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/014—Capacitor

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Abstract

一种制造集成电路中的金属极板电容器的方法包括在由层间电介质形成图案的多晶硅上形成一层钛/氮化钛。然后沉积电容器电介质，接下来用光刻胶形成图案、勾划出电容器，进行腐蚀以除去额外的电介质，沉积铝，再进一步形成图案并进行腐蚀以确定电容器和存取区域，而后除去光刻胶。

Description

电容器制造方法
本发明涉及电容器制造方法，具体地说是涉及集成电路中制造金属极板电容器的方法。
电容器广泛用于电子装置中来储存电荷。电容器基本上包括两个由绝缘体分开的导电板。电容、或每单位电压电容器储存的电荷用法拉来度量，由电容器板的面积，两板间的距离和绝缘体的介电系数决定。电容器用于滤波器，模数转换器(ADC)，存储器，和各种控制应用中。
集成电路中的电容器通常由多晶硅、金属与多晶硅或金属与多晶化物结构制成。在多数应用中，如在模数转换器(ADC)中，需要电容不随电压变化的电容器。电容随所加电压变化的大小叫做电容的电压系数(VoC)，用百万分率作单位。通常，用于集成电路中的电容器的VoC不是零(50-300PPM)，因此需要消除。采用零点法的电路技术假定VoC随电压的变化(不为零时)是电压的线性函数，这一假设对集成电路电容器无效。此外，虽然采用这些技术提高了ADC的精度和分辨率，但会耗用芯片面积，增加芯片成本。如果电容器的VoC小于π个PPM，就不需要采用零点电路技术，从而可降低电路的复杂性和成本。
Paterson等人的美国专利No.5108941公开一种制造金属与多晶硅型电容器的方法，这种电容器与多晶硅型电容器相比具有较低的VoC。在Paterson等人的方法中，电容器底板制作在场氧化结构上，其上沉积多层电介质。从电容器区域除去多层电介质，沿露出的底板和多层电介质用低压化学蒸气相沉积法(LPCVD)沉积一层氧化/氮化电介质。第一层钛/钨最好在接触腐蚀前沉积，然后形成与隔离壕和无关多晶硅的接触。金属化部分被完全溅射，金属和钛/钨被消除以留下填充接触孔的金属化部分和具有钛/钨及金属顶板的电容器。
在任何生产工艺中，简化都是个优点。因而，用同样成本的材料实现同样或更好质量的产品却采用较少步骤的生产方法是再好不过了，尤其是在去除的生产步骤减少了劳动力成本和对昂贵的生产设备的需要的情况下。
另外，生产集成电路的工艺步骤需要有灵活性。尤其是具有模块化的电容器制造过程非常有利，模块化的过程可作为选项加入到现有的数字化程序，而不会改变后续操作。如美国专利No.5108941所设想的那样在多晶硅上加一层硅化金属(多晶化物)需要将整个多晶硅层硅化以实现最佳电压稳定性。然而，硅化大大减小了工艺的灵活性。例如，对于硅化结构，为了退火、扩散、驱动掺杂剂、抹平层间电介质及类似目的而对集成电路进行热处理，限于低于850℃的温度。能够采用850℃以上的温度以及能够在集成电路生产的各阶段制成低VoC的电容器将非常有利。
这里提供一种低VoC的金属极板电容器和在集成电路中制造这种电容器的方法。该方法包括在导电衬底上形成场介电层；形成包括一层与所述导电多晶硅层电接触第一金属的电容器底板；和形成包括一层在所述电容器电介质上的第二金属的电容器顶板。
底板最好包括一层具有氮化钛涂层的钛。顶板最好是铝。电容器电介质最好是二氧化硅或氧化硅/电介质。
最好是，该方法还包括形成与所述场介电层接触的导电多品硅层并在形成电容器底板前在导电多晶硅层上沉积一种层间电介质(如二氧化硅)。
为使相关领域的技术人员能更好地了解如何实现本发明的方法，下面将参考附图详细描述该方法的最佳实施例。其中：
图1是本发明电容器10的剖面图；
图2至6是说明制造本发明电容器各个步骤的剖面图。
图1是根据这里描述的方法制造的金属极板电容器10的剖面图。电容器10包括下极板14，电介质层15，和上极板17。这些层可选择地迭加在多晶硅层12的上面，多晶硅层12在位于硅衬底18上的场氧化(FOX)电介质层11上形成。衬底18可以是P型或N型硅。
电容器10的下极板14可由任何适于导电和存储电荷的金属制成，如铝、铜、银、钛，或贵重金属如金、铂、钯、及类似金属。最好是，下面的极板14是一由镀有一层氮化钛(TiN)14b的钛(Ti)层14a。14层的厚度约为0.04微米到0.15微米，其中钛层14a的厚度约为0.01微米到0.05微米，TiN层的厚度约为0.03微米到0.10微米。
层15可由任何合适的电介质制成(如二氧化硅SiO2和/或氮化硅)并且厚度通常约为0.01微米到0.10微米，取决于电容器的电气要求。
电容器的顶板17可是任何适合制造集成电路电容器的金属。铝是制造顶板17优选的金属。铝可选择性地用铜或硅掺杂，或者可能是多层金属结构的部分。
制造具有低VoC的金属极板电容器10的方法在图2到图6中说明。
参考图2，多晶硅板12在场氧化层11(SiO2)上形成图案。场氧化层11用本领域众所周知的方法(如局域氧化或沉积)制作在硅衬底18上。相类似地，多晶硅的图案形成在本领域也为人熟知。于是层间电介质13以适当的图形被沉积以使多晶硅层12与上覆的金属化层绝缘。层间电介质13最好是二氧化硅，其可被任意掺杂，也可以是氮化硅或任何其它具有适于这里所描述应用的性质的材料。此时的结构如图2所示。
多晶硅12最好重掺杂以使其具有相当导电性，如同在常规集成电路中一样。通常多晶硅层通过扩散、离子注入、或原地掺杂将被n掺杂。应当注意，多晶硅层12不用作电容器10的底板，因此是任选的。然而，其用作将电荷导入及导出底板14的引线，因而有利于将电容器10并入集成电路。与美国专利No.5108941相反的是，这里的多晶硅层12不需要为获得电容器的最佳VoC性能而硅化。另外，其它的导电材料可以替代多晶硅，如铝、铜、银、钛或贵重金属如金，铂，钯及类似金属。
参考图3，通过沉积一层钛(Ti)14a和氮化钛(TiN)14b，制成底板14，最好是溅射沉积。氮化钛可在沉积了一定厚度的钛金属后通过使氮气注入钛溅射靶室被就地沉积。这样，氮化钛就形成了覆盖钛的薄膜，用来阻挡下面所讨论的后续工艺步骤的腐蚀。
接下来沉积电容器电介质15。通过在Ti/TiN层14上用化学气相沉积(CVD)法或等离子体增强的化学气相沉积(PECVD)法先沉积四乙氧基硅烷(TEOS)形成电介质层。TEOS分解后形成SiO2附着层15。尽管这里将电容器电介质描述成二氧化硅，技术人员应该知道其它材料也可起到电容器电介质的作用。例如，电容器电介质15可由氮化硅或铁电体材料(如BaTiO3)制成。由此，电容器就可用光刻胶16a掩膜，光刻胶用来描绘电容器10的边沿。这时的构造如图3所示。
参考图4，电容器的电介质层15用湿刻法(当电介质是二氧化硅时)如乙二醇/缓冲的氟化氢溶液或干刻法如反应溅射蚀刻刻去。TiN耐这种腐蚀，起阻挡腐蚀的作用。此时的构造如图4所示。
在下个步骤，光刻胶16a被剥去，铝层17被沉积。电容器10制成在留有电容器电介质的区域，其中电容器层包括钛—氮化钛—二氧化硅—铝。
接下来，铝层17用掩膜材料即光刻胶16b和16c形成图案，光刻胶部分被暴光并按常规的光刻技术冲洗以确定隔离槽16d，其用来使集成电路的表面暴露于腐蚀剂。光刻胶部分16b确定电容器10的界限，终止在氧化层15。所产生的构造如图5所示。
最后，将铝充分地过腐蚀，以除去位于隔离槽16d处的电介质15和钛—氮化钛基层14。然后剥去光刻胶部分16b和16c。所产生的构造如图6所示。构造19通过包含导电的铝层17和Ti/TiN层14成为接点，还通过多晶硅层12提供到电容器10的底板14的电通路。
虽然参考最佳实施例描述了本发明，但有关领域的普通技术人员很容易知道，可由此进行变化和修改而没有脱离所附权利要求规定的本发明的精神和范围。

Claims (20)

1.一种制造电容器的方法，其包括：
a)在导电衬底上形成场介电层；
b)形成由与所述导电多晶硅层电连接的第一金属层构成的电容器底板；
c)形成与所述电容器底板接触的电容器电介质层；
d)在所述电容器电介质层上形成由第二金属层构成的电容器顶板。
2.根据权利要求1所述的方法，其中所述形成电容器底板的步骤还包括在所述第一金属层上面形成一层导电的腐蚀阻挡层。
3.根据权利要求2所述的方法，其中所述第一金属是钛。
4.根据权利要求2所述方法，其中所述导电腐蚀阻挡层是氮化钛。
5.根据权利要求1所述的方法，其中所述第二金属是铝。
6.根据权利要求1所述的方法，其中所述电容器电介质是二氧化硅。
7.根据权利要求1所述的方法还包括步骤：
a)形成与所述场介电层接触导电多晶硅层；
b)形成电容器底板之前在所述导电多晶硅层上沉积一定图案的层间电介质。
8.权利要求7所述的方法，其中所述所述层间电介质由二氧化硅制成。
9.一种在集成电路中制造电容器的方法，其包括：
a)在导电衬底上形成场介电层；
b)形成与所述场介电层相接的导电多晶硅层；
c)在所述导电多晶硅层上沉积一定图案的层间电介质；
d)形成完整的一层第一金属；
e)形成完整的一层与所述第一金属接触电容器电介质；
f)用第一光刻胶覆盖所述电容器电介质被选择的部分，以勾划出电容器的边缘；
g)除去电容器电介质未被第一光刻胶覆盖的部分；
h)除去所述第一光刻胶；
i)涂敷完整的一层第二金属；
j)在所述一层第二金属被选择的部分涂敷第二光刻胶，所述第二光刻胶形成图案来确定要蚀刻的区域；
k)除去所述的由第二光刻胶确定的蚀刻区域中的第一金属、第二金属或电容器电介质；
l)除去所述第二光刻胶。
10.权利要求9所述的方法，其还包括在所述第一金属层的上面形成导电的腐蚀阻挡层。
11.权利要求10所述的方法，其中所述第一金属是钛。
12.权利要求11所述的方法，其中所述导电腐蚀阻挡层是氮化钛。
13.权利要求9所述的方法，其中所述第二金属是铝。
14.权利要求9所述的方法，其中所述电容器电介质是二氧化硅。
15.一种集成电路电容器，其包括：
a)底板，其包括一层钛和一层氮化钛；
b)金属的顶板；
c)夹在所述底板和顶板间的一层介电材料。
16.权利要求15所述的电容器，其中所述介电材料层与所述氮化钛层接触。
17.一种集成电路，其包括：
a)导电衬底；
b)形成在所述导电衬底上的场介电层；
c)形成在所述场介电层上的导电多晶硅层；
d)形成在所述多晶硅层上并与其导电接触的平行分开的第一和第二导电材料层，所述分开的第一和第二层每个都包括一层钛和一层氮化钛；
e)位于所述第一导电材料层上与所述氮化钛层接触的电容器电介质层；
f)位于所述电容器电介质层上的第三金属层；
g)位于所述第二导电材料层上的第四金属层。
18.权利要求17所述的集成电路，其中所述第三和第四金属层包括铝。
19.权利要求17所述的集成电路，其中所述第一和第二导电材料层被层间电介质分开。
20.权利要求17所述的集成电路，其中所述电容器电介质包括二氧化硅。
CN95120211A 1994-12-09 1995-12-04 电容器制造方法 Pending CN1130801A (zh)

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US08/353,015 US5576240A (en) 1994-12-09 1994-12-09 Method for making a metal to metal capacitor

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US5654581A (en) 1997-08-05
US5825073A (en) 1998-10-20
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KR100273609B1 (ko) 2000-12-15

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