CN113015823B - 用于对铜和铜合金选择性地进行蚀刻的蚀刻液和使用其的半导体基板的制造方法 - Google Patents

用于对铜和铜合金选择性地进行蚀刻的蚀刻液和使用其的半导体基板的制造方法 Download PDF

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CN113015823B
CN113015823B CN201980074655.4A CN201980074655A CN113015823B CN 113015823 B CN113015823 B CN 113015823B CN 201980074655 A CN201980074655 A CN 201980074655A CN 113015823 B CN113015823 B CN 113015823B
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copper
etching solution
etching
metal layer
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CN113015823A (zh
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深泽隼
藤井智子
松永裕嗣
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Mitsubishi Gas Chemical Co Inc
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Mitsubishi Gas Chemical Co Inc
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    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract

本发明涉及抑制镍、锡、金和它们的合金的溶解、且能对铜和铜合金选择性地进行蚀刻的蚀刻液。本发明的蚀刻液的特征在于,其包含:相对于蚀刻液的总质量为5~10.5质量%的(A)过氧化氢;相对于蚀刻液的总质量为0.3~6质量%的(B)硝酸;(C)任选具有取代基的、选自由三唑和四唑组成的组中的1种以上的含氮五元环化合物,所述取代基选自由碳数1~6的烷基、氨基、以及具有选自由碳数1~6的烷基和苯基组成的组中的取代基的取代氨基组成的组中的1种以上;以及(D)(d1)选自由碱金属氢氧化物、氨、胺和铵盐组成的组中的1种以上的pH调节剂、(d2)膦酸化合物或(d3)它们的组合。

Description

用于对铜和铜合金选择性地进行蚀刻的蚀刻液和使用其的半 导体基板的制造方法
技术领域
本发明涉及对选自由铜和铜合金组成的组中的1种以上选择性地进行蚀刻的蚀刻液和使用其的半导体基板的制造方法。
背景技术
以下一代的DRAM存储器、NAND存储器为代表的TSV(Through Silicon Via)等使用了凸起的半导体基板的布线形成中,要求抑制镍、镍合金、锡、锡合金、金和金合金的溶解、且对铜和铜合金选择性地进行蚀刻的技术。
已知有抑制镍和镍合金的溶解、对铜和铜合金选择性地进行蚀刻的技术(例如专利文献1~3)。
然而,以往,在除镍和镍合金之外还包含锡、金和它们的合金作为布线材料的情况下,尚未对边抑制这些金属的溶解边对铜和铜合金选择性地进行蚀刻的技术进行研究。
例如,专利文献1中公开了一种以规定的浓度比包含过氧化氢和硝酸的蚀刻液,然而在包含锡、金作为布线材料的情况下,该蚀刻液无法防止镍的溶解。
现有技术文献
专利文献
专利文献1:日本特开2004-43895号公报
专利文献2:国际公开第2011/074589号
专利文献3:国际公开第2017/188108号
发明内容
发明要解决的问题
在这种情况下,包含选自由镍和镍合金组成的组中的1种以上、和选自由锡、锡合金、金和金合金组成的组中的1种以上作为布线材料的情况下,要求提供:抑制这些金属的溶解、且可以对铜和铜合金选择性地进行蚀刻、能适合用于使用了凸起的半导体基板的布线形成的蚀刻液。
用于解决问题的方案
本发明人等对上述课题进行了深入研究,结果发现:以下所示的特定组成的蚀刻液可以解决上述课题。
即,本发明提供以下所示的蚀刻液和半导体基板的制造方法等。
[1]一种蚀刻液,其为:在包含选自由铜和铜合金组成的组中的1种以上、选自由镍和镍合金组成的组中的1种以上、和选自由锡、锡合金、金和金合金组成的组中的1种以上的半导体基板中,用于对选自由铜和铜合金组成的组中的1种以上选择性地进行蚀刻的蚀刻液,所述蚀刻液包含:
相对于蚀刻液的总质量为5~10.5质量%的(A)过氧化氢;
相对于蚀刻液的总质量为0.3~6质量%的(B)硝酸;
(C)任选具有取代基的、选自由三唑和四唑组成的组中的1种以上的含氮五元环化合物,所述取代基选自由碳数1~6的烷基、氨基、以及具有选自由碳数1~6的烷基和苯基组成的组中的1种以上取代基的取代氨基组成的组中的1种以上;以及
(D)(d1)选自由碱金属氢氧化物、氨、胺和铵盐组成的组中的1种以上的pH调节剂、(d2)膦酸化合物或(d3)它们的组合。
[2]根据[1]所述的蚀刻液,其中,成分(C)为选自由5-甲基四唑、5-氨基四唑和1,2,4-三唑组成的组中的1种以上的含氮五元环化合物。
[3]根据[1]或[2]所述的蚀刻液,其中,成分(C)的浓度相对于蚀刻液的总质量为0.005~2.0质量%。
[4]根据[1]~[3]中任一项所述的蚀刻液,其中,蚀刻液的pH为0.5~3.0。
[5]根据[1]~[3]中任一项所述的蚀刻液,其中,蚀刻液包含(d2)膦酸化合物。
[6]根据[1]~[5]中任一项所述的蚀刻液,其中,成分(d2)为选自由1-羟基乙叉基-1,1-二膦酸、二亚乙基三胺五(亚甲基膦酸)、和它们的盐组成的组中的1种以上的膦酸化合物。
[7]根据[1]~[6]中任一项所述的蚀刻液,其中,成分(d2)的浓度相对于蚀刻液的总质量为0.005~1.0质量%。
[8]一种半导体基板的制造方法,其包括如下工序:
准备半导体基材的工序,所述半导体基材在表面具有:包含选自由铜和铜合金组成的组中的1种以上的铜晶种层;
形成具有使前述铜晶种层的一部分露出的开口图案的抗蚀图案的工序;
在前述抗蚀图案的前述开口图案的开口部露出的前述铜晶种层的表面形成依次配置有金属层A和金属层B的工序,前述金属层A包含选自由镍和镍合金组成的组中的1种以上,前述金属层B包含选自由锡、锡合金、金和金合金组成的组中的1种以上;
将前述抗蚀图案去除的工序;和
使去除前述抗蚀图案而产生的、未形成前述金属层A和前述金属层B的前述铜晶种层的露出部与[1]~[7]中任一项所述的蚀刻液接触,对前述铜晶种层的露出部进行蚀刻的工序。
[9]根据[8]所述的半导体基板的制造方法,其中,在前述半导体基材上形成含有金属层A和金属层B的凸起,前述金属层A包含选自由镍和镍合金组成的组中的1种以上,前述金属层B包含选自由锡、锡合金、金和金合金组成的组中的1种以上。
发明的效果
根据本发明,可以提供:用于对铜和铜合金选择性地进行蚀刻的蚀刻液。另外,根据本发明,可以提供:使用该蚀刻液的半导体基板的制造方法。
根据本发明的优选方式,通过使用该蚀刻液,可以抑制镍、镍合金、锡、锡合金、金和金合金的溶解、且对铜和铜合金选择性地进行蚀刻。另外,根据本发明的优选方式,该蚀刻液可以适合用于使用了凸起的半导体基板的布线形成。
附图说明
图1(a)~(c)为示意性示出基材准备工序的一例的工序图。
图2为示意性示出抗蚀图案形成工序的一例的工序图。
图3为示意性示出镀铜层形成工序的一例的工序图。
图4为示意性示出金属层形成工序的一例的工序图。
图5为示意性示出抗蚀图案去除工序的一例的工序图。
图6为示意性示出蚀刻工序的一例的工序图。
图7为示意性示出势垒金属层去除工序的一例的工序图。
具体实施方式
以下,对本发明的蚀刻液和半导体基板的制造方法等具体地进行说明,但本发明不限定于此,可以在不脱离其主旨的范围内进行各种变形。
1.蚀刻液
本发明的蚀刻液的特征在于,其为:在包含选自由铜和铜合金组成的组中的1种以上、选自由镍和镍合金组成的组中的1种以上、和选自由锡、锡合金、金和金合金组成的组中的1种以上的半导体基板中,用于对选自由铜和铜合金组成的组中的1种以上选择性地进行蚀刻的蚀刻液,所述蚀刻液包含:
相对于蚀刻液的总质量为5~10.5质量%的(A)过氧化氢;
相对于蚀刻液的总质量为0.3~6质量%的(B)硝酸;
(C)任选具有取代基的、选自由三唑和四唑组成的组中的1种以上的含氮五元环化合物,所述取代基选自由碳数1~6的烷基、氨基、以及具有选自由碳数1~6的烷基和苯基组成的组中的1种以上取代基的取代氨基组成的组中的1种以上;以及
(D)(d1)选自由碱金属氢氧化物、氨、胺和铵盐组成的组中的1种以上的pH调节剂、(d2)膦酸化合物或(d3)它们的组合。
根据本发明的优选方式,本发明的蚀刻液如上述以特定的比率含有特定的成分,从而在包含选自由镍和镍合金组成的组中的1种以上、和选自由锡、锡合金、金和金合金组成的组中的1种以上作为布线材料的情况下,可以边抑制这些金属的溶解边对铜和铜合金选择性地进行蚀刻。需要说明的是,对于本说明书中的“镍合金”,只要是在镍中加入了1种以上的金属元素或非金属元素且具有金属的性质的物质就没有特别限定。对于“锡合金”、“金合金”和“铜合金”也同样。
以下,对本发明的蚀刻液中所含的各成分详细地进行说明。
[过氧化氢(A)]
本发明中过氧化氢(A)(以下,也称为成分(A))是作为铜的氧化剂发挥功能的成分。
过氧化氢(A)的等级没有特别限制,可以使用工业用和电子工业用等各种等级者。在获得性和操作性的方面,通常优选以过氧化氢水溶液的形式使用。
蚀刻液中的过氧化氢(A)的浓度相对于蚀刻液的总质量为5~10.5质量%的范围,优选6.0~10.0质量%的范围。过氧化氢(A)的浓度处于上述范围内,从而蚀刻速度变良好。另外,可以抑制布线材料的溶解。
[硝酸(B)]
本发明中硝酸(B)(以下,也称为成分(B))是作为被过氧化氢所氧化的铜和铜合金的蚀刻剂发挥作用的成分。
蚀刻液中的硝酸(B)的浓度为0.3~6质量%的范围、优选0.5~5.0质量%、更优选1.0~4.0质量%的范围。硝酸(B)的浓度处于上述范围内,从而蚀刻速度变良好。另外,可以抑制布线材料的溶解。
[含氮五元环化合物(C)]
本发明中含氮五元环化合物(C)(以下,也称为成分(C))吸附于铜表面,认为具有控制铜的蚀刻速度与降低镍、锡的腐蚀的功能。
含氮五元环化合物(C)为任选具有取代基的、选自由三唑和四唑组成的组中的1种以上,所述取代基选自由碳数1~6的烷基、氨基、以及具有选自由碳数1~6的烷基和苯基组成的组中的1种以上取代基的取代氨基组成的组中的1种以上。含氮五元环化合物(C)可以使用1种,也可以组合2种以上而使用。
作为含氮五元环化合物(C),优选可以举出下述式(1)、式(2)或式(3)所示的化合物:
Figure BDA0003062650050000061
[式(1)~式(3)中,R1、R2、R3、R4和R5各自独立地选自由(i)氢原子、(ii)碳数1~6的烷基、(iii)氨基、(iv)具有选自由碳数1~6的烷基和苯基组成的组中的1种以上取代基的取代氨基组成的组。]。
作为碳数1~6的烷基,可以举出直链或支链的烷基和环烷基。作为直链或支链的烷基,例如可以举出甲基、乙基、正丙基、异丙基、正丁基、异丁基、仲丁基、叔丁基、正戊基、正己基等。作为环烷基,可以举出碳数3~6的环烷基,例如可以举出环丙基、环戊基、环己基等。它们之中,优选甲基或乙基、特别优选甲基。
作为取代氨基,只要为具有选自由碳数1~6的烷基和苯基组成的组中的1种以上取代基的氨基就没有特别限制。关于碳数1~6的烷基,如上述中示例。
作为含氮五元环化合物(C)的优选具体例,可以举出5-甲基四唑、5-氨基四唑、1,2,4-三唑、1,2,3-三唑、和四唑。它们之中,特别优选选自由5-甲基四唑、5-氨基四唑和1,2,4-三唑组成的组中的1种以上。
蚀刻液中的含氮五元环化合物(C)的浓度相对于蚀刻液的总质量优选0.005~2.0质量%的范围、更优选0.01~1.0质量%、进一步优选0.05~0.5质量%的范围。含氮五元环化合物(C)的浓度处于上述范围内,从而蚀刻速度变良好。另外,可以抑制布线材料的溶解。
[成分(D)]
本发明中,作为成分(D),包含(d1)选自由碱金属氢氧化物、氨、胺和铵盐组成的组中的1种以上的pH调节剂、(d2)膦酸化合物、或(d3)它们的组合。通过包含成分(D),从而可以抑制布线材料的溶解。
[成分(d1)]
成分(d1)为选自由碱金属氢氧化物、氨、胺和铵盐组成的组中的1种以上的pH调节剂。通过包含成分(d1),从而可以将蚀刻液的pH调整为适当的范围。
作为本发明的蚀刻液的pH范围,没有特别限定,优选0.5~3.0、更优选0.6~3.0、进一步优选0.7~2.0、特别优选0.7~1.6、最优选0.7~1.3。其中,本发明的蚀刻液包含后述的成分(d2)的情况不受限于此,蚀刻液的pH范围即使为上述范围外,也可以有效地抑制布线材料的溶解。
作为碱金属氢氧化物,只要为碱金属的氢氧化物就没有特别限定,例如可以举出氢氧化钾、氢氧化钠、氢氧化锂、氢氧化铯等。
作为胺,只要为氨的氢原子被1~3个有机基团所取代的化合物就没有特别限定,例如可以举出单乙醇胺、二乙醇胺、三乙醇胺、二乙二醇胺、1-氨基-2-丙醇和N-羟乙基哌嗪等烷醇胺;乙胺、苄胺、二乙胺、正丁胺、3-甲氧基丙胺、叔丁胺、正己胺、环己胺、正辛胺、2-乙基己胺、邻二甲苯二胺、间二甲苯二胺、1-甲基丁胺、乙二胺、1,3-丙二胺、2-氨基苄胺、N-苄基乙二胺、二亚乙基三胺和三亚乙基四胺等不具有羟基的有机胺。
作为铵盐,只要为水溶性的季铵盐就没有特别限定。例如可以举出四甲基氢氧化铵、乙基三甲基氢氧化铵或四乙基氢氧化铵等碱性的季铵盐。
作为pH调节剂,例如可以优选使用氢氧化钾、氢氧化钠、氢氧化锂、氢氧化铯、三乙胺、氨、四甲基氢氧化铵、乙醇胺、1-氨基-2-丙醇等。pH调节剂可以使用1种,也可以组合2种以上而使用。
[成分(d2)]
成分(d2)为膦酸化合物。如前述,包含成分(d2)的情况下,即使不将蚀刻液的pH范围调整为规定范围的情况下,也可以得到所期望的效果。
作为膦酸化合物,可以举出1-羟基乙叉基-1,1-二膦酸(HEDP)、氨基三(亚甲基膦酸)(ATP)、乙二胺四(亚甲基膦酸)(EDTP)、顺式-环己二胺四(亚甲基膦酸)(cis-CDTP)、反式-环己二胺四(亚甲基膦酸)(反式-CDTP)、六亚甲基二胺四(亚甲基膦酸)(HDTP)、二亚乙基三胺五(亚甲基膦酸)(DTPP)、三亚乙基四胺六(亚甲基膦酸)(TTHP)、三(2-氨基乙基)胺六(亚甲基膦酸)(TAEHP)、四亚乙基五胺七(亚甲基膦酸)(TPHP)、五亚乙基六胺八(亚甲基膦酸)(PHOP)、和它们的盐。它们之中,优选选自由1-羟基乙叉基-1,1-二膦酸(HEDP)、二亚乙基三胺五(亚甲基膦酸)(DTPP)、和它们的盐组成的组中的1种以上的膦酸化合物,特别优选选自由1-羟基乙叉基-1,1-二膦酸(HEDP)和其盐组成的组中的1种以上的膦酸化合物。膦酸化合物可以使用1种,也可以组合2种以上而使用。
成分(d2)的浓度相对于蚀刻液的总质量优选0.005~1.0质量%的范围、更优选0.075~0.5质量%、特别优选0.01~0.1质量%的范围。
[成分(d3)]
本发明的蚀刻液可以包含成分(d1)和成分(d2)的组合。上述情况下,成分(d1)和成分(d2)的浓度只要分别落入上述所示的范围即可,另外,pH范围也可以为上述所示的范围外。
[其他成分]
本发明的蚀刻液除成分(A)、成分(B)、成分(C)和成分(D)之外,可以在不妨碍本发明的蚀刻液的效果的范围内还包含水和根据需要的其他蚀刻液中通常使用的各种添加剂中的1种以上。
作为水,优选通过蒸馏、离子交换处理、过滤器处理、各种吸附处理等而去除了金属离子、有机杂质、颗粒等的水,更优选纯水,特别优选超纯水。
另外,本发明的蚀刻液中,根据需要可以添加醇类、脲、苯基脲、有机羧酸类等公知的过氧化氢稳定剂、和蚀刻速度调节剂等。
需要说明的是,本发明的蚀刻液优选为溶解液,不含有研磨颗粒等固体颗粒。
本发明的蚀刻液中,成分(A)、成分(B)、成分(C)、成分(D)和水的总计含量相对于蚀刻液的总质量,优选70~100质量%的范围、更优选85~100质量%、进一步优选90~100质量%、特别优选95~100质量%。
[蚀刻液的制备]
通过将成分(A)、成分(B)、成分(C)、成分(D)和水、进一步根据需要的其他成分均匀地进行搅拌,从而可以制备本发明的蚀刻液。这些成分的搅拌方法没有特别限制,可以采用蚀刻液的制备中通常使用的搅拌方法。
[蚀刻液的用途]
本发明的蚀刻液可以用于铜和铜合金的蚀刻。特别是以下一代的DRAM存储器、NAND存储器为代表的TSV(Through Silicon Via)等使用了凸起的半导体基板的布线形成中,在包含选自由镍和镍合金组成的组中的1种以上、和选自由锡、锡合金、金和金合金组成的组中的1种以上作为布线材料的情况下,可以适合作为用于抑制这些金属的溶解、且对选自铜和铜合金中的至少1种选择性地进行蚀刻的蚀刻液而使用。
对本发明的蚀刻液的使用温度没有特别限制,优选10~50℃的温度、更优选20~45℃、进一步优选25~40℃。蚀刻液的温度如果为10℃以上,则蚀刻速度变良好,因此,可以得到优异的生产效率。另一方面,蚀刻液的温度如果为50℃以下,则可以抑制液体组成变化,保持蚀刻条件为恒定。通过升高蚀刻液的温度,从而蚀刻速度上升,但也可在考虑较小地抑制蚀刻液的组成变化(过氧化氢的分解)等的基础上,适宜确定最佳的处理温度。
另外,对蚀刻处理时间没有特别限制,优选20~240秒、更优选30~120秒。处理时间可以根据蚀刻对象物的表面的状态、蚀刻液的浓度、温度和处理方法等各种条件而适宜选择。
使蚀刻对象物与蚀刻液接触的方法没有特别限制。例如可以采用通过蚀刻液的滴加(单张旋涂处理)或喷涂等形式与蚀刻对象物接触的方法、或使蚀刻对象物浸渍于蚀刻液的方法等湿式法(wet)的蚀刻方法。本发明中,可以采用任意方法。
2.半导体基板的制造方法
本发明的半导体基板的制造方法的特征在于,其包括如下工序:
准备半导体基材的工序,所述半导体基材在表面具有:包含选自由铜和铜合金组成的组中的1种以上的铜晶种层;
形成具有使前述铜晶种层的一部分露出的开口图案的抗蚀图案的工序;
在前述抗蚀图案的前述开口图案的开口部露出的前述铜晶种层的表面形成依次配置有金属层A和金属层B的工序,前述金属层A包含选自由镍和镍合金组成的组中的1种以上,前述金属层B包含选自由锡、锡合金、金和金合金组成的组中的1种以上;
将前述抗蚀图案去除的工序;和
使去除前述抗蚀图案而产生的、未形成前述金属层A和前述金属层B的前述铜晶种层的露出部与本发明的蚀刻液接触,对前述铜晶种层的露出部进行蚀刻的工序。
以下,边利用附图边对本发明的半导体基板的制造方法的一例进行说明。
[基材准备工序]
基材准备工序中,准备半导体基材,所述半导体基材在表面具有:包含选自由铜和铜合金组成的组中的1种以上的铜晶种层。
图1(a)~(c)为示意性示出基材准备工序的一例的工序图。
首先,如图1(a)所示,准备具有平面部11的硅基板10。
接着,如图1(b)所示,在硅基板10的平面部11上形成由底面12a和侧面12b构成的凹陷12。形成凹陷12的方法没有特别限制,可以采用激光加工法、钻头加工法等通常的方法。
接着,如图1(c)所示,在硅基板10的平面部11、凹陷12的底面12a和侧面12b的表面形成铜晶种层40。在形成铜晶种层40之前,任意地形成硅氧化物层20、其上形成钛层等势垒金属层30,可以进一步依次配置铜晶种层40,也可以加入其他层。由此,在凹陷12上形成有铜晶种层40、或依次形成有硅氧化物层20、势垒金属层30和铜晶种层40,形成以铜晶种层40为底面1a和侧面1b的凹部1。如此,可以准备在表面具有铜晶种层40、且形成有凹部1的半导体基材100。硅氧化物层、铜晶种层和势垒金属层的形成方法没有特别限定,可以利用公知的方法。例如,关于铜晶种层和势垒金属层,优选使用溅射法。
[抗蚀图案形成工序]
接着,形成具有使前述工序中得到的铜晶种层的一部分露出的开口图案的抗蚀图案。
图2为示意性示出抗蚀图案形成工序的一例的工序图。
如图2所示,以从凹部1的边缘向外侧的铜晶种层40的表面的一部分露出的方式,在铜晶种层40的表面形成抗蚀剂树脂层50,形成抗蚀图案。抗蚀图案的形成方法没有特别限定,可以利用公知的方法。例如,通过使用液体抗蚀剂或干膜抗蚀剂将图案曝光,从而可以形成抗蚀图案。
[金属层形成工序]
接着,在前述工序中形成的抗蚀图案的开口图案的开口部露出的铜晶种层的表面形成金属层A和金属层B并使其依次配置,前述金属层A包含选自由镍和镍合金组成的组中的1种以上,前述金属层B包含选自由锡、锡合金、金和金合金组成的组中的1种以上。
需要说明的是,图3为示意性示出镀铜层形成工序的一例的工序图。在形成金属层A和B之前,如图3所示,可以任意地以填埋凹部1、且覆盖铜晶种层40的露出部的方式进行镀铜,形成镀铜层60。
图4为示意性示出金属层形成工序的一例的工序图。如图4所示,在镀铜层60的表面形成金属层A70和金属层B80并使其依次配置。
本发明的另一实施方式中,镀铜层和金属层A的配置顺序可以颠倒,也可以如下:以填埋凹部1、且覆盖铜晶种层40的露出部的方式形成金属层A60,在金属层A60的表面形成镀铜层70和金属层B80并使其依次配置。
另外,可以不形成镀铜层,不形成镀铜层的情况下,在铜晶种层40的露出部形成金属层A70和金属层B80并使其依次配置。需要说明的是,金属层A和金属层B可以分别为一层也可以为二层以上。另外,在金属层A和金属层B之间或其前后也可以具有其他层。这些镀铜层、金属层A、金属层B等的形成方法没有特别限定,可以利用公知的方法。例如,优选使用电镀。
[抗蚀图案去除工序]
图5为示意性示出抗蚀图案去除工序的一例的工序图。如图5所示,将抗蚀剂树脂层50去除。抗蚀剂树脂层的去除方法没有特别限定,可以利用公知的方法。
[蚀刻工序]
图6为示意性示出蚀刻工序的一例的工序图。如图6所示,使去除抗蚀图案而产生的、未形成金属层A70和金属层B80的铜晶种层40的露出部与本发明的蚀刻液接触,对前述铜晶种层40的露出部进行蚀刻。由此,势垒金属层30露出,形成具有铜晶种层40、镀铜层60、金属层A70和金属层B80的凸起2。需要说明的是,凸起2可以由铜晶种层40、金属层A60、镀铜层70和金属层B80构成,而且也可以不具有镀铜层。由此,可以制造半导体基板200。
蚀刻液的温度没有特别限制,优选10~50℃的温度、更优选20~45℃、进一步优选25~40℃。蚀刻液的温度如果为10℃以上,则蚀刻速度变良好,因此,可以得到优异的生产效率。另一方面,蚀刻液的温度如果为50℃以下,则可以抑制液体组成变化,保持蚀刻条件为恒定。通过升高蚀刻液的温度,从而蚀刻速度上升,但也可在考虑较小地抑制蚀刻液的组成变化(过氧化氢的分解)等的基础上,适宜确定最佳的处理温度。
对蚀刻处理时间没有特别限制,优选20~240秒、更优选30~120秒。处理时间可以根据蚀刻对象物的表面的状态、蚀刻液的浓度、温度和处理方法等各种条件而适宜选择。
[势垒金属层去除工序]
蚀刻工序之后,根据需要将势垒金属层去除。
图7为示意性示出势垒金属层去除工序的一例的工序图。如图7所示,将势垒金属层30的露出部去除,从而可以形成具有势垒金属层30、铜晶种层40、镀铜层60、金属层A70和金属层B80的凸起3。需要说明的是,凸起3可以由势垒金属层30、铜晶种层40、金属层A60、镀铜层70和金属层B80构成,而且也可以不具有镀铜层。由此,可以制造半导体基板200。势垒金属层的去除方法没有特别限定,可以利用公知的方法。
如上述,可以制造形成有凸起的半导体基板,所述凸起含有:包含选自由镍和镍合金组成的组中的1种以上的金属层A、和包含选自由锡、锡合金、金和金合金组成的组中的1种以上的金属层B。根据本发明的优选方式,如上述制造的半导体基板适合用于以下一代的DRAM存储器、NAND存储器为代表的TSV(Through Silicon Via)等中。
实施例
以下,根据实施例对本发明具体地进行说明,但只要发挥本发明的效果就可以适宜变更实施方式。
[实施例1~15]
在体积1L的玻璃烧杯中,以表1中记载的组成投入过氧化氢(A)、硝酸(B)、含氮五元环化合物(C)、pH调节剂(d1)、膦酸化合物(d2)或它们的组合(d3)和纯水,进行搅拌形成均匀的状态,制备蚀刻液。需要说明的是,pH调节剂的量以全部混合时成为目标pH的方式进行添加。
[比较例1~9]
使用表2中记载的组成,除此之外,与上述实施例同样地制备蚀刻液。
[评价用基板的制作]
使用具有图5的结构的基板作为评价用基板。需要说明的是,作为势垒金属层30,使用钛层。作为金属层A60,使用镍层。作为层70,使用镀铜层。作为金属层B80,对于实施例14使用金层,对于实施例15使用锡-银合金层,对于除实施例14和15以外的实施例1~13以及比较例1~9使用锡层。
(1)蚀刻液的pH值的测定
使用株式会社堀场制作所的pH/ION计“堀场制作所制pH计‘D-53’”,将电极浸渍于搅拌的蚀刻液中,在25℃下测定实施例和比较例中制备的蚀刻液的pH值。使用pH4和pH7的标准液进行pH测定装置的pH值的调节。
(2)铜晶种层的蚀刻处理时间和腐蚀的评价
对于评价用基板,使用实施例和比较例中制备的蚀刻液进行蚀刻处理。
铜晶种层的蚀刻时间(恰当蚀刻时间)进行如下评价:使评价用基板在30℃或40℃下浸渍于搅拌速度保持为200rpm的蚀刻液中,厚度600μm的铜晶种层溶解,测量可见钛层的时间。
镍、锡、金和锡-银合金的腐蚀评价如下:使对象物浸渍恰当蚀刻时间的2倍的时间,之后,用纯水进行清洗后,干燥,利用后述的扫描型电子显微镜观察而进行评价。
按照以下的基准评价恰当蚀刻时间(秒)。评价基准如以下所述。E和G为合格。
E:30~120秒
G:20~30秒或121~240秒
B:低于19秒或超过241秒
(3)扫描型电子显微镜(SEM:Scanning Electron Microscope)图像的观察
使用Hitachi High-Technologies Corporation制聚焦离子束加工装置“FB2200”,将前述(2)中所述的蚀刻处理后的评价用基板中的凸起或基板切断,用HitachiHigh-Technologies Corporation制的扫描型电子显微镜“S3400N”对得到的截面(凸起截面)以观察倍率3000倍(加速电压5.0kV、发射电流30μA)进行观察,确认对镍、锡、金和锡-银合金的腐蚀的有无。评价基准如以下所述。E为合格。
E:通过SEM无法确认腐蚀
(处理前后的凸起直径的减少:低于0.5μm、无金属表面异常)
B:通过SEM可以确认腐蚀
NE:铜晶种层未被蚀刻,因此,无法测定
WE:由于凸起下的铜晶种层的消失而无法确认凸起的有无,因此,无法测定
需要说明的是,表中,“-”表示未实施腐蚀试验。
分别将实施例的各种评价结果示于表1、将比较例的各种评价结果示于表2。需要说明的是,表中,“余量”是指,将蚀刻液设为100质量%的情况下所需的纯水的含量。
[表1]
Figure BDA0003062650050000161
[表2]
Figure BDA0003062650050000171
如表1所示,可以确认:实施例1~15的蚀刻液中,均可以抑制镍、锡、金和锡-银合金的腐蚀、且对铜选择性地进行蚀刻。
另一方面,如表2所示,成分(A)的组成比不满足本发明中限定的范围的情况下,产生了镍和锡中的任意者的腐蚀(比较例1、2)。另外,成分(B)的组成比不满足本发明中限定的范围的情况下,或不含有成分(B)的情况下,铜晶种层的蚀刻不进行(比较例3、4和5)。
使用硫酸代替成分(B)的硝酸的情况下,可知虽然铜晶种层的蚀刻进行,但镍发生腐蚀(比较例6)。另外,不含有成分(D)的情况下,可知锡发生腐蚀(比较例7)。不使用成分(C)的含氮五元环化合物的情况下,产生了镍和锡的腐蚀(比较例8),或铜晶种层的蚀刻不进行,另外,凸起的一部分或全部倒塌(比较例9)。
产业上的可利用性
本发明的蚀刻液可以适合用于使用了凸起的半导体基板的布线形成。根据本发明的优选方式,可以抑制包含镍、镍合金、锡、锡合金、金和金合金的布线材料的溶解、且对铜和铜合金选择性地进行蚀刻。
附图标记说明
1 凹部
1a 凹部的底面
1b 凹部的侧面
2、3 凸起
10 硅基板
11 平面部
12 凹陷
12a 凹陷的底面
12b 凹陷的侧面
20 硅氧化物层
30 势垒金属层
40 铜晶种层
50 抗蚀剂树脂层
60 镀铜层或金属层A
70 金属层A或镀铜层
80 金属层B
100 半导体基材
200 半导体基板

Claims (7)

1.一种蚀刻液,其为:在包含选自由铜和铜合金组成的组中的1种以上、选自由镍和镍合金组成的组中的1种以上、和选自由锡、锡合金、金和金合金组成的组中的1种以上的半导体基板中,用于对选自由铜和铜合金组成的组中的1种以上选择性地进行蚀刻的蚀刻液,所述蚀刻液包含:
相对于蚀刻液的总质量为5~10.5质量%的(A)过氧化氢;
相对于蚀刻液的总质量为0.3~6质量%的(B)硝酸;
(C)任选具有取代基的、选自由三唑和四唑组成的组中的1种以上的含氮五元环化合物,所述取代基选自由碳数1~6的烷基、氨基、以及具有选自由碳数1~6的烷基和苯基组成的组中的1种以上取代基的取代氨基组成的组中的1种以上;以及
(D)(d1)选自由碱金属氢氧化物、氨、胺和铵盐组成的组中的1种以上的pH调节剂、(d2)膦酸化合物或(d3)它们的组合,
所述蚀刻液的pH为0.7~1.3。
2.根据权利要求1所述的蚀刻液,其中,成分(C)为选自由5-甲基四唑、5-氨基四唑和1,2,4-三唑组成的组中的1种以上的含氮五元环化合物。
3.根据权利要求1或2所述的蚀刻液,其中,成分(C)的浓度相对于蚀刻液的总质量为0.005~2.0质量%。
4.根据权利要求1所述的蚀刻液,其中,成分(d2)为选自由1-羟基乙叉基-1,1-二膦酸、二亚乙基三胺五(亚甲基膦酸)、和它们的盐组成的组中的1种以上的膦酸化合物。
5.根据权利要求1所述的蚀刻液,其中,成分(d2)的浓度相对于蚀刻液的总质量为0.005~1.0质量%。
6.一种半导体基板的制造方法,其包括如下工序:
准备半导体基材的工序,所述半导体基材在表面具有:包含选自由铜和铜合金组成的组中的1种以上的铜晶种层;
形成具有使所述铜晶种层的一部分露出的开口图案的抗蚀图案的工序;
在所述抗蚀图案的所述开口图案的开口部露出的所述铜晶种层的表面形成依次配置有金属层A和金属层B的工序,所述金属层A包含选自由镍和镍合金组成的组中的1种以上,所述金属层B包含选自由锡、锡合金、金和金合金组成的组中的1种以上;
将所述抗蚀图案去除的工序;和
使去除所述抗蚀图案而产生的、未形成所述金属层A和所述金属层B的所述铜晶种层的露出部与权利要求1~5中任一项所述的蚀刻液接触,对所述铜晶种层的露出部进行蚀刻的工序。
7.根据权利要求6所述的半导体基板的制造方法,其中,在所述半导体基材上形成含有金属层A和金属层B的凸起,所述金属层A包含选自由镍和镍合金组成的组中的1种以上,所述金属层B包含选自由锡、锡合金、金和金合金组成的组中的1种以上。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102762770A (zh) * 2010-02-15 2012-10-31 三菱瓦斯化学株式会社 包含铜层及钼层的多层薄膜用蚀刻液
CN102834547A (zh) * 2010-01-28 2012-12-19 三菱瓦斯化学株式会社 铜/钛系多层薄膜用蚀刻液
JP2014101561A (ja) * 2012-11-21 2014-06-05 Sanyo Chem Ind Ltd 銅または銅合金用エッチング液
WO2015075765A1 (ja) * 2013-11-25 2015-05-28 パナソニックIpマネジメント株式会社 多層膜用エッチング液とエッチング濃縮液およびエッチング方法
JP2016098386A (ja) * 2014-11-18 2016-05-30 関東化學株式会社 銅、モリブデン金属積層膜エッチング液組成物、該組成物を用いたエッチング方法および該組成物の寿命を延ばす方法
JP2016111342A (ja) * 2014-11-27 2016-06-20 三菱瓦斯化学株式会社 液体組成物およびこれを用いたエッチング方法
CN108570678A (zh) * 2018-04-13 2018-09-25 深圳达诚清洗剂有限公司 一种应用于铜钼膜层的金属蚀刻液

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004043895A (ja) 2002-07-12 2004-02-12 Mitsubishi Chemicals Corp 銅エッチング液
CN102687251B (zh) 2009-12-15 2016-02-17 三菱瓦斯化学株式会社 蚀刻液及使用其的半导体装置的制造方法
JP6101421B2 (ja) 2010-08-16 2017-03-22 インテグリス・インコーポレーテッド 銅または銅合金用エッチング液
US9365770B2 (en) 2011-07-26 2016-06-14 Mitsubishi Gas Chemical Company, Inc. Etching solution for copper/molybdenum-based multilayer thin film
JP5933950B2 (ja) * 2011-09-30 2016-06-15 アドバンスド テクノロジー マテリアルズ,インコーポレイテッド 銅または銅合金用エッチング液
KR102255577B1 (ko) * 2014-08-25 2021-05-25 엘지디스플레이 주식회사 식각액 조성물
JP6818017B2 (ja) 2016-04-27 2021-01-20 三洋化成工業株式会社 エッチング液及び電子基板の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102834547A (zh) * 2010-01-28 2012-12-19 三菱瓦斯化学株式会社 铜/钛系多层薄膜用蚀刻液
CN102762770A (zh) * 2010-02-15 2012-10-31 三菱瓦斯化学株式会社 包含铜层及钼层的多层薄膜用蚀刻液
JP2014101561A (ja) * 2012-11-21 2014-06-05 Sanyo Chem Ind Ltd 銅または銅合金用エッチング液
WO2015075765A1 (ja) * 2013-11-25 2015-05-28 パナソニックIpマネジメント株式会社 多層膜用エッチング液とエッチング濃縮液およびエッチング方法
JP2016098386A (ja) * 2014-11-18 2016-05-30 関東化學株式会社 銅、モリブデン金属積層膜エッチング液組成物、該組成物を用いたエッチング方法および該組成物の寿命を延ばす方法
JP2016111342A (ja) * 2014-11-27 2016-06-20 三菱瓦斯化学株式会社 液体組成物およびこれを用いたエッチング方法
CN108570678A (zh) * 2018-04-13 2018-09-25 深圳达诚清洗剂有限公司 一种应用于铜钼膜层的金属蚀刻液

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