CN112820336A - 存储器器件及提供写入电压的方法 - Google Patents

存储器器件及提供写入电压的方法 Download PDF

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Publication number
CN112820336A
CN112820336A CN202011265898.7A CN202011265898A CN112820336A CN 112820336 A CN112820336 A CN 112820336A CN 202011265898 A CN202011265898 A CN 202011265898A CN 112820336 A CN112820336 A CN 112820336A
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China
Prior art keywords
voltage
circuit
memory device
instantaneous
write
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Pending
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CN202011265898.7A
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English (en)
Chinese (zh)
Inventor
赖建安
邹宗成
池育德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112820336A publication Critical patent/CN112820336A/zh
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0023Address circuits or decoders
    • G11C13/0026Bit-line or column circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/003Cell access
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0033Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0038Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087Data input latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14Dummy cell management; Sense reference voltage generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • G11C2013/0071Write using write potential applied to access device gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/79Array wherein the access device being a transistor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/82Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
CN202011265898.7A 2019-11-15 2020-11-13 存储器器件及提供写入电压的方法 Pending CN112820336A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962935830P 2019-11-15 2019-11-15
US62/935,830 2019-11-15
US17/061,600 2020-10-02
US17/061,600 US11393512B2 (en) 2019-11-15 2020-10-02 Memory device

Publications (1)

Publication Number Publication Date
CN112820336A true CN112820336A (zh) 2021-05-18

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Country Status (5)

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US (3) US11393512B2 (ko)
KR (2) KR20210060336A (ko)
CN (1) CN112820336A (ko)
DE (1) DE102020126502A1 (ko)
TW (1) TWI754450B (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10950658B2 (en) * 2018-09-21 2021-03-16 Taiwan Semiconductor Manufacturing Company Ltd. Circuit and method to enhance efficiency of memory
US11393512B2 (en) * 2019-11-15 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device
US11450373B2 (en) 2020-08-26 2022-09-20 Micron Technology, Inc. Memory system capable of compensating for kickback noise
KR20220039170A (ko) * 2020-09-22 2022-03-29 에스케이하이닉스 주식회사 전압 생성 회로, 전압 생성 회로를 포함하는 반도체 장치 및 전압 오차 보정 시스템
US20220344222A1 (en) * 2021-04-27 2022-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods of testing memory devices
US11854914B2 (en) * 2021-11-15 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods of testing memory devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103855760A (zh) * 2012-11-28 2014-06-11 瑞萨电子株式会社 半导体集成电路及其操作方法
CN109545258A (zh) * 2017-09-21 2019-03-29 三星电子株式会社 包括参考单元的电阻式存储器装置及其操作方法
CN110277122A (zh) * 2018-03-16 2019-09-24 台湾积体电路制造股份有限公司 存储器件及其感测放大器和读取方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3676904B2 (ja) 1997-04-11 2005-07-27 株式会社ルネサステクノロジ 半導体集積回路
JP4124692B2 (ja) * 2003-04-25 2008-07-23 シャープ株式会社 不揮発性半導体記憶装置
US7057958B2 (en) 2003-09-30 2006-06-06 Sandisk Corporation Method and system for temperature compensation for memory cells with temperature-dependent behavior
US7586795B2 (en) * 2006-03-20 2009-09-08 Cypress Semiconductor Corporation Variable reference voltage circuit for non-volatile memory
KR100929304B1 (ko) 2008-08-04 2009-11-27 주식회사 하이닉스반도체 온도 보상 상 변화 메모리 장치
KR101504340B1 (ko) * 2008-11-04 2015-03-20 삼성전자주식회사 온도 보상 기능을 가지는 불휘발성 메모리 장치 및 그것을 포함하는 메모리 시스템
JP2011211767A (ja) 2010-03-29 2011-10-20 Toshiba Corp 半導体集積回路装置
WO2012032775A1 (ja) 2010-09-07 2012-03-15 パナソニック株式会社 抵抗変化型不揮発性記憶装置の検査方法および抵抗変化型不揮発性記憶装置
US20120230081A1 (en) 2011-03-10 2012-09-13 International Business Machines Corporation Cell-state measurement in resistive memory
US9281029B2 (en) 2012-06-15 2016-03-08 Sandisk 3D Llc Non-volatile memory having 3D array architecture with bit line voltage control and methods thereof
US9202579B2 (en) 2013-03-14 2015-12-01 Sandisk Technologies Inc. Compensation for temperature dependence of bit line resistance
US9653156B2 (en) 2015-02-20 2017-05-16 Kabushiki Kaisha Toshiba Memory controller, nonvolatile semiconductor memory device and memory system
KR102469810B1 (ko) 2016-07-05 2022-11-24 에스케이하이닉스 주식회사 멀티-비트 데이터 저장을 위한 이피롬 장치 및 이피롬 장치의 리드 회로
KR102391503B1 (ko) 2017-09-11 2022-04-28 에스케이하이닉스 주식회사 임피던스 캘리브레이션 회로를 포함하는 메모리 시스템
KR102611634B1 (ko) 2018-01-22 2023-12-08 삼성전자주식회사 스토리지 장치, 스토리지 시스템 및 스토리지 장치의 동작 방법
US11393512B2 (en) * 2019-11-15 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103855760A (zh) * 2012-11-28 2014-06-11 瑞萨电子株式会社 半导体集成电路及其操作方法
CN109545258A (zh) * 2017-09-21 2019-03-29 三星电子株式会社 包括参考单元的电阻式存储器装置及其操作方法
CN110277122A (zh) * 2018-03-16 2019-09-24 台湾积体电路制造股份有限公司 存储器件及其感测放大器和读取方法

Also Published As

Publication number Publication date
KR20220159333A (ko) 2022-12-02
US20230402075A1 (en) 2023-12-14
TW202121423A (zh) 2021-06-01
US11393512B2 (en) 2022-07-19
TWI754450B (zh) 2022-02-01
KR20210060336A (ko) 2021-05-26
US11735238B2 (en) 2023-08-22
DE102020126502A1 (de) 2021-05-20
US20210151086A1 (en) 2021-05-20
US20220335996A1 (en) 2022-10-20
KR102580104B1 (ko) 2023-09-18

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