CN112435968A - 半导体封装 - Google Patents

半导体封装 Download PDF

Info

Publication number
CN112435968A
CN112435968A CN202010861476.XA CN202010861476A CN112435968A CN 112435968 A CN112435968 A CN 112435968A CN 202010861476 A CN202010861476 A CN 202010861476A CN 112435968 A CN112435968 A CN 112435968A
Authority
CN
China
Prior art keywords
semiconductor chip
package
semiconductor
conductive film
package substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010861476.XA
Other languages
English (en)
Other versions
CN112435968B (zh
Inventor
金泳龙
俞泰元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN112435968A publication Critical patent/CN112435968A/zh
Application granted granted Critical
Publication of CN112435968B publication Critical patent/CN112435968B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05172—Vanadium [V] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

可以提供一种半导体封装，其包括：封装基板；在封装基板的顶表面上的半导体芯片；在封装基板与半导体芯片之间的连接端子，该连接端子将封装基板连接到半导体芯片；在封装基板与半导体芯片之间的非导电膜(NCF)，NCF包围连接端子并将半导体芯片接合到封装基板；以及侧包封材料，覆盖半导体芯片的侧表面、接触封装基板并包括在半导体芯片的底表面与封装基板的顶表面之间的第一部分。NCF的至少一部分包括当从上方观察时从半导体芯片水平突出的第二部分，并且侧包封材料的一部分与半导体芯片的底表面接触。

Description

半导体封装
技术领域
本发明构思涉及半导体封装。更具体地，本发明构思涉及使用利用非导电膜(NCF)的热压工艺制造的半导体封装。
背景技术
随着技术、材料和制造工艺的发展，计算力和无线通信能力已迅速进展了几十年。因此，已经实现了高度集成的高性能晶体管，并且根据摩尔定律，集成程度约每18个月翻了一番。实现具有功率效率的更小且更轻的系统是半导体工业的持续目标。当现有工艺似乎达到经济和/或物理极限时，提出了三维(3D)集成封装作为有效的解决方案。
3D集成器件从1980年推出的互补金属氧化物半导体(CMOS)器件开始发展，并且已经通过往后约30年的不断研究和开发取得了进步。3D集成技术包括例如逻辑电路和存储电路的集成、传感器封装以及微机电系统(MEMS)和CMOS的异质集成。3D集成技术可以实现减小的形状参数(form factor)、更高的可靠性、更低的功耗和/或相对低的制造成本。
发明内容
本发明构思提供了具有提高的可靠性的半导体封装和/或制造该半导体封装的方法。
本发明构思不限于以上所述，并且将由以下描述被本领域技术人员清楚地理解。
根据本发明构思的一示例实施方式，一种半导体封装包括：封装基板；在封装基板的顶表面上的半导体芯片；在封装基板与半导体芯片之间的连接端子，连接端子将封装基板连接到半导体芯片；在封装基板与半导体芯片之间的非导电膜(NCF)，NCF围绕连接端子并将半导体芯片接合到封装基板；以及侧包封材料，覆盖封装基板的侧表面、接触封装基板并且包括在半导体芯片的底表面与封装基板的顶表面之间的第一部分。NCF的至少一部分包括当从上方观察时从半导体芯片水平突出的第二部分，并且侧包封材料的一部分与半导体芯片的底表面接触。
根据本发明构思的一示例实施方式，一种半导体封装包括：印刷电路板，包括基板基底、在基板基底的顶表面上的第一焊盘、覆盖基板基底的顶表面并暴露第一焊盘的至少一部分的第一阻焊层、在基板基底的底表面上的第二焊盘以及覆盖基板基底的底表面并暴露第二焊盘的至少一部分的第二阻焊层；在印刷电路板的顶表面上的半导体芯片，半导体芯片具有从顶视图看的四边形形状；在印刷电路板与半导体芯片之间的连接端子，连接端子包括接触第一焊盘的第一凸块下金属化(UBM)层和接触第一UBM层的第一焊料；外部连接端子，包括接触第二焊盘的第二UBM层和接触第二UBM层的第二焊料，外部连接端子大于连接端子；NCF，在印刷电路板与半导体芯片之间的空间的仅一部分中，NCF围绕连接端子并将印刷电路板接合到半导体芯片；以及侧包封材料，在半导体芯片的底表面与印刷电路板的顶表面之间，侧包封材料覆盖半导体芯片的侧表面并接触印刷电路板。
根据本发明构思的一示例实施方式，一种半导体封装包括：封装基板；在封装基板的顶表面上的半导体芯片；NCF，在封装基板与半导体芯片的底表面之间的空间的仅一部分中，NCF具有比半导体芯片大的水平面积；以及沿着半导体芯片的侧表面的侧包封材料，侧包封材料覆盖半导体芯片的侧表面并且接触封装基板的顶表面和半导体芯片的底表面。
附图说明
本发明构思的一些示例实施方式将由以下结合附图的详细描述被更清楚地理解，附图中：
图1A是根据一示例实施方式的半导体封装的示意性布局图；
图1B是沿图1A中的线IB-IB'截取的剖视图；
图1C是图1B中的区域IC的放大视图；
图1D是沿图1A中的线ID-ID'截取的剖视图；
图2是根据一示例实施方式的半导体封装的示意性布局图；
图3A是根据一示例实施方式的半导体封装的示意性布局图；
图3B是沿图3A中的线IIIB-IIIB'截取的剖视图；
图4是根据一示例实施方式的半导体封装的示意性布局图；
图5是根据一示例实施方式的制造半导体封装的方法的示意性流程图；
图6至图10是根据一示例实施方式的制造半导体封装的方法中的阶段的剖视图；
图11至图14是根据一些示例实施方式的半导体封装的示意性布局图；以及
图15是根据一示例实施方式的包括半导体封装的系统的示意性方块图。
具体实施方式
在下文中，将参照附图详细描述一些示例实施方式。在附图中，同样的附图标记表示同样的元件，并且将省略其多余的描述。在附图中，为了方便和清楚起见，可以夸大层的厚度和尺寸，因此，所述层的形状和大小可以不同于实际的形状和大小。
虽然在对示例实施方式的描述中使用了术语“相同”或“同一”，但是应理解，可以存在一些不精确。因此，当一个元件被称为与另一元件相同时，应理解，元件或值在期望的制造或操作公差范围(例如±10％)内与另一元件相同。
当术语“约”或“基本上”在本说明书中与数值结合使用时，意图是相关的数值包括围绕所述及的数值的制造或操作公差(例如±10％)。而且，当词语“大体上”和“基本上”与几何形状结合使用时，意图是不要求所述几何形状的准确性，而是对该形状的宽容度(latitude)在本公开的范围内。此外，无论数值被修改为“约”还是“基本上”，将理解，这些值应被解释为包括围绕所述及的数值的制造或操作公差(例如±10％)。
当在此使用时，术语“和/或”包括一个或更多个相关所列举项目的任何及所有组合。诸如“……中的至少一个”的表述当在一列元素之后时，修饰整列元素，而不修饰该列中的个别元素。因此，例如，“A、B和C”意思是A、B、C或其任何组合。
图1A是根据一示例实施方式的半导体封装10的示意性布局图。
图1B是沿图1A中的线IB-IB'截取的剖视图。
图1C是图1B中的区域IC的放大视图。
图1D是沿图1A中的线ID-ID'截取的剖视图。
参照图1A至图1D，半导体封装10可以包括封装基板100和半导体芯片200。半导体封装10还可以包括焊料212、非导电膜(NCF)220和侧包封材料230。根据一些示例实施方式，半导体封装10还可以包括热界面材料(TIM)层240和散热器250。
半导体芯片200可以堆叠在封装基板100上。半导体芯片200在封装基板100上堆叠的方向被定义为Z方向。垂直于Z方向且彼此交叉的两个方向被定义为X方向和Y方向。X方向基本上垂直于Y方向。垂直方向是指Z方向。水平方向是指X方向、Y方向以及相对于X方向和Y方向倾斜且垂直于Z方向的方向之一。垂直水平(vertical level)是指垂直方向上的高度，水平宽度是指水平方向上的宽度。
封装基板100可以包括例如印刷电路板。封装基板100可以包括基板基底101、以及分别在基板基底101的顶表面和底表面上的阻焊层121和123。封装基板100可以包括上焊盘122和下焊盘124，上焊盘122形成在基板基底101的顶表面上并且通过阻焊层121暴露，下焊盘124形成在基板基底101的底表面上并且通过阻焊层123暴露。
基板基底101可以包括选自酚醛树脂、环氧树脂和聚酰亚胺中的至少一种。例如，基板基底101可以包括选自以下中的至少一种材料：阻燃剂4(FR4)、四官能环氧树脂、聚苯醚、环氧树脂/聚亚苯基氧化物、双马来酰亚胺三嗪(BT)、Thermount、氰酸酯、聚酰亚胺和液晶聚合物。
电连接到上焊盘122和/或下焊盘124的内部布线110可以形成在基板基底101中。
上焊盘122和下焊盘124可以包括铜、镍、不锈钢或铍铜。上焊盘122和下焊盘124可以是通过图案化基板基底101的顶表面和底表面上的铜箔而形成的电路布线的部分，其中电路布线的所述部分通过阻焊层121和123暴露。
外部连接端子130可以附接到封装基板100的底表面。例如，外部连接端子130可以分别附接到下焊盘124。外部连接端子130可以包括例如焊料或凸块。外部连接端子130可以将半导体封装10电连接到外部装置。
根据一些示例实施方式，外部连接端子130可以包括在封装基板100的底表面上的凸块下金属化(under bump metallurgy)(UBM)层131和在UBM层131上的焊料132。外部连接端子130还可以包括在UBM层131与焊料132之间的导电柱(未示出)。导电柱可以包括例如铜。
外部连接器130可以是用于信号的输入/输出和电力传输的端子。例如，外部连接端子130可以是接收输入信号并发送输出信号的输入/输出(I/O)端子、指定接地电位的接地端子或供应工作电力的电源端子。
UBM层131可以包括例如铬(Cr)、钨(W)、钛(Ti)、铜(Cu)、镍(Ni)、铝(Al)、钯(Pd)、金(Au)或其组合。UBM层131可以包括单个金属层或多个金属层的堆叠结构。
例如，UBM层131可以包括依次堆叠在每个下焊盘124上的第一至第三金属层。第一金属层可以包括用于将焊料132稳定地附接到下焊盘124的粘合层。例如，第一金属层可以包括选自Ti、TiW、Cr和Al中的至少一种材料。第二金属层可以包括阻隔层，该阻隔层阻挡或防止金属材料扩散到封装基板100中。第二金属层可以包括选自Cu、Ni、Cr-Cu和镍钒(Ni-V)中的至少一种。第三金属层可以包括增强焊料132的润湿特性的润湿层或用于外部连接柱的籽晶层。第三金属层可以包括选自Ni、Cu和Al中的至少一种。
在一些示例实施方式中，焊料132可以具有球形形状或球状物形状。焊料132可以包括锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、Cu、银(Ag)、锌(Zn)、铅(Pb)和/或其合金。例如，焊料132可以包括Sn、Pb、Sn-Pb、Sn-Ag、Sn-Au、Sn-Cu、Sn-Bi、Sn-Zn、Sn-Ag-Cu、Sn-Ag-Bi、Sn-Ag-Zn、Sn-Cu-Bi、Sn-Cu-Zn和Sn-Bi-Zn中的至少一种。
在一些示例实施方式中，外部连接端子130的垂直高度和水平宽度可以为约50μm或更大。然而，外部连接端子130的垂直高度和水平宽度不限于此。
就水平面积而言，半导体芯片200可以具有相对大的尺寸。根据一些示例实施方式，半导体芯片200的水平面积可以为约100mm2或更大。根据一些示例实施方式，半导体芯片200的X方向长度可以为约10mm或更大，并且半导体芯片200的Y方向长度可以为约10mm或更大。根据一些示例实施方式，半导体芯片200的X方向长度可以为约20mm或更大，并且半导体芯片200的Y方向长度可以为约20mm或更大。
尽管图1A示出了在顶视图中具有正方形形状的半导体芯片200，但是根据本发明构思的示例实施方式不限于此。例如，从顶视图看，半导体芯片200可以具有矩形形状。在这种情况下，半导体芯片200在一个方向(例如X方向)上的宽度可以大于在另一方向(例如Y方向)上的宽度。
半导体芯片200可以包括例如逻辑芯片。逻辑芯片可以包括门阵列、单元基底阵列、嵌入式阵列、结构化专用集成电路(ASIC)、现场可编程门阵列(FPGA)、复杂可编程逻辑器件(CPLD)、中央处理单元(CPU)、微处理单元(MPU)、微控制器单元(MCU)、逻辑集成电路(IC)、应用处理器(AP)、显示驱动器IC(DDI)、射频(RF)芯片或互补金属氧化物半导体(CMOS)图像传感器。
然而，本发明构思的示例实施方式不限于此，半导体芯片200可以包括存储芯片。存储芯片可以包括例如易失性存储芯片(诸如动态随机存取存储器(DRAM)或静态RAM(SRAM))或非易失性存储芯片(诸如相变RAM(PRAM)、磁阻RAM(MRAM)、铁电RAM(FeRAM)或电阻RAM(ReRAM))。根据一些示例实施方式，半导体芯片200可以包括包含DRAM芯片的高带宽存储器(HBM)。
半导体芯片200可以通过连接端子210连接到封装基板100。连接端子210可以包括UBM层211和焊料212。连接端子210的UBM层211和焊料212中的每个可以包括与外部连接端子130的UBM层131和焊料132中的对应一个相同的材料。连接端子210的UBM层211和焊料212中的每个可以具有比外部连接端子130的UBM层131和焊料132中的对应一个更小的尺寸(例如，更小的水平宽度和垂直高度)。
NCF 220可以布置在半导体芯片200与封装基板100之间。NCF 220可以包括将半导体芯片200接合到封装基板100的粘合膜。NCF 220可以包括绝缘材料。半导体芯片200和封装基板100可以使用利用NCF的热压工艺彼此接合，这将在下面进行描述。
从顶视图看的NCF 220的形状可以不同于从顶视图看的半导体芯片200的形状。NCF 220的水平剖面面积可以不同于半导体芯片200的水平剖面面积。NCF 220的水平剖面面积可以大于半导体芯片200的水平剖面面积，但是示例实施方式不限于此。例如，NCF 220的水平剖面面积可以等于或小于半导体芯片200的水平剖面面积。
从顶视图看的NCF 220的形状可以包括弯曲的轮廓线。从顶视图看的NCF 220的形状可以是基本上圆形的。然而，本发明构思的示例实施方式不限于此，从顶视图看的NCF220的形状可以是椭圆的或不规则的。
NCF 220可以不设置在半导体芯片200的一部分之下。换言之，NCF 220可以不设置在半导体芯片200与封装基板100之间的至少一部分中。半导体芯片200与封装基板100之间的没有设置NCF 220的部分被定义为未填充区域UR。半导体芯片200与封装基板100之间的设置了NCF 220的部分被定义为填充区域FR。NCF 220的如从上方观察的从半导体芯片200向外突出的部分被定义为突出区域PR。未填充区域UR可以与半导体芯片200的拐角垂直地重叠。未填充区域UR的水平宽度(例如X方向宽度或Y方向宽度)可以为约5mm或更小，但不限于此。
尽管在图1A中示出了对应于半导体芯片200的拐角形成四个未填充区域UR，但是本发明构思的示例实施方式不限于此。在一些示例实施方式中，NCF 220可以设置在半导体芯片200的一些拐角之下，从而可以形成一个至三个未填充区域UR。
NCF 220可以包括填料。填料可以包括二氧化硅填料，但不限于此。根据一些示例实施方式，NCF 220可以具有约30wt％至约60wt％的填料含量。NCF 220可以是透明的。当NCF 220具有小于30wt％的填料含量时，NCF 220的杨氏模量太低，以至于NCF 220无法适当地支撑半导体芯片200和封装基板100。当NCF 220具有大于60wt％的填料含量时，NCF 220不是透明的，因此，切单(singulation)的可靠性可能降低。根据一些示例实施方式，NCF220的填料含量可以低于侧包封材料230的填料含量。
因为NCF 220具有合适的填料含量(例如约30wt％至约60wt％)，所以NCF 220的杨氏模量可以在合适的范围内。因此，NCF 220可以具有合适的硬度以在下面将描述的晶片级模制工艺以及后续工艺中用于保持。
侧包封材料230可以围绕或覆盖半导体芯片200的侧表面的至少一部分。侧包封材料230还可以覆盖半导体芯片200的底表面的一部分。侧包封材料230还可以在每个未填充区域UR中覆盖半导体芯片200的底表面。换言之，侧包封材料230还可以布置在半导体芯片200与封装基板100之间。
侧包封材料230可以在未填充区域UR与填充区域FR之间的边界上与NCF 220接触。根据一些示例实施方式，NCF 220和侧包封材料230可以一起完全填充半导体芯片200与封装基板100之间的空间(见图1B)。然而，本发明构思的示例实施方式不限于此。空隙可以部分地形成在半导体芯片200与封装基板100之间。
在图1B和图1C的垂直剖视图中，NCF 220可以包括凹形轮廓。侧包封材料230的在半导体芯片200与封装基板100之间的部分230p可以相对于NCF 220具有互补的形状。因此，部分230p可以包括凸形轮廓。然而，本发明构思的示例实施方式不限于此。在一些示例实施方式中，NCF 220和部分230p的垂直剖面轮廓可以是直线，或者NCF 220的垂直剖面轮廓可以是凸的，而部分230p的垂直剖面轮廓可以是凹的。
参照图1B和图1C，从封装基板100的顶表面到半导体芯片200的顶表面的垂直水平被定义为芯片高度CH，侧包封材料230的垂直高度被定义为填角高度(fillet height)FH。根据一些示例实施方式，填角高度FH可以等于或小于芯片高度CH。根据一些示例实施方式，填角高度FH可以是芯片高度CH的至少50％。当填角高度FH是芯片高度CH的至少50％时，可以以足够的机械强度将半导体芯片200支撑在封装基板100上。因此，侧包封材料230可以不覆盖半导体芯片200的顶表面。然而，本发明构思的示例实施方式不限于此。在一些示例实施方式中，侧包封材料230可以部分或全部覆盖半导体芯片200的顶表面。
侧包封材料230可以包括树脂。侧包封材料230可以包括与NCF 220不同的材料。侧包封材料230可以包括硅基材料、热固性材料、热塑性材料、紫外(UV)固化材料等。当侧包封材料230包括热固性材料时，侧包封材料230可以包括苯酚型、酸酐型或胺型硬化剂以及丙烯酸聚合物添加剂。
侧包封材料230还可以包括填料。侧包封材料230的填料含量可以高于NCF 220的填料含量。根据一些示例实施方式，侧包封材料230可以具有约40wt％至约90wt％的填料含量。侧包封材料230的杨氏模量可以大于NCF 220的杨氏模量。侧包封材料230可以比NCF220不透明。
返回参照图1A，从顶视图看的侧包封材料230的形状的(或在与封装基板100的顶表面相同水平处的侧包封材料230的水平剖面形状的)内轮廓线可以不同于其外轮廓线。例如，侧包封材料230的布局的内轮廓线可以包括曲线，而侧包封材料230的布局的外轮廓线可以包括直线。因为NCF 220的形状在形成侧包封材料230的工艺期间被传递，所以侧包封材料230的布局的内轮廓线可以与NCF 220的布局的外轮廓线相同或基本相似。因为半导体芯片200的形状在形成侧包封材料230的工艺期间被传递，所以侧包封材料230的布局的外轮廓线可以与半导体芯片200的布局的外轮廓线相同或基本相似。
TIM层240可以布置在半导体芯片200上。TIM层240可以包括用于消散半导体模块的高功率器件中的热的导热化合物。TIM层240可以减小高功率器件的金属与散热器250之间的热接触电阻。
TIM层240可以具有相对高的填料含量。从存在大的温度变化的情形(例如，半导体芯片200的初始操作)开始，TIM层240可以提供高度可靠的热接触电阻特性。因此，半导体封装10在没有单独的预烧(burn-in)循环的情况下可以是可操作的。TIM层240可以包括绝缘层，但不限于此。根据一些示例实施方式，TIM层240可以不包括硅。TIM层240可以通过减轻或防止在半导体芯片200与散热器250之间形成空隙来增强散热。
散热器250可以是一种被动热交换器。散热器250可以控制半导体芯片200以使其处于最佳操作温度。散热器250可以具有增大或最大化接触冷却介质的表面积的结构(例如波纹状结构)。
散热器250可以包括铜或铝，但不限于此。当散热器250包括铜时，散热器250可以具有相对高的热效率和相对高的耐久性。当散热器250包括铝时，散热器250具有比当散热器250包括铜时低的热导率，但是可以降低散热器250的制造成本和重量。
图2是根据一示例实施方式的半导体封装10'的示意性布局图。
为了便于描述，将省略以上参照图1A至图1D给出的多余的描述，并且以下描述将集中于不同之处。
参照图2，半导体封装10'可以包括侧包封材料230'，该侧包封材料230'具有与图1A的半导体封装10的侧包封材料230不同的从顶视图看的形状。
根据一些示例实施方式，侧包封材料230'可以小于图1A的侧包封材料230。例如，侧包封材料230'可以具有比图1A的侧包封材料230小的水平宽度。因此，因为NCF 220的形状被传递到侧包封材料230'，所以从顶视图看的侧包封材料230'的形状的内轮廓线和外轮廓线可以包括曲线。例如，当从顶视图看的NCF 220的形状具有圆形轮廓线时，从顶视图看的侧包封材料230'的形状的内轮廓线和外轮廓线两者可以与NCF 220的圆形轮廓线的中心同心。
根据一些示例实施方式，半导体芯片200在未填充区域UR中的形状和NCF 220在突出区域PR中的形状可以被传递给从顶视图看的侧包封材料230'的形状。在这样的情况下，在从顶视图看的侧包封材料230'的形状的外轮廓线中，拐角之间的中间部分可以包括曲线，并且每个拐角可以包括直线。
图3A是根据一示例实施方式的半导体封装20的示意性布局图。
图3B是沿图3A中的线IIIB-IIIB'截取的剖视图。
为了便于描述，将省略以上参照图1A至图1D给出的多余的描述，并且以下描述将集中于不同之处。
参照图3A和图3B，与图1A至图1D的半导体封装10不同，未填充区域UR可以被进一步限定在半导体芯片200的每一条边的远离半导体芯片200的两个相邻拐角的部分之下。因此，NCF 220可以具有从顶视图看的X形状或四片叶子的四叶草形状。因此，可以相对于半导体芯片200的每一条边限定两个突出区域PR。
尽管在图3A和图3B中示出了，除了半导体芯片200的每个拐角之外，还对应于半导体芯片200的每一条边的中间部分限定未填充区域UR，但本发明构思的示例实施方式不限于此。例如，未填充区域UR可以不对应于半导体芯片200的拐角中的一些来限定，或者可以仅对应于半导体芯片200的边中的一些来限定。
图4是根据一示例实施方式的半导体封装30的示意性布局图。
为了便于描述，将省略以上参照图1A至图1D给出的多余的描述，并且以下描述将集中于不同之处。
参照图4，当从上方观察时，NCF 220可以在X方向和Y方向上从半导体芯片200突出。根据一些示例实施方式，从顶视图看的NCF 220的轮廓线可以包括弯曲部分和笔直部分。
图5是根据一示例实施方式的制造半导体封装的方法的示意性流程图。
图6至图10是根据一示例实施方式的制造半导体封装的方法中的阶段的剖视图。
参照图5和图6，在操作P110中，半导体芯片200可以被切单。
半导体芯片200的切单可以包括沿着划道SL切割晶片W，该晶片W包括半导体芯片200并且具有附接到其的NCF 220。NCF 220可以包括透明材料。NCF 220可以基于其总重量具有约30wt％至约60wt％的填料含量。由于NCF 220的透明性，可以提高切单工艺的可靠性。
在切单工艺之前，可以执行用于形成包括在半导体芯片200中的电路器件的一系列工艺、提供连接器210的工艺以及提供NCF 220的工艺。这些工艺可以包括在半导体芯片200的切单之前对晶片W的正面执行的晶片级工艺、以及包含用于将半导体芯片200的电路器件连接到连接端子210的金属化的后段(BEOL)工艺。
尽管在图6中示出了使用切割刀片BL执行切单，但是本发明构思的示例实施方式不限于此。例如，可以使用激光锯切来执行切单。
参照图5和图7，在操作P120中，可以将半导体芯片200安装在封装基板100上。
因为NCF 220在半导体芯片200的切单期间也被切单，所以从顶视图来看，NCF 220的形状和面积可以与半导体芯片200的形状和面积相同。
参照图5和图8，在操作P130中，可以执行热压工艺。
热压工艺可以包括使用包含加热构件的压头以一定的热和压力将半导体芯片200压在封装基板100上。
由于热压工艺，焊料212可以连接到上焊盘122中的对应一个，并且NCF 220可以被硬化。根据一些示例实施方式，可以通过热压工艺来改变NCF 220的形状，因此，NCF 220的顶视图形状和水平面积可以不同于半导体芯片200的顶视图形状和水平面积。当NCF 220的形状通过热压工艺被改变时，NCF 220可以不设置在半导体芯片200与封装基板100之间的空间的至少一部分中。
参照图5和图9，在操作P140中，可以形成侧包封材料230。
侧包封材料230的形成可以包括：沿着半导体芯片200的侧表面提供底部填充材料(例如液态树脂)；以及使底部填充材料硬化，使得半导体芯片200接合到封装基板100。液态树脂可以填充半导体芯片200与封装基板100之间的其中不存在NCF 220的空间，以形成侧包封材料230。
因此，侧包封材料230和NCF 220一起完全填充半导体芯片200与封装基板100之间的空间，因此，可以提高半导体封装的可靠性。
通过使用人工智能(AI)逻辑芯片和第五代(5G)模块，高性能和高功率半导体芯片被用于系统封装中。高性能和高功率半导体芯片包括具有超精细节距的I/O端子以增加I/O容量，并使用大主体基板(LBS)技术以具有相对大的芯片尺寸(例如100mm2或更大的水平面积)。
对于高性能和高功率半导体芯片，当将回流工艺应用于包括超低K(ULK)电介质层的精细节距半导体芯片以减轻或防止电阻电容(RC)延迟时，由于半导体芯片与封装基板(例如印刷电路板)之间的热膨胀系数不匹配，可能发生BEOL裂纹(crack)和凸块打开(bump-open)故障。
为了减轻或防止这样的BEOL裂纹和凸块打开故障，可以用利用NCF的热压工艺代替回流工艺。在热压工艺期间，使用接合工具同时加热和按压半导体芯片。由于热压工艺，NCF硬化并支撑凸块，从而减轻在接合工艺期间施加到凸块的应力。
因为在利用NCF的热压工艺中NCF的接合特性被放在首位，所以在技术上难以控制NCF的机械性能。在一些示例实施方式中，NCF可以不形成或不规则地形成在半导体芯片的边缘和拐角中，以避免沿着半导体芯片的边缘(例如拐角)的破裂或分层。
根据一些示例实施方式，在执行利用NCF的热压工艺之后，沿着半导体芯片的外边缘提供单位质量具有相对高的填料含量的侧包封材料。因此，可以减轻或防止NCF破裂和分层，因此可以提高半导体封装的制造可靠性。
参照图5和图10，在操作P150中，可以提供TIM层240和散热器250。
TIM层240和散热器250与参照图1A至图1D描述的TIM层240和散热器250相同或基本相似。
随后，参照图5和图1B，在操作P160中，提供外部连接端子130。
根据一些示例实施方式，外部连接端子130可以包括UBM层131和焊料132。UBM层131和焊料132可以使用电镀形成。
图11至图14是根据一些示例实施方式的半导体封装40、50、60和70的示意性布局图。
为了便于描述，将省略以上参照图1A至图1D给出的描述，并且以下描述将集中于不同之处。
参照图11，与图1A至图1D的半导体封装10不同，半导体封装40可以包括长度限制构件225和无源元件260。
长度限制构件225可以限制使用底部填充工艺形成的侧包封材料230的分布。根据一些示例实施方式，长度限制构件225可以围绕半导体芯片200。在这种情况下，长度限制构件225可以限制在半导体封装40中分配给侧包封材料230的水平面积(例如，侧包封材料230的X方向长度和Y方向长度)，因此，可以增大半导体封装40的集成密度。
根据一些示例实施方式，长度限制构件225可以包括在Y方向上延伸并且在X方向上彼此分离的两个条状物。在这种情况下，仅侧包封材料230的X方向长度可以被限制。
无源元件260可以包括例如多层陶瓷电容器(MLCC)。MLCC可以阻挡外部噪声。
参照图12，与图11的半导体封装40不同，半导体封装50可以不包括TIM层240和散热器250。
半导体封装50可以包括加强件255，以增强封装基板100(例如印刷电路板)的机械强度并保护半导体芯片200。
参照图13，半导体封装60可以包括封装基板100、中介层基板(interposersubstrate)300以及第一至第三半导体芯片410、420和430。半导体封装60还可以包括加强件255、无源元件260、包括UBM层311和焊料312的连接端子310、NCF 320、侧包封材料330以及粘合膜340。
中介层基板300可以包括包含半导体材料的基板基底、在基板基底的顶表面上的上焊盘、以及在基板基底的底表面上的下焊盘。例如，基板基底可以由硅晶片形成。内部布线可以形成在基板基底的顶表面和底表面以及内部中。此外，将上焊盘电连接到下焊盘的多个贯通通路可以形成在基板基底的内部中。
多个连接端子310可以布置在中介层基板300之下。连接端子310与图1B中的连接端子210相同或基本相似。中介层基板300可以通过连接端子310电连接到封装基板100。
NCF 320和侧包封材料330与图1B中的NCF 220和侧包封材料230相同或基本相似，因而将省略其详细描述。根据一些示例实施方式，中介层基板300可以通过NCF 320和侧包封材料330接合到封装基板100。因此，可以提高半导体封装60的可靠性。
第一至第三半导体芯片410、420和430可以通过粘合膜340固定到中介层基板300。第一至第三半导体芯片410、420和430可以包括包含DRAM芯片的HBM、图形处理单元(GPU)、ASIC、FPGA、CPU或RF芯片，但不限于此。尽管未示出，但是连接端子可以在中介层基板300与第一至第三半导体芯片410、420和430之间。第一至第三半导体芯片410、420和430可以通过连接端子电连接到中介层基板300的内部布线(例如，贯通通路以及上焊盘和下焊盘)。
参照图14，与图1A至图1D的半导体封装10相比，半导体封装70还可以包括第四半导体芯片440。第四半导体芯片440可以通过包括UBM层441和焊料442的连接端子443连接到封装基板100。
TIM层445可以布置在第四半导体芯片440的顶表面上，以形成与散热器250的热接触。TIM层445可以与TIM层240相同或基本相似。
第四半导体芯片440可以相对小于半导体芯片200。因此，第四半导体芯片440可以通过回流工艺连接到封装基板100，并且NCF或侧包封材料可以不形成在第四半导体芯片440与封装基板100之间。
图15是根据一示例实施方式的包括半导体封装的系统1200的示意性方块图。
参照图15，系统1200包括控制器1210、I/O装置1220、存储装置1230和接口1240。根据一些示例实施方式，系统1200可以包括图1A至图1D的半导体封装10、图2至图4的半导体封装10'、20和30以及图12至图14的半导体封装40、50、60和70之一，或由图1A至图1D的半导体封装10、图2至图4的半导体封装10'、20和30以及图12至图14的半导体封装40、50、60和70之一实现。
系统1200可以包括移动系统、或发送或接收信息的系统。在一些示例实施方式中，移动系统可以包括个人数字助理(PDA)、便携式计算机、网络平板电脑、无线电话、移动电话、数字音乐播放器或存储卡。
控制器1210控制系统1200中的可运行程序。控制器1210可以包括微处理器、数字信号处理器、微控制器等。
I/O装置1220可以输入或输出系统1200的数据。系统1200可以通过I/O装置1220连接到外部装置(例如个人计算机或网络)并与之交换数据。例如，I/O装置1220可以包括小键盘、键盘或显示器。
存储装置1230可以存储用于操作控制器1210的代码和/或数据，或存储由控制器1210处理的数据。
接口1240可以是系统1200与外部装置之间的数据传输通道。控制器1210、I/O装置1220、存储装置1230和接口1240可以通过总线1250彼此通信。系统1200可以被包括在移动电话、MP3播放器、导航装置、便携式多媒体播放器(PMP)、固态盘(SSD)或家用电器中。
虽然已经参照本发明构思的一些示例实施方式具体显示和描述了本发明的构思，但是将理解，在不背离所附权利要求的精神和范围的情况下，可以在其中进行在形式和细节上的各种改变。
本申请要求享有2019年8月26日在韩国知识产权局提交的韩国专利申请第10-2019-0104579号的优先权，该韩国专利申请的公开内容通过引用全文合并于此。

Claims (20)

1.一种半导体封装，包括：
封装基板；
在所述封装基板的顶表面上的半导体芯片；
在所述封装基板与所述半导体芯片之间的连接端子，所述连接端子将所述封装基板连接到所述半导体芯片；
在所述封装基板与所述半导体芯片之间的非导电膜，所述非导电膜围绕所述连接端子并且将所述半导体芯片接合到所述封装基板；以及
侧包封材料，覆盖所述半导体芯片的侧表面、接触所述封装基板并且包括在所述半导体芯片的底表面与所述封装基板的所述顶表面之间的第一部分，
其中所述非导电膜包括当从上方观察时从所述半导体芯片水平突出的第二部分，并且所述侧包封材料与所述半导体芯片的所述底表面的一部分接触。
2.根据权利要求1所述的半导体封装，其中所述侧包封材料具有与所述非导电膜不同的填料质量含量。
3.根据权利要求2所述的半导体封装，其中所述侧包封材料具有比所述非导电膜高的填料质量含量。
4.根据权利要求2所述的半导体封装，其中所述侧包封材料具有在40wt％与90wt％之间的填料质量含量。
5.根据权利要求2所述的半导体封装，其中所述非导电膜具有在30wt％与60wt％之间的填料质量含量。
6.根据权利要求1所述的半导体封装，其中所述非导电膜是透明的。
7.根据权利要求1所述的半导体封装，其中所述侧包封材料具有比所述非导电膜高的杨氏模量。
8.根据权利要求1所述的半导体封装，其中所述侧包封材料包括液态树脂。
9.一种半导体封装，包括：
印刷电路板，包括基板基底、在所述基板基底的顶表面上的第一焊盘、覆盖所述基板基底的所述顶表面并且暴露所述第一焊盘的至少一部分的第一阻焊层、在所述基板基底的底表面上的第二焊盘以及覆盖所述基板基底的所述底表面并且暴露所述第二焊盘的至少一部分的第二阻焊层；
半导体芯片，在所述印刷电路板的所述顶表面上，所述半导体芯片具有从顶视图看的四边形形状；
连接端子，在所述印刷电路板与所述半导体芯片之间，所述连接端子包括接触所述第一焊盘的第一凸块下金属化层和接触所述第一凸块下金属化层的第一焊料；
外部连接端子，包括接触所述第二焊盘的第二凸块下金属化层和接触所述第二凸块下金属化层的第二焊料，所述外部连接端子大于所述连接端子；
非导电膜，在所述印刷电路板与所述半导体芯片之间的空间的仅一部分中，所述非导电膜围绕所述连接端子并且将所述印刷电路板接合到所述半导体芯片；以及
侧包封材料，在所述半导体芯片的底表面与所述印刷电路板的所述顶表面之间，所述侧包封材料覆盖所述半导体芯片的侧表面并且接触所述印刷电路板。
10.根据权利要求9所述的半导体封装，其中所述印刷电路板与所述半导体芯片之间的所述空间被所述非导电膜、所述侧包封材料和所述连接端子完全填充。
11.根据权利要求9所述的半导体封装，其中从顶视图看的所述非导电膜的形状不同于从顶视图看的所述半导体芯片的所述形状。
12.根据权利要求9所述的半导体封装，其中从顶视图看的所述非导电膜的轮廓线包括曲线部分。
13.根据权利要求9所述的半导体封装，其中当从上方观察时，所述非导电膜在横向方向上从所述半导体芯片突出。
14.根据权利要求9所述的半导体封装，其中所述非导电膜不在与所述半导体芯片的所述四边形形状的四个拐角中的至少一个对应的第一拐角之下。
15.根据权利要求14所述的半导体封装，其中所述侧包封材料在所述第一拐角之下。
16.根据权利要求9所述的半导体封装，其中所述半导体芯片的水平面积为至少100mm2。
17.一种半导体封装，包括：
封装基板；
在所述封装基板的顶表面上的半导体芯片；
非导电膜，在所述封装基板与所述半导体芯片的底表面之间的空间的仅一部分中，所述非导电膜具有比所述半导体芯片大的水平面积；以及
沿着所述半导体芯片的侧表面的侧包封材料，所述侧包封材料覆盖所述半导体芯片的所述侧表面并且接触所述封装基板的所述顶表面和所述半导体芯片的所述底表面。
18.根据权利要求17所述的半导体封装，其中所述非导电膜不在所述半导体芯片的至少一个拐角之下。
19.根据权利要求17所述的半导体封装，其中所述非导电膜不在与所述半导体芯片的所述侧表面中的一个对应的第一侧表面的中间部分之下。
20.根据权利要求17所述的半导体封装，其中所述非导电膜和所述侧包封材料一起完全填充在所述封装基板与所述半导体芯片之间。
CN202010861476.XA 2019-08-26 2020-08-25 半导体封装 Active CN112435968B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2019-0104579 2019-08-26
KR1020190104579A KR102633142B1 (ko) 2019-08-26 2019-08-26 반도체 패키지

Publications (2)

Publication Number Publication Date
CN112435968A true CN112435968A (zh) 2021-03-02
CN112435968B CN112435968B (zh) 2024-04-19

Family

ID=74681725

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010861476.XA Active CN112435968B (zh) 2019-08-26 2020-08-25 半导体封装

Country Status (3)

Country Link
US (2) US11164805B2 (zh)
KR (1) KR102633142B1 (zh)
CN (1) CN112435968B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115377021A (zh) * 2022-08-29 2022-11-22 北京超材信息科技有限公司 电子器件模组封装结构及制作方法
KR102640929B1 (ko) 2023-06-02 2024-02-27 (주) 멥스젠 미세생체조직시스템 형성 장치
CN117038683A (zh) * 2023-07-07 2023-11-10 信扬科技(佛山)有限公司 光机电模组、半导体封装组件及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373142B1 (en) * 1999-11-15 2002-04-16 Lsi Logic Corporation Method of adding filler into a non-filled underfill system by using a highly filled fillet
JP2002170854A (ja) * 2000-11-30 2002-06-14 Hitachi Cable Ltd 半導体装置及びその製造方法
CN101166395A (zh) * 2006-10-18 2008-04-23 松下电器产业株式会社 半导体安装基板及其制造方法
US20150255312A1 (en) * 2014-03-05 2015-09-10 International Business Machines Corporation Low-stress dual underfill packaging
CN110473796A (zh) * 2018-05-09 2019-11-19 德克萨斯仪器股份有限公司 用于倒装芯片封装件的多个底部填充剂

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866953A (en) 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
CN1378769A (zh) * 1999-08-12 2002-11-06 Ibiden股份有限公司 多层印刷电路板、阻焊配方、多层印刷电路板的制造方法和半导体器件
JP4945919B2 (ja) * 2005-04-25 2012-06-06 凸版印刷株式会社 Ｂｇａ型多層回路配線板
JP5075463B2 (ja) 2007-04-19 2012-11-21 ルネサスエレクトロニクス株式会社 半導体装置
US8084553B2 (en) 2008-01-10 2011-12-27 Trillion Science, Inc. Curable adhesive compositions, process, and applications
US7973310B2 (en) 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
JP4984099B2 (ja) 2009-02-27 2012-07-25 ソニーケミカル＆インフォメーションデバイス株式会社 半導体装置の製造方法
US8067484B2 (en) 2010-03-12 2011-11-29 Trillion Science, Inc. Latent hardener with improved barrier properties and compatibility
US8044154B2 (en) 2009-06-12 2011-10-25 Trillion Science, Inc. Latent hardener for epoxy compositions
KR101715761B1 (ko) * 2010-12-31 2017-03-14 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR20120123919A (ko) 2011-05-02 2012-11-12 삼성전자주식회사 칩 적층 반도체 패키지 제조 방법 및 이에 의해 제조된 칩 적층 반도체 패키지
KR101814022B1 (ko) 2012-01-27 2018-01-04 삼성전자주식회사 반도체 패키지
JP5965185B2 (ja) * 2012-03-30 2016-08-03 デクセリアルズ株式会社 回路接続材料、及びこれを用いた半導体装置の製造方法
KR101374146B1 (ko) 2012-06-27 2014-03-17 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US9209156B2 (en) 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
KR101514137B1 (ko) 2013-08-06 2015-04-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
JP6157998B2 (ja) * 2013-09-03 2017-07-05 ルネサスエレクトロニクス株式会社 半導体装置
KR102107961B1 (ko) * 2013-11-14 2020-05-28 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
KR20150066184A (ko) * 2013-12-06 2015-06-16 삼성전자주식회사 반도체 패키지 및 그 제조방법
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
TWI567886B (zh) * 2014-05-28 2017-01-21 南茂科技股份有限公司 晶片封裝結構以及晶片封裝結構的製作方法
KR102245003B1 (ko) * 2014-06-27 2021-04-28 삼성전자주식회사 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법
KR20160034496A (ko) * 2014-09-19 2016-03-30 삼성전자주식회사 반도체 패키지 제조방법
KR101680428B1 (ko) 2014-10-10 2016-11-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 ncf 및 이의 제조 방법, ncf를 이용한 반도체 패키지 제조 방법
KR102341750B1 (ko) * 2015-06-30 2021-12-23 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR102478381B1 (ko) 2015-12-21 2022-12-20 삼성전자주식회사 반도체 패키지
KR102579876B1 (ko) 2016-02-22 2023-09-18 삼성전자주식회사 반도체 패키지
KR102505853B1 (ko) * 2016-07-06 2023-03-03 삼성전자 주식회사 반도체 패키지
KR102649471B1 (ko) * 2016-09-05 2024-03-21 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
KR20180137888A (ko) * 2017-06-20 2018-12-28 주식회사 프로텍 반도체 칩 본딩 장치 및 반도체 칩 본딩 방법
TWI643302B (zh) * 2017-11-29 2018-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
KR102467030B1 (ko) * 2018-01-17 2022-11-14 삼성전자주식회사 반도체 패키지 및 그 패키지를 포함한 반도체 장치
KR20200144370A (ko) * 2019-06-18 2020-12-29 삼성전자주식회사 히트 스프레더를 갖는 반도체 패키지

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373142B1 (en) * 1999-11-15 2002-04-16 Lsi Logic Corporation Method of adding filler into a non-filled underfill system by using a highly filled fillet
JP2002170854A (ja) * 2000-11-30 2002-06-14 Hitachi Cable Ltd 半導体装置及びその製造方法
CN101166395A (zh) * 2006-10-18 2008-04-23 松下电器产业株式会社 半导体安装基板及其制造方法
US20150255312A1 (en) * 2014-03-05 2015-09-10 International Business Machines Corporation Low-stress dual underfill packaging
CN110473796A (zh) * 2018-05-09 2019-11-19 德克萨斯仪器股份有限公司 用于倒装芯片封装件的多个底部填充剂

Also Published As

Publication number Publication date
US11676875B2 (en) 2023-06-13
US20210066148A1 (en) 2021-03-04
KR20210024866A (ko) 2021-03-08
KR102633142B1 (ko) 2024-02-02
CN112435968B (zh) 2024-04-19
US20220020653A1 (en) 2022-01-20
US11164805B2 (en) 2021-11-02

Similar Documents

Publication Publication Date Title
US10204892B2 (en) Semiconductor package
KR101645507B1 (ko) 반도체 패키지 내의 다이간 간격을 감소시키는 언더필 물질 플로우 제어
KR102057210B1 (ko) 반도체 칩 및 이를 갖는 적층형 반도체 패키지
US8945985B2 (en) Semiconductor package and method of manufacturing the same
CN112435968B (zh) 半导体封装
US10770364B2 (en) Chip scale package (CSP) including shim die
US8338929B2 (en) Stacked-type chip package structure and fabrication method thereof
US20150162265A1 (en) Semiconductor package and method of manufacturing the same
US20150340343A1 (en) Integrated circuit package assembly
US20150228591A1 (en) Semiconductor package and method of manufacturing the same
KR101939240B1 (ko) 반도체 패키지
US20210305122A1 (en) Semiconductor package and manufacturing method thereof
WO2013009853A2 (en) Electronic assembly including die on substrate with heat spreader having an open window on the die
US11671010B2 (en) Power delivery for multi-chip-package using in-package voltage regulator
KR102287761B1 (ko) 방열 부재를 가지는 반도체 패키지
US11862613B2 (en) Semiconductor package
US20230261572A1 (en) Power delivery for multi-chip-package using in-package voltage regulator
US20130256915A1 (en) Packaging substrate, semiconductor package and fabrication method thereof
US11600607B2 (en) Semiconductor module including multiple power management semiconductor packages
US20150031170A1 (en) Method and apparatus for stacked semiconductor chips
KR102644598B1 (ko) 반도체 패키지
US11581290B2 (en) Semiconductor package
CN212342601U (zh) 一种多芯片超薄扇出型封装结构
US20240186209A1 (en) Semiconductor package structure
US20240162188A1 (en) Semiconductor package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant