CN111344856A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN111344856A CN111344856A CN201780096691.1A CN201780096691A CN111344856A CN 111344856 A CN111344856 A CN 111344856A CN 201780096691 A CN201780096691 A CN 201780096691A CN 111344856 A CN111344856 A CN 111344856A
- Authority
- CN
- China
- Prior art keywords
- resin
- semiconductor device
- resin layer
- insulating film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 title claims description 8
- 239000011347 resin Substances 0.000 claims abstract description 198
- 229920005989 resin Polymers 0.000 claims abstract description 198
- 230000035699 permeability Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004593 Epoxy Substances 0.000 claims description 8
- 229920001187 thermosetting polymer Polymers 0.000 claims description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 9
- 239000004642 Polyimide Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
半导体装置具有:半导体器件(2),其在半导体芯片(1)的主面具有电极以及配线;第1树脂构造体(A),其配置于该半导体芯片(1)的主面侧,在所述半导体器件(2)的特定的电极(3)的侧方以及上方,与该特定的电极(3)之间构成中空构造(8);第2树脂构造体(B),其将所述第1树脂构造体(A)的外侧覆盖,介电常数小于或等于该第1树脂构造体(A);以及绝缘膜(11),其将所述第2树脂构造体(B)的外侧覆盖,透湿性小于该第2树脂构造体(B)。
Description
技术领域
本发明涉及在半导体器件的电极的周围具有中空构造的半导体装置及其制造方法。
背景技术
为了实现半导体装置的高集成化和小型化,使用在半导体芯片之上反复层叠树脂膜和金属配线的多层配线构造。但是,由于树脂膜,例如场效应晶体管(简称为FET。下面相同)的栅极与源极间、或者栅极与漏极间的寄生电容增加,半导体器件的高频特性劣化。
另外,就将半导体芯片收容于封装体而没有使用多层配线的构造的半导体装置而言,为了小型化、低价格化,有时与在陶瓷等绝缘体的中空容器内搭载半导体芯片的构造相比,优选通过树脂模塑而封装了半导体芯片的封装体构造,但如果与中空封装的情况相比,则由于树脂模塑封装所用的树脂的介电常数而使寄生电容(与杂散电容相同。下面相同)增加,产生增益等高频特性的劣化。
因此,为了改善上述高频特性的劣化,提出了通过在半导体芯片之上形成中空构造而抑制寄生电容的增加的构造的半导体装置(例如,参照专利文献1、专利文献2)。
半导体芯片之上的中空构造例如通过如下等工序形成,即,(a)在半导体基板的主面形成了FET后,(b)在该半导体基板的主面之上,形成不与FET的栅极电极接触、将栅极电极的侧方包围的第1树脂层,(c)然后使不与栅极电极接触、将栅极电极的上方覆盖的第2树脂层与第1树脂构造的上表面接合而形成中空构造,然后进行加热处理使树脂构造固化。(d)通过透湿性比形成中空构造的树脂小的绝缘膜将中空构造覆盖,提高中空构造的耐湿性。
专利文献1:日本特开平5-335343号公报
专利文献2:日本特开2016-39319号公报
发明内容
就中空构造的形成而言,在使第2树脂层与第1树脂层之上接合(参照上述(c)所示的工序)时的压力弱或者不均匀的情况下,存在贴合性变弱的课题。在贴合性弱的部分,接合剥离而形成水分向中空构造内的侵入路径,存在使半导体器件的耐湿性劣化的问题。
另外,在将该半导体芯片搭载于封装体的情况下,在高温高压下进行树脂模塑封装时,存在贴合性弱的部分被破坏、模塑树脂侵入至中空构造内的问题。
本发明就是为了解决上述课题而提出的,目的在于针对在半导体芯片之上具有中空构造的半导体装置,得到防止耐湿性的劣化或者中空构造的破坏的构造的半导体装置以及其制造方法。
本发明所涉及的半导体装置的特征在于,具有:半导体器件,其在半导体芯片的主面具有电极以及配线;第1树脂构造体,其以与所述半导体器件的特定的电极隔开空间而将该特定的电极的侧方以及上方覆盖的方式配置于所述半导体芯片的主面侧;第2树脂构造体,其将所述第1树脂构造体的外侧覆盖,介电常数小于或等于该第1树脂构造体;以及绝缘膜,其将所述第2树脂构造体的外侧覆盖,透湿性小于该第2树脂构造体。
发明的效果
本发明的半导体装置通过不与电极接触的树脂构造体形成中空构造,通过介电常数小于或等于构成该中空构造的树脂构造体的树脂将该树脂构造体的中空构造的外侧覆盖,因此,不会发生树脂构造体的接合剥离而形成水分向中空构造内的侵入路径这样的情况,能够防止半导体器件的耐湿性的劣化。另外,由于能够降低电极与配线间的寄生电容,因此能够提高半导体装置的高频特性。
附图说明
图1是表示本发明的实施方式1所涉及的半导体装置的一个例子的剖面图。
图2是沿着图1的CS1-CS2的剖面图。
图3是用于对本发明的实施方式1所涉及的半导体装置的晶片的制造工序进行说明的一系列图中的第1个图。
图4是用于对本发明的实施方式1所涉及的半导体装置的晶片的制造工序进行说明的一系列图中的第2个图。
图5是用于对本发明的实施方式1所涉及的半导体装置的晶片的制造工序进行说明的一系列图中的第3个图。
图6是表示本发明的实施方式2所涉及的半导体装置的一个例子的剖面图。
图7是表示本发明的实施方式3所涉及的半导体装置的一个例子的剖面图。
图8是表示本发明的实施方式4所涉及的半导体装置的一个例子的剖面图。
具体实施方式
实施方式1.
下面,使用附图说明本发明的实施方式1所涉及的半导体装置。图1是表示本实施方式1所涉及的半导体装置的一个例子的图。另外,图2是沿着图1的CS1-CS2的剖面图。
就本实施方式1所涉及的半导体装置而言,在半导体芯片1的主面形成有半导体器件2。半导体器件2是具有包含檐的Y型或者T型的栅极电极3、源极电极4、漏极电极5以及配线6的场效应晶体管(FET)。除了FET以外,有时也形成二极管等其他器件,半导体器件2被氮化硅膜(例如SiN)等绝缘膜7覆盖。
另外,半导体器件2的栅极电极3通过使用了聚酰亚胺等的第1树脂层9以及第2树脂层10,将侧方(由具有与栅极电极的侧面相同程度的面积且与栅极电极的侧面平行的面的集合构成的栅极电极的外侧的空间部分)和(栅极电极的)上方覆盖,由第1树脂层9以及第2树脂层10形成的树脂构造体(图中,通过标号A表示的部分。下面,称为第1树脂构造体)不与栅极电极3接触,形成中空构造8。在上述中,以该第1树脂构造体A的材料使用相对介电常数为3左右的聚酰亚胺的情况为前提进行了说明,但也可以使用相对介电常数为2.5~2.7左右的苯并环丁烯树脂(下面称为BCB(BCB,Benzocyclobutene)树脂)。此外,下面,有时将上述中空构造内的电极(上述的例子中为栅极电极)称为特定的电极。
上述第1树脂构造体A的外侧被使用了BCB树脂的第2树脂构造体B覆盖。这样,该第2树脂构造体B的材料使用具有与用于第1树脂构造体A的树脂相同、或者比用于第1树脂构造体A的树脂低的介电常数的树脂。
配线12夹着(隔着)第2树脂构造体B形成在第1树脂构造体A的上方,第2树脂构造体B的外侧被与用于第2树脂构造体B的树脂相比透湿性(每单位时间、每单位面积透过的水分量的值。例如,表示每1m2在24小时透过几g水分的值)小的氮化硅膜(例如SiN)等绝缘膜11以及配线12覆盖。
接着,说明本实施方式1所涉及的半导体装置的晶片的制造工序(参照图3~图5)。
首先,如图3所示,在与上述半导体芯片1相当的半导体基板15的主面形成半导体器件2,通过绝缘膜7覆盖半导体器件2。然后,在半导体基板15的主面之上和半导体器件2之上涂敷感光性聚酰亚胺等感光性树脂而形成了树脂膜,之后通过曝光和显影对树脂膜进行图案化,由此形成不与栅极电极3接触、将栅极电极3的侧方包围的第1树脂层9。此时,在树脂构造的上方形成配线的部位也能够同样地进行图案化而形成开口。
接着,如图4所示,将半固化状态的感光性聚酰亚胺片贴于第1树脂层9的上表面而作为对中空构造进行封装的第2树脂层10,通过曝光和显影对树脂膜进行图案化,由此,在配线的接触部等必要部位设置了开口,之后进行加热处理,使第1树脂层9以及第2树脂层10固化。
接着,如图5所示,在半导体基板15的主面之上或者第1树脂构造体A之上涂敷BCB树脂而形成树脂膜使其硬化后,通过干蚀刻去除开口部或者不需要的部分,形成第2树脂构造体B。然后,形成配线12,然后通过氮化硅膜(例如SiN)等绝缘膜11(未图示)将第2树脂构造体B的侧面或者上方的露出部覆盖,由此能够制造图1的半导体装置。
接着,下面对本实施方式1所涉及的半导体装置的作用进行说明。就本实施方式1所涉及的半导体装置而言,即使在上述第1树脂构造体A存在贴合性弱的部分,也能够通过由第2树脂构造体B对该贴合性弱的部分进行加强,从而防止第1树脂构造体A的接合剥离而形成水分向中空构造内的侵入路径,因此能够防止半导体器件2的耐湿性的劣化。
另外,本实施方式1所涉及的半导体装置的第2树脂构造体B的树脂的介电常数低于第2树脂层10的树脂的介电常数,由此,与仅形成了第1树脂构造体A的情况相比,能够降低栅极电极3与配线12间、或者漏极电极5与配线12间的寄生电容。通过采用这样的结构,能够提高半导体装置的高频特性。
实施方式2.
下面,使用附图说明本发明的实施方式2所涉及的半导体装置。
图6是表示实施方式2所涉及的半导体装置的一个例子的剖面图。在半导体芯片1的主面形成有半导体器件2。
半导体器件2是具有包含檐的Y型或者T型的栅极电极3、源极电极4、漏极电极5以及配线6的场效应晶体管(FET)。除了FET之外,有时也形成二极管等其他器件。这里,半导体器件2被氮化硅膜(例如SiN)等绝缘膜7覆盖。
半导体器件2的栅极电极3被使用了聚酰亚胺等的第1树脂层9以及第2树脂层10覆盖侧方和上方,由第1树脂层9以及第2树脂层10形成的第1树脂构造体A不与栅极电极3接触,形成中空构造8。虽然上述中第1树脂构造体A的材料使用了聚酰亚胺,但也可以使用BCB树脂等。另外,第1树脂构造体A的紧外侧被与用于第1树脂构造体A的树脂相比透湿性小的氮化硅膜(例如SiN)等绝缘膜11覆盖。
半导体芯片1搭载于封装体的框架21,通过导线22(图中为导线22a以及导线22b)将半导体芯片1与框架21电连接。
另外,就该半导体芯片1而言,在上述绝缘膜11的外侧,涂敷介电常数与用于第1树脂构造体A的树脂相同或者比其低的第2树脂构造体B,然后,通过介电常数为4左右的环氧类热固化树脂体23进行封装而封装体化。
另外,就本实施方式2的半导体装置而言,如图6所示,成为第2树脂构造体B保护第1树脂构造体A的构造。而且,通过该构造,当通过上述环氧类热固化树脂体在高温高压环境下进行模塑封装时,能够防止第1树脂构造体A的贴合性弱的部分被破坏而使模塑树脂侵入至第1树脂构造体A的中空构造内。
就本实施方式2的半导体装置而言,特别是,使第2树脂构造体B的介电常数低于环氧类热固化树脂体23,由此与仅形成第1树脂构造体A的情况相比,栅极电极3与配线6间的寄生电容的降低效果变大。由此,就本实施方式2的半导体装置而言,能够提高高频特性。
另外,在上述中,作为将绝缘膜11的外侧覆盖的树脂构造体,以介电常数小于或等于第1树脂构造体A的第2树脂构造体为例进行了说明,但在取代该第2树脂构造体而涂敷了介电常数比其低的例如相对介电常数为2左右的以氟树脂为代表的第3树脂构造体C(未图示)的情况下,其效果当然进一步增加。
实施方式3.
接着,使用附图说明本发明的实施方式3所涉及的半导体装置。
在图7中,在半导体芯片1的主面形成有半导体器件2。该半导体器件2是具有包含檐的Y型或者T型的栅极电极3、源极电极4、漏极电极5及配线6的场效应晶体管(FET)。除了FET之外,有时也形成二极管等其他器件。
另外,上述半导体器件2被氮化硅膜(例如SiN)等绝缘膜7覆盖。该半导体器件2的栅极电极3被使用了聚酰亚胺等的第1树脂层9以及第2树脂层10覆盖侧方和上方,由第1树脂层9以及第2树脂层10形成的第1树脂构造体A不与栅极电极3接触,形成中空构造8。
在上述中,以本实施方式3所涉及的半导体装置的第1树脂构造体A的材料使用了相对介电常数为3左右的聚酰亚胺的情况为前提进行了说明,但也可以使用相对介电常数为2.5~2.7左右的BCB树脂等。
在本实施方式中,第1树脂构造体A的外侧被使用了BCB树脂的第2树脂构造体B覆盖。第2树脂构造体B的材料也可以使用除了BCB树脂以外的相对介电常数为2.5~2.7左右的树脂,使用介电常数与用于第1树脂构造体A的树脂相同、或者比用于第1树脂构造体A的树脂低的树脂。
另外,第2树脂构造体B的外侧覆盖有与用于第2树脂构造体B的树脂相比透湿性小的氮化硅膜(例如SiN)等绝缘膜11。
另外,就本实施方式3的半导体装置而言,半导体芯片1搭载于封装体的框架21,通过导线22(图中为导线22a以及导线22b)将半导体芯片1与框架21电连接,然后,通过与实施方式2中说明的相同的环氧类热固化树脂体23进行封装而封装体化。
接着,下面对本实施方式3所涉及的半导体装置的作用进行说明。当通过上述环氧类热固化树脂体23在高温高压环境下进行模塑封装时,第2树脂构造体B保护第1树脂构造体A。由此,能够防止第1树脂构造体A的贴合性弱的部分被破坏而使模塑树脂侵入至中空构造内。
另外,通过使第2树脂构造体B的介电常数低于环氧类热固化树脂体23,与仅形成了第1树脂构造体A的情况相比,能够降低栅极电极3与配线6间、或者栅极电极3与导线22间的寄生电容。由此,能够提高本实施方式3所涉及的半导体装置的高频特性。
实施方式4.
接着,下面使用图8说明本发明的实施方式4所涉及的半导体装置。
本实施方式4所涉及的半导体装置大致为将上述实施方式2与实施方式3进行了组合的构造。
在该实施方式中,与实施方式2的情况不同(具体而言如图8所示),在第1树脂构造体A的外侧设置有具有比用于第1树脂构造体A的树脂低的介电常数的第2树脂构造体B。而且,透湿性比该第2树脂构造体B小的氮化硅膜(例如SiN)等绝缘膜11将该第2树脂构造体B的外侧覆盖。
并且,在该绝缘膜11的外侧涂敷有介电常数比第1树脂构造体A低、例如相对介电常数为2左右的以氟树脂为代表的第3树脂构造体C。
此外,本实施方式4所涉及的半导体装置的作用和效果与上述实施方式2或者实施方式3相同,因此这里省略其说明。
此外,本发明在其发明的范围内,能够自由地对各实施方式进行组合,或者适当地对各实施方式进行变更、省略。
标号的说明
1半导体芯片,2半导体器件,3栅极电极,4源极电极,5漏极电极,6、12配线,7、11绝缘膜,8中空构造,9第1树脂层,10第2树脂层,15半导体基板,21框架,22、22a、22b导线,23环氧类热固化树脂体,A第1树脂构造体,B第2树脂构造体,C第3树脂构造体。
Claims (8)
1.一种半导体装置,其特征在于,具有:
半导体器件,其在半导体芯片的主面具有电极以及配线;
第1树脂构造体,其以与所述半导体器件的特定的电极隔开空间而将该特定的电极的侧方以及上方覆盖的方式配置于所述半导体芯片的主面侧;
第2树脂构造体,其将所述第1树脂构造体的外侧覆盖,介电常数小于或等于该第1树脂构造体;以及
绝缘膜,其将所述第2树脂构造体的外侧覆盖,透湿性小于该第2树脂构造体。
2.根据权利要求1所述的半导体装置,其特征在于,
多层的配线设置于所述第2树脂构造体的上方。
3.一种半导体装置,其特征在于,具有:
半导体器件,其在半导体芯片的主面具有电极以及配线;
第1树脂构造体,其以与所述半导体器件的特定的电极隔开空间而将该特定的电极的侧方以及上方覆盖的方式配置于所述半导体芯片的主面侧;
绝缘膜,其将所述第1树脂构造体的外侧覆盖,透湿性小于所述第1树脂构造体;以及
第2树脂构造体,其将所述第1树脂构造体以及所述绝缘膜的外侧覆盖,介电常数小于或等于所述第1树脂构造体。
4.根据权利要求1~3中任一项所述的半导体装置,其特征在于,
所述半导体器件、所述第1树脂构造体、所述第2树脂构造体以及所述绝缘膜全部被环氧类热固化树脂体封装而封装体化。
5.根据权利要求4所述的半导体装置,其特征在于,
所述第2树脂构造体以及所述绝缘膜的外侧被第3树脂构造体覆盖,该第3树脂构造体由介电常数小于或等于所述第1树脂构造体以及所述第2树脂构造体的树脂构成。
6.根据权利要求1至5中任一项所述的半导体装置,其特征在于,
所述特定的电极包含檐,所述特定的电极的剖面为Y型形状或者T型形状,并且所述特定的电极在所述檐的下部具有其他中空构造。
7.一种半导体装置的制造方法,其是权利要求1或5所述的半导体装置的制造方法,
其特征在于,包含以下工序:
在半导体基板的主面形成具有电极以及配线的半导体器件;
在半导体基板的主面侧形成第1树脂层,该第1树脂层非接触地将所述半导体器件的特定的电极的侧方包围;
使在所述特定的电极的上方配置的第2树脂层在与所述第1树脂层的上表面接合后固化,与所述特定的电极隔开空间地配置;
在所述第1树脂层以及所述第2树脂层的上方和侧方,通过介电常数比所述第1树脂层以及所述第2树脂层的树脂低的树脂,形成第3树脂层;以及
通过透湿性比该第3树脂层小的绝缘膜将所述第3树脂层的上表面和侧面覆盖。
8.一种半导体装置的制造方法,其是权利要求3所述的半导体装置的制造方法,
其特征在于,包含以下工序:
在半导体基板的主面形成具有电极以及配线的半导体器件;
在半导体基板的主面侧形成第1树脂层,该第1树脂层非接触地将所述半导体器件的特定的电极的侧方包围;
使在所述特定的电极的上方配置的第2树脂层在与所述第1树脂层的上表面接合后固化,与所述特定的电极隔开空间地配置;
通过透湿性比所述第1树脂层以及所述第2树脂层小的绝缘膜将所述第1树脂层以及所述第2树脂层的上方和侧方覆盖;以及
通过介电常数小于或等于所述第1树脂层以及所述第2树脂层的树脂将所述绝缘膜的外侧覆盖。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2017/040936 WO2019097573A1 (ja) | 2017-11-14 | 2017-11-14 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111344856A true CN111344856A (zh) | 2020-06-26 |
CN111344856B CN111344856B (zh) | 2023-05-30 |
Family
ID=63104417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780096691.1A Active CN111344856B (zh) | 2017-11-14 | 2017-11-14 | 半导体装置及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US11348849B2 (zh) |
JP (1) | JP6370515B1 (zh) |
CN (1) | CN111344856B (zh) |
DE (1) | DE112017008195B4 (zh) |
TW (1) | TWI670810B (zh) |
WO (1) | WO2019097573A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112687630A (zh) * | 2020-12-15 | 2021-04-20 | 株洲中车时代半导体有限公司 | 一种功率器件及其制作方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112017008195B4 (de) * | 2017-11-14 | 2023-06-22 | Mitsubishi Electric Corporation | Halbleitereinrichtung und Verfahren zu deren Herstellung |
MX2021011117A (es) * | 2020-06-18 | 2022-01-31 | Tpr Co Ltd | Forro espinoso y metodo de fabricacion del mismo, y metodo de determinacion de la fuerza de adhesion. |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05335343A (ja) * | 1992-05-27 | 1993-12-17 | Sony Corp | 電界効果トランジスタ |
JPH11217440A (ja) * | 1998-02-05 | 1999-08-10 | Hitachi Chem Co Ltd | フルオロアルキル基含有ポリシロキサン、低誘電率樹脂組成物及び物品 |
US6211570B1 (en) * | 1998-12-02 | 2001-04-03 | Fujitsu Limited | Semiconductor device having a multilayer interconnection structure |
US6255732B1 (en) * | 1998-08-14 | 2001-07-03 | Nec Corporation | Semiconductor device and process for producing the same |
JP2001223267A (ja) * | 2000-02-07 | 2001-08-17 | Canon Sales Co Inc | 半導体装置の製造方法 |
JP2004296904A (ja) * | 2003-03-27 | 2004-10-21 | Toshiba Corp | 半導体装置、半導体装置の製造方法 |
JP2005314711A (ja) * | 2005-07-29 | 2005-11-10 | Hitachi Chem Co Ltd | 多孔質膜、物品及び複合材 |
US20060017164A1 (en) * | 2004-05-18 | 2006-01-26 | Kiyotaka Tabuchi | Semiconductor device |
US20080230847A1 (en) * | 2007-03-22 | 2008-09-25 | Takeshi Furusawa | Semiconductor device and manufacturing method of the same |
US20090026589A1 (en) * | 2007-07-26 | 2009-01-29 | Nec Corporation | Semiconductor device and method of manufacturing the same |
CN101492149A (zh) * | 2008-01-25 | 2009-07-29 | 株式会社东芝 | 构建到半导体集成电路中的电器件 |
CN102945840A (zh) * | 2012-11-22 | 2013-02-27 | 苏州晶方半导体科技股份有限公司 | 半导体芯片封装结构及封装方法 |
CN105374743A (zh) * | 2014-08-08 | 2016-03-02 | 三菱电机株式会社 | 半导体装置的制造方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3689613B2 (ja) * | 2000-03-02 | 2005-08-31 | シャープ株式会社 | 半導体装置の製造方法 |
JP2005354046A (ja) * | 2004-05-10 | 2005-12-22 | Toshiba Corp | 半導体装置の製造方法 |
JP2006259757A (ja) * | 2006-04-24 | 2006-09-28 | Semiconductor Energy Lab Co Ltd | 液晶表示装置、アクティブマトリクス型液晶ディスプレイ、及びパーソナルコンピュータ |
JP2009021439A (ja) * | 2007-07-12 | 2009-01-29 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US7943480B2 (en) * | 2008-02-12 | 2011-05-17 | International Business Machines Corporation | Sub-lithographic dimensioned air gap formation and related structure |
JP2009267347A (ja) * | 2008-03-31 | 2009-11-12 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2010205837A (ja) * | 2009-03-02 | 2010-09-16 | Mitsubishi Electric Corp | 電界効果型トランジスタ及びその製造方法 |
JP2011049303A (ja) * | 2009-08-26 | 2011-03-10 | Toshiba Corp | 電気部品およびその製造方法 |
US8399350B2 (en) * | 2010-02-05 | 2013-03-19 | International Business Machines Corporation | Formation of air gap with protection of metal lines |
US8232618B2 (en) * | 2010-08-11 | 2012-07-31 | International Business Machines Corporation | Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach |
JP2014207492A (ja) * | 2011-08-22 | 2014-10-30 | パナソニック株式会社 | 立体映像表示装置 |
KR102108572B1 (ko) * | 2011-09-26 | 2020-05-07 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
JP2015046445A (ja) | 2013-08-27 | 2015-03-12 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
JP6206096B2 (ja) * | 2013-10-31 | 2017-10-04 | 富士通株式会社 | 半導体装置の製造方法 |
US9365411B2 (en) * | 2014-02-03 | 2016-06-14 | Seiko Epson Corporation | MEMS device and method for manufacturing the same |
JP6237429B2 (ja) | 2014-04-14 | 2017-11-29 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
JP6295802B2 (ja) * | 2014-04-18 | 2018-03-20 | ソニー株式会社 | 高周波デバイス用電界効果トランジスタおよびその製造方法、ならびに高周波デバイス |
JP6520197B2 (ja) * | 2015-02-20 | 2019-05-29 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
CN108028224B (zh) * | 2015-10-16 | 2022-08-16 | 索尼公司 | 半导体装置以及半导体装置的制造方法 |
JP6810350B2 (ja) * | 2016-12-28 | 2021-01-06 | 富士通株式会社 | 半導体装置、半導体装置の製造方法及び電子装置 |
DE112017008195B4 (de) * | 2017-11-14 | 2023-06-22 | Mitsubishi Electric Corporation | Halbleitereinrichtung und Verfahren zu deren Herstellung |
-
2017
- 2017-11-14 DE DE112017008195.5T patent/DE112017008195B4/de active Active
- 2017-11-14 CN CN201780096691.1A patent/CN111344856B/zh active Active
- 2017-11-14 US US16/634,526 patent/US11348849B2/en active Active
- 2017-11-14 JP JP2018508264A patent/JP6370515B1/ja active Active
- 2017-11-14 WO PCT/JP2017/040936 patent/WO2019097573A1/ja active Application Filing
-
2018
- 2018-02-22 TW TW107105971A patent/TWI670810B/zh active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05335343A (ja) * | 1992-05-27 | 1993-12-17 | Sony Corp | 電界効果トランジスタ |
JPH11217440A (ja) * | 1998-02-05 | 1999-08-10 | Hitachi Chem Co Ltd | フルオロアルキル基含有ポリシロキサン、低誘電率樹脂組成物及び物品 |
US6255732B1 (en) * | 1998-08-14 | 2001-07-03 | Nec Corporation | Semiconductor device and process for producing the same |
US6211570B1 (en) * | 1998-12-02 | 2001-04-03 | Fujitsu Limited | Semiconductor device having a multilayer interconnection structure |
JP2001223267A (ja) * | 2000-02-07 | 2001-08-17 | Canon Sales Co Inc | 半導体装置の製造方法 |
JP2004296904A (ja) * | 2003-03-27 | 2004-10-21 | Toshiba Corp | 半導体装置、半導体装置の製造方法 |
US20060017164A1 (en) * | 2004-05-18 | 2006-01-26 | Kiyotaka Tabuchi | Semiconductor device |
JP2005314711A (ja) * | 2005-07-29 | 2005-11-10 | Hitachi Chem Co Ltd | 多孔質膜、物品及び複合材 |
US20080230847A1 (en) * | 2007-03-22 | 2008-09-25 | Takeshi Furusawa | Semiconductor device and manufacturing method of the same |
US20090026589A1 (en) * | 2007-07-26 | 2009-01-29 | Nec Corporation | Semiconductor device and method of manufacturing the same |
CN101492149A (zh) * | 2008-01-25 | 2009-07-29 | 株式会社东芝 | 构建到半导体集成电路中的电器件 |
CN102945840A (zh) * | 2012-11-22 | 2013-02-27 | 苏州晶方半导体科技股份有限公司 | 半导体芯片封装结构及封装方法 |
CN105374743A (zh) * | 2014-08-08 | 2016-03-02 | 三菱电机株式会社 | 半导体装置的制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112687630A (zh) * | 2020-12-15 | 2021-04-20 | 株洲中车时代半导体有限公司 | 一种功率器件及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
DE112017008195T5 (de) | 2020-07-23 |
JPWO2019097573A1 (ja) | 2019-11-14 |
JP6370515B1 (ja) | 2018-08-08 |
DE112017008195B4 (de) | 2023-06-22 |
TW201919163A (zh) | 2019-05-16 |
TWI670810B (zh) | 2019-09-01 |
WO2019097573A1 (ja) | 2019-05-23 |
CN111344856B (zh) | 2023-05-30 |
US11348849B2 (en) | 2022-05-31 |
US20200176340A1 (en) | 2020-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10446504B2 (en) | Chip package and method for forming the same | |
US20200013735A1 (en) | Semiconductor package structure with antenna | |
US11024954B2 (en) | Semiconductor package with antenna and fabrication method thereof | |
US20170147857A1 (en) | Chip package and method for forming the same | |
CN101667548A (zh) | 制造具有应力消除层的传感器装置的方法 | |
US20070090543A1 (en) | Plastic packaged device with die interface layer | |
CN111344856B (zh) | 半导体装置及其制造方法 | |
US10147661B2 (en) | Semiconductor device | |
US20170207194A1 (en) | Chip package and method for forming the same | |
US10461002B2 (en) | Fabrication method of electronic module | |
US9018044B2 (en) | Chip-on-lead package and method of forming | |
US8569169B2 (en) | Bottom source power MOSFET with substrateless and manufacturing method thereof | |
US20140117537A1 (en) | Semiconductor package and method of fabricating the same | |
US9576845B2 (en) | Method for manufacturing a semiconductor device including a hollow structure around an electrode of a semiconductor element | |
JP2008078555A (ja) | 半導体装置およびその製造方法 | |
JP2014220463A (ja) | 半導体装置 | |
US11342240B2 (en) | Semiconductor device | |
JP6757293B2 (ja) | 化合物半導体集積回路及びその作製方法 | |
US9136379B2 (en) | Bottom source substrateless power MOSFET | |
US20190252301A1 (en) | Electronic device and manufacturing method thereof | |
US11244863B2 (en) | Method for manufacturing semiconductor apparatus | |
US9704771B2 (en) | Flip-chip mounted semiconductor device | |
JP2021057452A (ja) | モジュールおよびその製造方法 | |
JP2007053285A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |