CN1113398C - 在半导体器件中形成保护膜的方法 - Google Patents

在半导体器件中形成保护膜的方法 Download PDF

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CN1113398C
CN1113398C CN97125706A CN97125706A CN1113398C CN 1113398 C CN1113398 C CN 1113398C CN 97125706 A CN97125706 A CN 97125706A CN 97125706 A CN97125706 A CN 97125706A CN 1113398 C CN1113398 C CN 1113398C
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film
sog film
silicon
sog
metal line
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金善佑
金民载
辛东善
孙容宣
金正泰
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SK Hynix Inc
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant

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Abstract

本发明公开了一种形成保护膜的方法，该保护膜可减小金属布线间的寄生电容并改善它的薄弱部分，该方法包括以下步骤：形成衬底的金属布线，在包括金属布线在内的衬底上淀积氧化硅膜，在氧化硅膜上形成SOG膜，硬化SOG膜，然后在SOG膜上形成氮化硅膜。SOG膜由介电常数比氧化硅膜更低的材料形成，并由甲基-硅倍半环氧烷和氢-硅倍半环氧烷之一形成。

Description

在半导体器件中形成保护膜的方法
本发明涉及在半导体器件中形成保护膜的方法，该保护膜可减少金属布线间的寄生电容。
一般来说，半导体器件中的保护膜由氧化硅膜和氮化硅膜层叠组成，并由等离子淀积形成。保护膜可保护半导体器件不受外界环境变化的影响。然而，由于氧化硅膜(介电常数k＝4.3)和氮化硅膜(介电常数k＝6～8)具有高的介电常数，如果金属宽度和金属布线间的间隔小于1μm，那么布线间的寄生电容则快速增加，以致产生信号的相互干扰和信号传递延时特性。因此，器件的工作特性变坏。
由布线间的寄生电容造成的器件特性变坏大多发生在高速工作的器件中。此外，形成保护膜后，由于对应于金属布线的高度和金属布线间的间距的台阶覆盖变差，在金属布线的较低部分产生薄弱部分，因此降低了器件的可靠性。
图1A为其内形成金属布线的器件剖面图，图1B为图1A中金属布线间的寄生电容的等效电路图。金属布线12形成在衬底11上，此时，由于金属布线12之间存在介电常数为1的空气，所以金属布线12之间的寄生电容可以认为是理想寄生电容。
图2A为其内形成常规保护膜的器件剖面图。氧化硅膜23和氮化硅膜24形成在包括金属布线22在内的衬底21上。
图2B为图2A中金属布线间的寄生电容的等效电路图。金属布线22之间的寄生电容正比于金属布线和介电常数，并且反比于金属布线间的距离。因此，由于氧化膜23具有高介电常数(k＝4.3)并且氮化膜24具有高介电常数(k＝8)，所以金属布线间的寄生电容增加，因此产生相互干扰。特别是，施加驱动电压的电路周围的外围电路受到很大影响。此外，如图2A所示，在金属布线22的下部氧化膜23和氮化膜24的厚度较薄，产生薄弱部分W，因而保护膜的特性退化。
因此，本发明的目的是提供一种形成保护膜的方法，该保护膜可减小金属布线间的寄生电容并改善其薄弱部分。
为达此目的，形成保护膜的方法包括以下步骤：形成衬底的金属布线；在包括所述金属布线在内的所述衬底上淀积氧化硅膜；在所述氧化硅膜上形成具有低介电常数的硅倍半环氧烷基SOG膜，所述SOG膜由介电常数等于或小于3.0并且比所述氧化硅膜更低的材料形成；硬化所述SOG膜；以及在所述SOG膜上形成氮化硅膜作为最终的保护膜。
SOG膜由介电常数比氧化硅膜更低的材料形成，并由甲基-硅倍半环氧烷和氢-硅倍半环氧烷之一形成。
通过下面结合附图对实施例的详细介绍会理解本发明的其它目的和优点。
图1A为其内形成有金属布线的器件剖面图；
图1B为图1A中器件的等效电路图；
图2A为其内形成有常规保护膜的器件剖面图；
图2B为图2A中器件的等效电路图；
图3A为根据本发明的第一实施例形成保护膜的器件剖面图；
图3B为图3A中器件的等效电路图；
图3C为根据本发明的第二实施例形成保护膜的器件剖面图；
图4为说明现有技术和本发明中用做SOG的材料的化学结构式表；
图5为使用常规保护膜和本发明的保护膜的成品率对比图。
图3A为根据本发明的第一实施例形成保护膜的器件剖面图。
薄氧化硅膜33淀积在包括金属布线32在内的衬底31上。具有低介电常数(k＝3)的SOG(旋涂玻璃)膜34涂在氧化硅膜33上，然后硬化。氮化硅膜35淀积在SOG膜34上。当淀积SOG膜34时，旋转衬底31。因此，由于SOG的流动性，SOG膜34的表面平面化，并且SOG膜34中不存在空隙。即，SOG膜34的密度变得更高。
为了挥发掉涂敷的SOG膜34中的油性材料，在90到400℃的温度下对涂敷的SOG膜34进行焙烘工艺。此时，可根据油性材料和SOG的特性改变温度。在400到500℃的温度下进行硬化工艺，以稳固涂敷的SOG膜34的化学键。此外，在SOG膜34上形成氧化硅膜，以使SOG膜34不吸收潮气，并提高器件的可靠性。
氮化硅膜35用做最后的保护膜，并均匀地淀积在具有良好平面特性的SOG膜34上。然而，如图3A所示，由于SOG膜34的流动性，在垂直方向没有不产生拓扑结构(topology)，因此未产生氮化硅膜35的薄弱部分。由于存在氮化硅膜35，使得保护半导体器件不受诸如外部压力和潮气的侵入等的外界环境影响的能力增强。
图3B为图3A中器件的等效电路图。与图2B相比可以看出，由于使用具有低介电常数(k＝3)的SOG膜34和具有高介电常数(k＝4.3)的氧化膜33，金属布线间的寄生电容比现有技术得到很大改善。
图3C为根据本发明的第二实施例形成保护膜的器件剖面图。
薄氧化硅膜43淀积在包括金属布线42在内的衬底41上。具有低介电常数(k＝3)的SOG膜44涂在硅氧化膜43上，然后硬化。之后，对SOG膜44进行干法腐蚀，以便露出形成在金属布线42上的氧化硅膜43。
可以看出，形成在SOG膜44上的氮化硅膜45更平面化，并能防止潮气进入SOG膜44中。
当然，金属布线42之间的寄生电容与图3B所示的金属布线32之间的寄生电容相同。
图4表明了现有技术和本发明中用做SOG的材料的化学结构式。
在本发明中，使用一种烃置换型SOG的甲基-硅倍半环氧烷或一种氢置换型SOG的氢-硅倍半环氧烷作为低介电SOG。本发明中使用的SOG的介电常数(k)为3或更低，而甲基硅氧烷类和硅酸盐类的介电常数(k)为3.8或更高。通过甲基(methyl radical)或氢化改善常规的硅-氧原子之间的强极化特性，得到烃置换型SOG和氢置换型SOG。
根据金属布线的高度和金属布线间的间隔，在不同的条件下进行低介电SOG的涂层工艺。
图5为当形成常规保护膜和根据本发明分别由介电常数为3.8或更高的硅氧烷和硅酸盐结构的SOG形成的第一保护膜和由介电常数为3或更低的甲基-硅倍半氧烷或氢-硅倍半氧烷形成的第二保护膜时的成品率的对比图。
从图5中可知，当形成根据本发明的保护膜时，成品率比常规的保护膜增加了约2.25倍。
在本发明中，如上所述，用于形成保护膜并具有低介电常数的SOG具有优良的平面化和填充特性，因此可得到稳定的保护膜。由于SOG具有低介电常数，金属布线间的寄生电容可以最小化，因此器件的可靠性增强。
虽然介绍的优选实施例具有一定程度的特殊性，但以上说明仅介绍了本发明的原则。应该理解本发明并不限于这里公开并介绍的优选实施例。因此，在本发明的范围和精神内做出的所有变形都包括在本发明的其它实施例中。

Claims (8)

1.在半导体器件中形成保护膜的方法，包括以下步骤：
形成衬底的金属布线；
在包括所述金属布线在内的所述衬底上淀积氧化硅膜；
在所述氧化硅膜上形成具有低介电常数的硅倍半环氧烷基SOG膜，所述SOG膜由介电常数等于或小于3.0并且比所述氧化硅膜更低的材料形成；
硬化所述SOG膜；以及
在所述SOG膜上形成氮化硅膜作为最终的保护膜。
2.根据权利要求1的方法，其中在进行硬化步骤之前，在90到400℃的温度下干燥所述SOG膜。
3.根据权利要求1的方法，其中在400到500℃的温度下硬化所述SOG膜。
4.根据权利要求1的方法，其中所述SOG膜由甲基-硅倍半环氧烷和氢-硅倍半环氧烷之一形成。
5.根据权利要求1的方法，还包括在硬化所述SOG膜的步骤之后执行腐蚀所述SOG膜的部分的步骤。
6.根据权利要求5的方法，其中在进行硬化步骤之前，在90到400℃的温度下干燥所述SOG膜。
7.根据权利要求5的方法，其中在400到500℃的温度下硬化所述SOG膜。
8.根据权利要求5的方法，其中所述SOG膜由甲基-硅倍半环氧烷和氢-硅倍半环氧烷之一形成。
CN97125706A 1996-12-28 1997-12-25 在半导体器件中形成保护膜的方法 Expired - Fee Related CN1113398C (zh)

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GB2358734A (en) * 1999-08-30 2001-08-01 Lucent Technologies Inc Process for fabricating integrated circuit with multi-layer dielectric having reduced capacitance
GB2358733A (en) * 1999-08-30 2001-08-01 Lucent Technologies Inc Integrated circuit with multi-layer dielectric having reduced capacitance
CN100444331C (zh) * 2003-11-11 2008-12-17 三星电子株式会社 旋涂玻璃组合物和在半导体制造工序中使用该旋涂玻璃形成氧化硅层的方法
JP2008502165A (ja) 2004-06-08 2008-01-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ ｌｏｗ−ｋスピンオン誘電体膜におけるクラッキングの減少

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WO1987002828A1 (en) * 1985-11-04 1987-05-07 Motorola, Inc. Glass intermetal dielectric
US5374833A (en) * 1990-03-05 1994-12-20 Vlsi Technology, Inc. Structure for suppression of field inversion caused by charge build-up in the dielectric
US5057897A (en) * 1990-03-05 1991-10-15 Vlsi Technology, Inc. Charge neutralization using silicon-enriched oxide layer
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