CN111211057A - 显示装置及其制造方法 - Google Patents

显示装置及其制造方法 Download PDF

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CN111211057A
CN111211057A CN201911148619.6A CN201911148619A CN111211057A CN 111211057 A CN111211057 A CN 111211057A CN 201911148619 A CN201911148619 A CN 201911148619A CN 111211057 A CN111211057 A CN 111211057A
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active pattern
silicon layer
region
layer
channel region
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梁泰勋
金基范
白种埈
苏炳洙
李宗璨
郑雄喜
郑在祐
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Samsung Display Co Ltd
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Abstract

公开了显示装置及其制造方法。显示装置包括基础衬底、有源图案和栅电极，位于基础衬底上的有源图案包括源区、漏区和掺杂在源区与漏区之间的沟道区，沟道区包括晶体硅，并且栅电极与有源图案的沟道区重叠。沟道区可包括下部、上部和位于上部与下部之间的中间部，并且下部的掺杂剂密度可为上部的掺杂剂密度的80％或更多。

Description

显示装置及其制造方法
技术领域
示例实施方式涉及显示装置和显示装置的制造方法。
背景技术
近来，已制造出重量轻且尺寸小的显示装置。阴极射线管(CRT)显示装置已经因性能和有竞争力的价格而被使用。然而，CRT显示装置具有尺寸或便携性的弱点。因此，诸如等离子显示装置、液晶显示装置和有机发光显示装置的显示装置已经因尺寸小、重量轻和功耗低而备受推崇。
发明内容
实施方式涉及显示装置，包括基础衬底、有源图案和栅电极，位于基础衬底上的有源图案包括源区、漏区和掺杂在源区与漏区之间的沟道区，沟道区包括晶体硅，并且栅电极与有源图案的沟道区重叠。沟道区可包括下部、上部和位于上部与下部之间的中间部，并且下部的掺杂剂密度可为上部的掺杂剂密度的80％或更多。
上部可为有源图案的1/3厚度，并且下部可为有源图案的1/3厚度。
有源图案的沟道区的掺杂剂可包括硼、磷、氮、镍和钴中的一种或更多种。
有源图案的沟道区的平均粒度可为270nm或更大。
根据有源图案的沟道区的电子背散射衍射结果，(001)方向的分数可为33％或更大。
显示装置还可包括栅极绝缘层、层间绝缘层、源电极和漏电极，栅极绝缘层位于有源图案与栅电极之间，层间绝缘层位于栅电极上，并且源电极和漏电极位于层间绝缘层上并且电连接到有源图案。
显示装置还可包括通孔绝缘层、第一电极、发光层和第二电极，通孔绝缘层位于源电极和漏电极上，第一电极位于通孔绝缘层上并且电连接到漏电极，发光层位于第一电极上，并且第二电极位于发光层上。
实施方式也涉及显示装置的制造方法，该方法包括：在基础衬底上形成非晶硅层；用杂质掺杂非晶硅层；通过用准分子激光器照射掺杂的非晶硅层来形成晶体硅层；对晶体硅层进行图案化；以及在晶体硅层中形成源区和漏区，以形成包括源区、漏区和位于源区与漏区之间的沟道区的有源图案。沟道区可包括下部、上部和位于上部与下部之间的中间部，并且下部的掺杂剂密度可为上部的掺杂剂密度的80％或更多。
在掺杂非晶硅层时，有源图案的沟道区的掺杂剂可包括硼、磷、氮、镍和钴中的一种或更多种。
在掺杂非晶硅层时，掺杂剂的剂量可为0.4E12 at/cm2至1.5E12 at/cm2。
晶体硅层可满足下式1：
<式1>
Y＝-0.075X+1.018nm
其中，Y是单位为纳米的在掺杂剂的量的最大峰值处距晶体硅层的上表面的深度，并且X是单位为J/cm2的准分子激光器的激光密度。
在形成有源图案时，掺杂的晶体硅层的源区和漏区还可掺杂有杂质以增加源区和漏区的导电性。
在形成有源图案时用于形成源区和漏区的剂量可大于在掺杂非晶硅层时的剂量。
有源图案的沟道区的平均粒度可为270nm或更大。
根据有源图案的沟道区的电子背散射衍射结果，(001)方向的分数可为33％或更大。
该方法还可包括：在对晶体硅层进行图案化之后，在图案化的晶体硅层上形成栅极绝缘层；以及在栅极绝缘层上形成栅电极。在形成有源图案时，杂质可掺杂到布置有栅电极的晶体硅层中以形成源区和漏区。
该方法还可包括：在栅电极上形成中间绝缘层；在中间绝缘层上形成电连接到有源图案的源电极和漏电极；在源电极和漏电极上形成通孔绝缘层；在通孔绝缘层上形成电连接到漏电极的第一电极；在第一电极上形成发光层；以及在发光层上形成第二电极。
该方法还可包括对有源图案执行热处理。
附图说明
通过参考附图对示例实施方式进行详细描述，特征将对本领域技术人员变得显而易见，在附图中：
图1示出了根据示例实施方式的显示装置的剖面图；
图2示出了根据沟道掺杂顺序和沟道掺杂量的薄膜晶体管的I-V曲线的曲线图；
图3A和图3B示出了根据沟道掺杂顺序和沟道掺杂量的薄膜晶体管的滞后的曲线图；
图4示出了根据准分子激光退火(ELA)工艺的激光能量的取决于有源图案的深度的掺杂剂密度的变化的曲线图；
图5示出了根据沟道掺杂顺序的EBSD(电子背散射衍射)结果的图；
图6A至图6H示出根据示例实施方式的显示装置的制造方法的剖面图；
图7示出了根据示例实施方式的电子设备的框图；
图8A示出了图7的电子设备被实现为电视机的示例的图；以及
图8B示出了图7的电子设备被实现为智能电话的示例的图。
具体实施方式
现在，将在下文中参考附图对示例实施方式进行更加全面地描述；然而，它们可以以不同的形式实施，并且不应被解释为受限于本文中所记载的实施方式。相反，提供这些实施方式以使得本公开将是彻底和完整的，并且将向本领域技术人员全面地传达示例实现方式。在附图中，为了清楚地示出，层和区的尺寸可被放大。在整个说明书中，相同的附图标记指示相同的元件。
图1是示出根据示例实施方式的显示装置的剖面图。
参照图1，显示装置可包括基础衬底100、缓冲层110、有源图案ACT、栅极绝缘层120、栅电极GE、层间绝缘层130、源电极SE、通孔绝缘层140、发光结构180、像素限定层PDL和薄膜封装层TFE。
基础衬底100可包括透明或不透明的绝缘材料。例如，基础衬底100可包括石英衬底、合成石英衬底、氟化钙衬底、氟化物掺杂的石英衬底、钠钙玻璃衬底、无碱玻璃衬底等。在另一实现方式中，基础衬底100可包括柔性透明材料，诸如柔性透明树脂衬底，例如，聚酰亚胺衬底。在这种情况下，聚酰亚胺衬底可包括第一聚酰亚胺层、阻挡膜层、第二聚酰亚胺层等。例如，聚酰亚胺衬底可具有第一聚酰亚胺层、阻挡膜层和第二聚酰亚胺层堆叠在刚性玻璃衬底上的配置。
缓冲层110可布置在基础衬底100上。缓冲层110可布置在整个基础衬底100上。缓冲层110可防止金属原子和/或杂质从基础衬底100扩散到有源图案ACT中。另外，缓冲层110可控制用于形成有源图案ACT的结晶工艺中的热传递速率，而这可有助于提供基本上均匀的有源图案ACT。另外，当基础衬底100的表面不均匀时，缓冲层110可改善基础衬底100的表面的平坦度。
有源图案ACT可布置在缓冲层110上。有源图案ACT可包括多晶硅。有源图案ACT可包括掺杂有杂质的漏区D和源区S以及位于漏区D与源区S之间的沟道区CH。
杂质也可掺杂在沟道区CH中(沟道掺杂)，并且杂质可包括硼(B)、磷(P)、氮(N)、镍(Ni)、钴(Co)和氟(F)中的至少一种。在本示例实施方式中，例示了杂质为硼的情况。沟道区CH可包括与缓冲层110相邻的下部10、与栅极绝缘层120相邻的上部30以及位于下部10与上部30之间的中间部20。
当掺杂剂为硼时，掺杂剂的密度可能不会根据从有源图案ACT的顶表面的深度而快速地变化，但是可相对缓慢地变化。因此，掺杂剂可均匀地分布在有源图案ACT的整个沟道区CH中。
在本示例实施方式中，下部10的掺杂剂密度可为上部30的掺杂剂密度的80％或更高。上部30的厚度可为有源图案ACT的总厚度的约1/3。下部10的厚度可为有源图案ACT的总厚度的约1/3。
通常，在执行沟道掺杂的有源图案的沟道区中，掺杂剂密度布置成与有源图案的表面(该有源图案的上表面)相邻地集中，并且掺杂剂密度随着更靠近有源图案的下表面而快速地减少。
另一方面，根据本示例实施方式，根据预掺杂，从有源图案ACT的上表面到下表面，沟道区CH的掺杂剂被基本上均匀地分布，而这将在下面描述。因此，即使在少量沟道掺杂的情况下，也可获得Vth的足够的正移位，可增大驱动范围(DR范围)，并且可减小亚阈值摆幅(SS)和漏极引起的势垒降低(DIBL)。
栅极绝缘层120可覆盖位于缓冲层110上的有源图案ACT，并且可布置成沿着有源图案ACT的轮廓具有基本上相同的厚度。栅极绝缘层120可包括无机绝缘材料，诸如硅化合物或金属氧化物。
栅电极GE可布置在栅极绝缘层120上以与有源图案ACT的沟道区CH重叠。栅电极GE可使用金属、合金、金属氮化物、导电金属氧化物、透明导电材料等形成。
层间绝缘层130可布置在布置有栅电极GE的栅极绝缘层120上。层间绝缘层130可充分地覆盖栅极绝缘层120上的栅电极GE，并且可具有基本平坦的上表面，而不会在栅电极GE周围形成台阶。层间绝缘层130可包括无机绝缘材料，诸如硅化合物或金属氧化物。
源电极SE和漏电极DE可布置在层间绝缘层130上。源电极SE和漏电极DE可通过分别穿过层间绝缘层130和栅极绝缘层120形成的接触孔连接到薄膜晶体管TFT的源区S和漏区D。将参考图2至图5对薄膜晶体管TFT的特性进行详细描述。
有源图案ACT、栅电极GE、源电极SE和漏电极DE可包括在薄膜晶体管TFT中。薄膜晶体管TFT可为向作为发光结构的有机发光二极管(OLED)提供驱动电流的驱动晶体管。
通孔绝缘层140可布置在布置有源电极SE和漏电极DE的层间绝缘层130上。通孔绝缘层140可具有单层结构，或者可具有包括至少两个绝缘层的多层结构。通孔绝缘层140可使用诸如光致抗蚀剂、丙烯酸树脂、聚酰亚胺树脂、聚酰胺树脂或硅氧烷基树脂的有机材料来形成。
发光结构180可包括第一电极181、发光层182和第二电极183。
第一电极181可布置在通孔绝缘层140上。根据显示装置的发射类型，第一电极181可包括反射材料或透射材料。在示例实施方式中，第一电极181可具有可包括金属膜、合金膜、金属氮化物膜、导电金属氧化物膜和/或透明导电膜的单层结构或多层结构。
像素限定层PDL可布置在布置有第一电极181的通孔绝缘层140上。像素限定层PDL可使用有机材料形成。例如，像素限定层PDL可包括光刻胶、丙烯酸基树脂、聚酰亚胺基树脂、聚酰胺基树脂、硅氧烷基树脂等。在示例实施方式中，可通过蚀刻像素限定层PDL来形成暴露第一电极181的开口。显示装置的发射区域和非发射区域可通过像素限定层PDL的开口来限定。例如，定位有像素限定层PDL的开口的部分可对应于发射区域，并且非发射区域可对应于与像素限定层PDL的开口相邻的部分。
发光层182可布置在通过像素限定层PDL的开口暴露的第一电极181上。另外，发光层182可在像素限定层PDL的开口的侧壁上延伸。在示例实施方式中，发光层182可包括有机发光层(EL)、空穴注入层(HIL)、空穴传输层(HTL)、电子传输层(ETL)、电子注入层(EIL)等。在示例实施方式中，除了有机发光层之外，空穴注入层、空穴传输层、电子传输层和电子注入层可公共地形成为对应于多个像素。在示例实施方式中，多个有机发光层可使用根据显示装置的彩色像素而生成不同颜色的光(诸如红色光、绿色光和蓝色光)的发光材料形成。在示例实施方式中，发光层182的有机发光层可包括用于生成红色光、绿色光和蓝色光的多个堆叠的发光材料，从而发射白色光。此处，发光层182的元件可公共地形成为对应于多个像素，并且每个像素可由滤色器层划分。
第二电极183可布置在像素限定层PDL和发光层182上。根据显示装置的发射类型，第二电极183可包括透射材料或反射材料。在示例实施方式中，第二电极183也可具有可包括金属膜、合金膜、金属氮化物膜、导电金属氧化物膜和/或透明导电膜的单层结构或多层结构。
薄膜封装层TFE可布置在第二电极183上。薄膜封装层TFE可防止湿气和氧气从外部渗透。薄膜封装层TFE可包括至少一个有机层和至少一个无机层。至少一个有机层和至少一个无机层可彼此交替地堆叠。例如，薄膜封装层TFE可包括两个无机层和位于它们之间的一个有机层。在示例实施方式中，可提供用于屏蔽外部空气和湿气以免渗透到显示装置中的密封衬底，而不是薄膜封装层TFE。
图2是示出根据示例实施方式的显示装置的剖面图。
附图中的横轴是输入到薄膜晶体管的栅电极的栅极电压(Vgs)，纵轴是在薄膜晶体管的沟道区中流动的源-漏电流(Ids)。
如附图中所示，在栅极电压Vgs为负的区中，流经薄膜晶体管的源-漏电流Ids与其大小成比例。因此，通过控制栅极电压Vgs，可控制从电源线输入到第一电极的电流或输入到有机发光二极管的电流，并因此，可控制图像的显示。
在图2中示出了六种情况下的薄膜晶体管的I-V曲线。与当执行后结晶化(POST，后掺杂)时相比，当掺杂非晶硅并使其结晶化(PRE，预掺杂)时，Vth(阈值电压)移位到正极方向(右侧)。可看出，随着杂质的剂量增加(4E11、1E12、1.5E12)，Vth移位到正极方向(右侧)。
此外，在预掺杂的情况下，IV曲线的斜率变得比在后掺杂的情况更缓和并且驱动范围变得更宽，以使得其适合用作有机发光显示装置的驱动晶体管。
当薄膜晶体管表现出滞后现象时，该滞后可能导致图像的残像(重影)。当薄膜晶体管表现出滞后时，在将栅极电压Vgs从低电压改变为高电压期间测量源-漏电流Ids的曲线与在将栅极电压Vgs从高电压改变为低电压期间测量源-漏电流Ids的曲线是彼此不一致的。
在这种情况下，当显示灰屏时，栅极电压Vgs从低电压改变为高电压期间的源-漏电流Ids的值大于栅极电压Vgs从高电压改变为低电压期间的源-漏电流Ids的值。相应地，可能根据前一帧的显示图像而导致诸如残像的显示品质问题。
例如，当施加黑色/白色图案10秒，且然后施加48灰度(低灰度)图案时，出现亮度差，并且亮度差随时间而减小。此时，可通过测量亮度差达到0.4％的时间来确认残像的程度(单位：秒)。
图3A和图3B是根据沟道掺杂顺序和沟道掺杂量的薄膜晶体管的滞后的曲线图。
图3A和图3B示出了在未掺杂薄膜晶体管的沟道区的情况(跳过(SKIP))以及预掺杂(PRE，即，在准分子激光退火(ELA)工艺之前进行掺杂)和后掺杂(POST，即，在准分子激光退火(ELA)工艺之后进行掺杂)的情况中根据剂量(0.4E12、1E12、2E12)的变化而测量的滞后(单位：V(电压))。
图3A示出了薄膜晶体管是具有4μm(微米)的沟道宽度和21.04μm的长度的PMOS晶体管的情况。图3B示出了薄膜晶体管是具有4μm的沟道宽度和4μm的长度的PMOS晶体管的情况。在这两种情况下，均可看出，与相同剂量或SKIP的后掺杂相比，预掺杂可减少滞后。
具体地，与图3A中具有1E12的剂量的后掺杂情况(POST1E12)相比，在具有0.4E12的剂量的预掺杂情况下，Vth的正移效应被最大化，而剂量被减小，并且滞后减少。
另外，可减少滞后以改善残像，而这可通过下表1确认。
[表1]
掺杂顺序 加速电压 剂量 Vth 滞后(V) 即时残像(秒)
后掺杂 10K 1.3E12 -3.23 0.219 8.6
预掺杂 15K 1.5E12 -3 0.187 7.0
图4是示出根据准分子激光退火(ELA)工艺的激光能量的取决于有源图案的深度的掺杂剂密度的变化的曲线图。
参照图4，横轴表示距有源图案的上表面的深度，并且纵轴表示作为掺杂剂的硼(B)的密度。
如图中所示，根据ELA工艺，硼掺杂剂扩散到有源图案的下部。因此，硼主要以初始掺杂状态分布在有源图案的上部，但是根据ELA工艺，硼扩散到有源图案的下部。
此时，随着ELA工艺的激光能量变高(即，注入：掺杂状态→1.95J/cm2→2.05J/cm2→2.35J/cm2)，扩散变得更好，硼的密度峰值(掺杂最大峰值)变得更深。
当制定该公式时，可获得下[式1]的结果。
[式1]
Y＝-0.075X+1.018nm
其中，Y是单位为纳米的在掺杂剂的量的最大峰值处距晶体硅层的上表面的深度，并且X是单位为J/cm2的准分子激光器的激光密度。
上式的常数可根据薄膜的性质和器件的特性而变化。
图5是示出根据沟道掺杂顺序的EBSD(电子背散射衍射)结果的图。
参照图5，示出了根据电子背散射衍射(EBSD)的色标标准三角形、在后掺杂(b)的情况下的表面取向图像以及在预掺杂(a)的情况下的表面取向图像。EBSD是一种用菊池衍射图测量样品中粒度统计分布的已知方法。
下表2示出了分别在预掺杂和后掺杂的情况下根据EBSD测量的平均粒度和(001)方向的分数(fraction)。
[表2]
平均粒度(nm) (001)分数(％)
预掺杂 285 36.5
后掺杂 256 30.7
在预掺杂的情况下，可确认，与后掺杂的情况相比，(001)方向的分数增加了10％至30％。
图6A至图6H是示出根据示例实施方式的显示装置的制造方法的剖面图。
参照图6A，可在基础衬底100上形成缓冲层110。非晶硅层(a-Si层)可形成在缓冲层110上。
参照图6B，可通过在非晶硅层(a-Si层)上提供杂质来执行掺杂工艺。作为掺杂剂的杂质可为硼(B)、磷(P)、氮(N)、镍(Ni)、钴(Co)和氟(F)中的任一种。掺杂工艺可通过注入机、喷淋、CVD、溅射等来执行。
此时，掺杂剂的剂量可为0.4E12 at/cm2至1.5E12 at/cm2。当剂量太大时，滞后可减小，但是Vth移位量可能偏离期望的范围，并且分散度可能变成大得不合适。另一方面，当剂量太小时，可能无法获得期望的效果。
参照图6C，可通过用准分子激光器照射掺杂的非晶硅层来形成晶体硅层(例如，多晶硅层(p-Si层))。
此时，准分子激光器的激光能量可在适当的范围内。当激光能量太低时，掺杂剂可能无法充分扩散，而当激光能量太高时，可能难以获得期望的薄膜晶体管特性。
参照图6D，可将多晶硅层(p-Si层)图案化为有源图案ACT。例如，可通过光刻工艺等对多晶硅层(p-Si层)进行图案化。此时，有源图案ACT可处于不形成源区和漏区并且仅执行沟道掺杂的状态。
参照图6E，可在有源图案ACT上形成栅极绝缘层120。栅电极GE可形成在栅极绝缘层120上以与有源图案ACT重叠。
参照图6F，可通过将杂质掺杂到形成有栅电极GE的有源图案ACT中来形成有源图案ACT的源区S和漏区D。相应地，源区S与漏区D之间的沟道区CH可形成为与栅电极GE重叠。
此后，可对有源图案ACT执行热处理以激活和固化有源图案ACT。
参照图6G，可在布置有栅电极GE的栅极绝缘层120上形成层间绝缘层130。可去除层间绝缘层130的一部分以形成暴露有源图案ACT的源区S和漏区D的接触孔。源电极SE和漏电极DE可形成在形成有接触孔的层间绝缘层130上。
参照图6H，可在形成有源电极SE和漏电极DE的层间绝缘层130上形成具有暴露漏电极DE的接触孔的通孔绝缘层140。第一电极181、像素限定层PDL、发光层182和第二电极183可顺序地形成在通孔绝缘层140上。薄膜封装层TFE可形成在第二电极183上。因此，可制造显示装置。各种合适的方法可用作用于形成显示装置的每种配置的方法。
根据本示例实施方式，显示装置包括有源图案ACT，有源图案ACT包括掺杂的沟道区CH。有源图案ACT通过用杂质掺杂非晶硅层，且然后用准分子激光器照射掺杂的非晶硅层来形成，从而可改善薄膜晶体管的特性。特别地，可减少薄膜晶体管的滞后，从而减少残像问题并改善显示品质。另外，可使沟道区CH的剂量小于通常的薄膜晶体管的剂量，以使得可以以小剂量来减少薄膜晶体管的特性的分散。
图7是示出根据示例实施方式的电子设备的框图。图8A是示出图7的电子设备被实现为电视机的示例的图。图8B是示出图7的电子设备被实现为智能电话的示例的图。
参照图7至图8B，电子设备500可包括处理器510、存储设备520、储存设备530、输入/输出(I/O)设备540、电源550和显示设备560。此处，显示设备560可对应于图1的显示装置。另外，电子设备500还可包括用于与视频卡、声卡、存储卡、通用串行总线(USB)设备、其它电子设备等进行通信的多个端口。在示例实施方式中，如图8A中所示，电子设备500可实现为电视机。在另一示例实施方式中，例如，如图8B中所示，电子设备500可实现为智能电话。电子设备500也可实现为蜂窝电话、视频电话、智能平板、智能表、平板电脑、汽车导航系统、电脑显示屏、膝上型电脑、头戴式显示器(HMD)等。
处理器510可执行各种计算功能。处理器510可为微处理器、中央处理单元(CPU)、应用处理器(AP)等。处理器510可经由地址总线、控制总线、数据总线等耦接到其它部件。此外，处理器510可耦接到诸如外围部件互连(PCI)总线的扩展总线。存储设备520可存储用于电子设备500的操作的数据。例如，存储设备520可包括至少一个非易失性存储设备和/或至少一个易失性存储设备，至少一个非易失性存储设备诸如可擦除可编程只读存储(EPROM)设备、电可擦除可编程只读存储(EEPROM)设备、闪速存储设备、相变随机存取存储(PRAM)设备、电阻随机存取存储(RRAM)设备、纳米浮动栅极存储(NFGM)设备、聚合物随机存取存储(PoRAM)设备、磁随机存取存储(MRAM)设备、铁电随机存取存储(FRAM)设备等，并且至少一个易失性存储设备诸如动态随机存取存储(DRAM)设备、静态随机存取存储(SRAM)设备、移动DRAM设备等。储存设备530可包括固态驱动(SSD)设备、硬盘驱动(HDD)设备、CD-ROM设备等。I/O设备540可包括输入设备和输出设备，输入设备诸如键盘、小键盘、鼠标设备、触摸板、触摸屏等，并且输出设备诸如打印机、扬声器等。电源550可为电子设备500的操作提供电力。
显示设备560可经由总线或其它通信链路耦接到其它部件。在示例实施方式中，显示设备560可包括在I/O设备540中。如上所述，显示设备560可包括具有经减小的滞后和经改善的驱动范围的薄膜晶体管作为驱动晶体管。因此，可改善显示装置的显示品质。然而，由于上面已对此进行了描述，因此其描述将不再重复。
示例实施方式可应用于有机发光显示装置和包括有机发光显示装置的各种电子设备。例如，示例实施方式可应用于移动电话、智能电话、视频电话、智能平板、智能表、平板电脑、汽车导航系统、电视机、电脑显示屏、笔记本电脑等。
通过总结和回顾，显示装置可包括薄膜晶体管。薄膜晶体管可包括有源图案，有源图案包括可为结晶化的非晶硅的晶体硅。为了改善薄膜晶体管的特性，先前已经考虑了对晶体硅的额外沟道掺杂。在有机发光显示装置中，显示品质可能受到驱动晶体管的特性的影响。
如上所述，示例实施方式涉及可提供经改善的显示品质的显示装置和显示装置的制造方法。
在权利要求书中，装置加功能条款旨在覆盖本文中所描述为执行所述功能的结构，并且不只是结构等同物，而且还包括等同结构。
本文中已公开了示例实施方式，并且尽管采用了具体术语，但是它们仅以一般和描述性意义使用和解释，而并不是为了限制的目的。在一些情况下，如本领域普通技术人员随着本申请的提交而将显而易见的是，除非另有明确指示，否则结合特定实施方式描述的特征、特性和/或元件可单独使用或者与结合其它实施方式描述的特征、特性和/或元件组合使用。相应地，本领域技术人员将理解，在不背离如所附权利要求书中所记载的示例实施方式的精神和范围的情况下，可进行形式和细节上的各种改变。

Claims (10)

1.一种显示装置的制造方法，所述方法包括：
在基础衬底上形成非晶硅层；
用杂质掺杂所述非晶硅层；
通过用准分子激光器照射掺杂的所述非晶硅层来形成晶体硅层；
对所述晶体硅层进行图案化；以及
在所述晶体硅层中形成源区和漏区，以形成包括所述源区、所述漏区和位于所述源区与所述漏区之间的沟道区的有源图案，
其中，所述沟道区包括下部、上部和位于所述上部与所述下部之间的中间部，并且所述下部的掺杂剂密度为所述上部的掺杂剂密度的80％或更多。
2.如权利要求1所述的方法，其中，在掺杂所述非晶硅层时，所述有源图案的所述沟道区的掺杂剂包括硼、磷、氮、镍和钴中的一种或更多种。
3.如权利要求2所述的方法，其中，在掺杂所述非晶硅层时，所述掺杂剂的剂量为0.4E12 at/cm2至1.5E12 at/cm2。
4.如权利要求2所述的方法，其中，所述晶体硅层满足下式1：
<式1>
Y＝-0.075X+1.018nm
其中，Y是单位为纳米的在所述掺杂剂的量的最大峰值处距所述晶体硅层的上表面的深度，并且X是单位为J/cm2的所述准分子激光器的激光密度。
5.如权利要求2所述的方法，其中，在形成所述有源图案时，掺杂的所述晶体硅层的所述源区和所述漏区还掺杂有杂质以增加所述源区和所述漏区的导电性。
6.如权利要求5所述的方法，其中，在形成所述有源图案时用于形成所述源区和所述漏区的剂量大于在掺杂所述非晶硅层时的剂量。
7.如权利要求1所述的方法，其中，所述有源图案的所述沟道区的平均粒度为270nm或更大。
8.如权利要求1所述的方法，其中，根据所述有源图案的所述沟道区的电子背散射衍射结果，(001)方向的分数为33％或更大。
9.如权利要求1所述的方法，还包括：
在对所述晶体硅层进行图案化之后，在图案化的所述晶体硅层上形成栅极绝缘层；以及
在所述栅极绝缘层上形成栅电极，
其中，在形成所述有源图案时，将杂质掺杂到布置有所述栅电极的所述晶体硅层中以形成所述源区和所述漏区。
10.一种显示装置，包括：
基础衬底；
有源图案，所述有源图案位于所述基础衬底上，包括源区、漏区和掺杂在所述源区与所述漏区之间的沟道区，所述沟道区包括晶体硅；以及
栅电极，所述栅电极与所述有源图案的所述沟道区重叠，
其中，所述沟道区包括下部、上部和位于所述上部与所述下部之间的中间部，并且所述下部的掺杂剂密度为所述上部的掺杂剂密度的80％或更多。
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