CN111106092A - 包括测试焊盘的半导体封装及其形成方法 - Google Patents

包括测试焊盘的半导体封装及其形成方法 Download PDF

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Publication number
CN111106092A
CN111106092A CN201911012964.7A CN201911012964A CN111106092A CN 111106092 A CN111106092 A CN 111106092A CN 201911012964 A CN201911012964 A CN 201911012964A CN 111106092 A CN111106092 A CN 111106092A
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semiconductor chip
pad
substrate
insulating layer
semiconductor
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CN201911012964.7A
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李赫宰
金泰勳
黄智焕
金志勳
洪志硕
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN111106092A publication Critical patent/CN111106092A/zh
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Abstract

提供一种包括测试焊盘的半导体封装及其形成方法。所述半导体封装包括：基底，包括第一接合结构；以及第一半导体芯片，包括第二接合结构，第二接合结构耦合到基底的第一接合结构，其中所述第一接合结构包括：测试焊盘；第一焊盘，电连接到测试焊盘；以及第一绝缘层，其中所述第二接合结构包括：第二焊盘，电连接到第一焊盘；以及第二绝缘层，接触第一绝缘层，且其中所述测试焊盘的至少一部分接触第二绝缘层。

Description

包括测试焊盘的半导体封装及其形成方法
[相关申请的交叉参考]
本申请主张在2018年10月26日在韩国知识产权局提出申请的韩国专利申请第10-2018-0129137号的优先权，所述韩国专利申请的公开内容全文以引用方式并入本申请。
技术领域
根据示例性实施例的设备涉及一种半导体封装，且更具体来说，涉及一种包括测试焊盘的半导体封装。
背景技术
近来，随着对高性能电子产品的需求以及对这种高性能电子产品的微型化的需求一直增加，已经开发了各种类型的半导体封装。为此，正在开发包括多个半导体芯片的半导体封装，在所述半导体封装中将个别芯片安装或堆叠在衬底或另一芯片上来减小半导体封装的厚度。
当对个别芯片进行安装或堆叠时，如果将正常芯片安装或堆叠在有缺陷的芯片上，则不仅有缺陷的芯片而且堆叠在有缺陷的芯片上的正常芯片也可能无法在半导体封装中正常工作。
发明内容
一个或多个示例性实施例提供一种包括能够检查半导体芯片的缺陷的测试焊盘的半导体封装。
根据示例性实施例的一方面，提供一种半导体封装，所述半导体封装包括：基底，包括第一接合结构；以及第一半导体芯片，包括第二接合结构，所述第二接合结构耦合到所述基底的所述第一接合结构，其中所述第一接合结构包括：测试焊盘；第一焊盘，电连接到所述测试焊盘；以及第一绝缘层，其中所述第二接合结构包括：第二焊盘，电连接到所述第一焊盘；以及第二绝缘层，接触所述第一绝缘层，且其中所述测试焊盘的至少一部分接触所述第二绝缘层。
根据另一示例性实施例的一方面，提供一种半导体封装，所述半导体封装包括：基底；以及多个半导体芯片，设置在所述基底上，其中所述多个半导体芯片包括：第一半导体芯片；以及第二半导体芯片，所述第一半导体芯片与所述第二半导体芯片依序堆叠在所述基底上且耦合到所述基底。所述第一半导体芯片包括：第一表面；以及第二表面，与所述第一表面相对。所述第二半导体芯片包括：第三表面；以及第四表面，与所述第三表面相对。所述第一半导体芯片包括第一内部电路布线，所述第一内部电路布线设置在所述第一半导体芯片的第一表面上。所述第二半导体芯片包括第二内部电路布线，所述第二内部电路布线设置在所述第二半导体芯片的所述第三表面上。所述第一半导体芯片的所述第二表面包括：第一焊盘；测试焊盘；以及第一绝缘层。所述第二半导体芯片的所述第三表面包括：第二焊盘，接触所述第一焊盘并接合到所述第一焊盘；以及第二绝缘层，接触所述第一绝缘层并接合到所述第一绝缘层。
根据另一示例性实施例的一方面，提供一种半导体封装，所述半导体封装包括：基底，具有第一表面及与所述第一表面相对的第二表面；下部半导体芯片，设置在所述基底上且具有第三表面及与所述第三表面相对的第四表面；以及上部半导体芯片，设置在所述下部半导体芯片上且具有第五表面及与所述第五表面相对的第六表面。所述基底的所述第二表面及所述下部半导体芯片的所述第四表面中的每一者包括第一接合结构。所述下部半导体芯片的所述第三表面及所述上部半导体芯片的所述第五表面中的每一者包括第二接合结构。所述第一接合结构包括：第一焊盘；测试焊盘；以及第一绝缘层，所述第二接合结构包括：第二焊盘；以及第二绝缘层。所述基底的所述第一接合结构与所述下部半导体芯片的所述第二接合结构在彼此接触的同时接合。所述下部半导体芯片的所述第一接合结构与所述上部半导体芯片的所述第二接合结构在彼此接触的同时接合。
附图说明
通过结合附图理解以下详细说明，将更清楚地理解本公开的以上和/或其他方面、特征及优点，在附图中：
图1A是示出根据示例性实施例的半导体封装的剖视图。
图1B是根据示例性实施例以分解方式示出在图1A中所示的半导体封装的基底、第一半导体芯片及第二半导体芯片的剖视图。
图2A是根据示例性实施例以分解方式示出图1A所示半导体芯片的第一接合结构及第二接合结构的透视图。
图2B是示出根据示例性实施例的图1A所示半导体芯片的第一接合结构及第二接合结构的经修改的实例的透视图。
图3是示出根据示例性实施例的半导体封装的经修改的实例的剖视图。
图4是根据示例性实施例以分解方式示出图3所示半导体芯片的第一接合结构及第二接合结构的剖视图。
图5是示出根据示例性实施例的半导体封装的经修改的实例的剖视图。
图6是根据示例性实施例以分解方式示出图5所示半导体芯片的第一接合结构及第二接合结构的剖视图。
图7是示出根据示例性实施例的半导体封装的经修改的实例的剖视图。
图8是示出根据示例性实施例的半导体封装的经修改的实例的剖视图。
图9是根据示例性实施例以分解方式示出图8所示的半导体芯片的第一接合结构及第二接合结构的剖视图。
图10是示出根据示例性实施例的半导体封装的经修改的实例的剖视图。
图11是示出根据示例性实施例的半导体封装的经修改的实例的剖视图。
图12是示出根据示例性实施例的半导体封装的经修改的实例的剖视图。
图13是示出根据示例性实施例的半导体封装的经修改的实例的剖视图。
图14A到图14D是示出根据示例性实施例的制造半导体封装的方法的视图。
[符号的说明]
1a、1b、1c、1d、1e、1f、1g、1h、1i：半导体封装
10、10a：下部结构
20：连接结构
100、100'、100a、100a'：基底
100W：晶片
105：基底主体
110：基底贯穿电极结构
128：基底内部电路
130：下部绝缘层
130'：基底下部绝缘层/基底内部电路结构
135：基底下部焊盘
135'：基底下部焊盘/基底内部电路结构
160：基底布线结构/基底背侧结构
160'：基底背侧结构
160a：下部连接结构
165：基底背侧绝缘层/基底背侧结构
175(INS1)、275(INS1)、INS1：第一绝缘层
180a(P1a)、182(P1b)、280a(P1a)、282(P1b)：第一焊盘
180b(TP)、280b(TP)、TP：测试焊盘
180c(IPa)、280c(IPa)、IPa：焊盘连接部
200：第一半导体芯片/下部半导体芯片/半导体芯片
200a、200b、200c：下部半导体芯片/半导体芯片
205：第一半导体主体
210：第一贯穿电极结构
215：第一内部电路布线/第一内部电路结构/内部电路结构
220：第一下部绝缘层/第一内部电路结构/内部电路结构
230(INS2)、330(INS2)、INS2：第二绝缘层
265：上部绝缘层
300：第二半导体芯片/半导体芯片/上部半导体芯片
305：第二半导体主体
315：第二内部电路布线/第二内部电路结构/内部电路结构
320：第二下部绝缘层/第二内部电路结构/内部电路结构
235(P2a)、235(P2b)、335(P2a)、335(P2b)、P2a、P2b：第二焊盘
400：第三半导体芯片/半导体芯片
405：第三半导体主体
415：第三内部电路布线/内部电路布线/第三内部电路结构
420：下部绝缘层/第三内部电路结构
450：模制层
460：散热结构
462：绝缘热传导层/热传导层
464：散热板
510a：载体衬底
520a：粘合层
600：锯切工艺
1000：测试设备
1010a、1010b：探针
BS：背侧
DA：虚设区域
DP：虚设焊盘区域
IPb：虚设连接部
FS：前侧
P1a：第一部分/焊盘/第一焊盘
P1b：第二部分/第一焊盘
PA：测试区域
ST1：第一接合结构
ST2：第二接合结构
Wb、Wc1、Wc2、WTP、WP：宽度
具体实施方式
下文中，将参照附图阐述本公开的示例性实施例。
首先，将参照图1A、图1B及图2A阐述根据示例性实施例的半导体封装1a的示例性实施例。图1A是示出根据示例性实施例的半导体封装的剖视图。图1B是根据示例性实施例以分解方式示出在图1A中所示的半导体封装1a的基底100、第一半导体芯片200及第二半导体芯片300的剖视图。图2A是根据示例性实施例以分解方式示出图1A及图1B所示第一接合结构ST1及第二接合结构ST2的透视图。
参照图1A及图1B，根据示例性实施例的半导体封装1a可包括基底100及位于基底100上的一个或多个半导体芯片。
在示例性实施例中，基底100可为中间层。然而，示例性实施例并非仅限于此。举例来说，基底100可为半导体芯片。
根据示例性实施例的半导体封装1a还可包括下部结构10，所述下部结构10设置在基底100下方且通过连接结构20耦合到基底100。下部结构10可为印刷电路板。连接结构20可为凸块或焊料球。
在示例性实施例中，半导体封装1a可包括：第一半导体芯片200及第二半导体芯片300，依序堆叠在基底100上；以及第三半导体芯片400，邻近第一半导体芯片200设置在基底100上，如图1A中所示。
在示例性实施例中，第一半导体芯片200、第二半导体芯片300及第三半导体芯片400可包括逻辑半导体芯片和/或存储器半导体芯片。举例来说，第一半导体芯片200及第二半导体芯片300可为存储器半导体芯片，且第三半导体芯片400可为逻辑半导体芯片。存储器半导体芯片可为易失性存储器芯片(例如，动态随机存取存储器(dynamic randomaccess memory，DRAM)或静态随机存取存储器(static random access memory，SRAM))或者非易失性存储器芯片(例如，相变随机存取存储器(phase-change random accessmemory，PRAM)、磁阻随机存取存储器(magnetoresistive random access memory，MRAM)、铁电随机存取存储器(ferroelectric random access memory，FeRAM)、电阻式随机存取存储器(resistive random access memory，RRAM)或闪存)。逻辑半导体芯片可为微处理器、模拟装置或数字信号处理器。
基底100以及第一半导体芯片200、第二半导体芯片300及第三半导体芯片400可通过包含第一接合结构ST1与第二接合结构ST2而耦合。举例来说，基底100及第一半导体芯片200可包括位于基底100及第一半导体芯片200中的每一者的顶表面上的第一接合结构ST1，且第一半导体芯片200、第二半导体芯片300及第三半导体芯片400可包括位于第一半导体芯片200、第二半导体芯片300及第三半导体芯片400中的每一者的底表面上的第二接合结构ST2。如图1B中所示，基底100的第一接合结构ST1耦合到第一半导体芯片200的第二接合结构ST2，且第一半导体芯片200的第一接合结构ST1耦合到第二半导体芯片300的第二接合结构ST2。另外，基底100的宽度Wb大于第一半导体芯片、第二半导体芯片及第三半导体芯片中的每一者的宽度Wc1、Wc2。
第一接合结构ST1可包括第一焊盘P1a及P1b、测试焊盘TP以及第一绝缘层INS1。第二接合结构ST2可包括第二焊盘P2a及P2b以及第二绝缘层INS2。
在示例性实施例中，第一焊盘P1a及P1b的第一部分P1a可通过焊盘连接部IPa电连接到测试焊盘TP，且第一焊盘P1a及P1b的第二部分P1b可与测试焊盘TP间隔开，如图2A中所示。另外，测试焊盘TP中的每一者的宽度WTP大于第一焊盘P1a及P1b中的每一者的宽度WP。
当第一接合结构ST1与第二接合结构ST2彼此耦合时，第一焊盘P1a及P1b与第二焊盘P2a及P2b可彼此直接接触。第一焊盘P1a及P1b与第二焊盘P2a及P2b可包含相同的导电材料，例如铜(Cu)。在面对彼此的同时彼此直接接触的第一焊盘P1a及P1b与第二焊盘P2a及P2b可通过铜的相互扩散而耦合。
在示例性实施例中，能够形成第一焊盘P1a及P1b以及第二焊盘P2a及P2b的导电材料可不仅限于铜，而是可包含能够相互彼此耦合的任何材料。举例来说，能够形成第一焊盘P1a及P1b以及第二焊盘P2a及P2b的导电材料可包括金(Au)。
当第一接合结构ST1与第二接合结构ST2彼此耦合时，第一接合结构ST1的第一绝缘层INS1与第二接合结构ST2的第二绝缘层INS2可在面对彼此的同时彼此直接接触。第一绝缘层INS1与第二绝缘层INS2可由相同的材料形成。举例来说，第一绝缘层INS1及第二绝缘层INS2可由氧化硅(SiO2)形成。第一绝缘层INS1与第二绝缘层INS2可在彼此直接接触的同时彼此耦合。
在示例性实施例中，第一绝缘层INS1及第二绝缘层INS2可不仅限于氧化硅(SiO2)，且可包含能够相互彼此耦合的所有材料。举例来说，第一绝缘层INS1及第二绝缘层INS2可由氮碳化硅(SiCN)形成。
返回参照图1A及图1B，基底100可包括：基底主体105；下部绝缘层130及基底下部焊盘135，设置在基底主体105下方；基底背侧结构165及160，设置在基底主体105上；第一接合结构ST1，设置在基底背侧结构160及165上；以及基底贯穿电极结构110，穿透过基底主体105。基底主体105可为半导体衬底。举例来说，基底主体105可为硅衬底。
基底100的第一接合结构ST1可包括第一焊盘180a(P1a)及182(P1b)、焊盘连接部180c(IPa)、测试焊盘180b(TP)以及第一绝缘层175(INS1)。
基底背侧结构160及165可包括：基底背侧绝缘层165；以及基底布线结构160，设置在基底背侧绝缘层165中且电连接基底100的基底贯穿电极结构110与第一焊盘180a(P1a)及182(P1b)。基底贯穿电极结构110可电连接到基底下部焊盘135。因此，基底100的第一焊盘180a(P1a)及182(P1b)可通过基底贯穿电极结构110电连接到基底下部焊盘135。基底贯穿电极结构110可为硅通孔(through-silicon via，TSV)结构。基底布线结构160可电连接到测试焊盘180b(TP)。举例来说，基底布线结构160可通过第一焊盘P1b及连接部IPa电连接到测试焊盘180b(TP)。
第一半导体芯片200可包括：第一半导体主体205；上部绝缘层265，设置在第一半导体主体205上；第一接合结构ST1，设置在上部绝缘层265上；第一内部电路结构215及220，设置在第一半导体主体205下方；第二接合结构ST2，设置在第一内部电路结构215及220下方；以及第一贯穿电极结构210，穿透过第一半导体主体205。第一贯穿电极结构210可为硅通孔(TSV)结构。第一半导体主体205可为半导体衬底，例如硅衬底。
第一半导体芯片200的第一接合结构ST1可包括第一焊盘280a(P1a)及282(P1b)、焊盘连接部280c(IPa)、测试焊盘280b(TP)以及第一绝缘层275(INS1)。第一半导体芯片200的第一焊盘280a(P1a)及282(P1b)可电连接到第一贯穿电极结构210。第一半导体芯片200的第二接合结构ST2可包括第二焊盘235(P2a及P2b)以及第二绝缘层230(INS2)。
第一半导体芯片200的第一内部电路结构215及220可包括第一内部电路布线215，所述第一内部电路布线215设置在第一下部绝缘层220中且电连接到第一半导体芯片200的第一贯穿电极结构210及第一焊盘280a(P1a)及282(P1b)。第一内部电路结构215及220可设置在第一半导体芯片200的第二接合结构ST2与第一半导体主体205之间。
第二半导体芯片300可包括：第二半导体主体305；第二内部电路结构315及320，设置在第二半导体主体305下方；以及第二接合结构ST2，设置在第二内部电路结构315及320下方。第二半导体主体305可为半导体衬底，例如硅衬底。第二半导体芯片300的第二接合结构ST2可包括第二焊盘335(P2a及P2b)以及第二绝缘层330(INS2)。
第二半导体芯片300的第二内部电路结构315及320可包括：第二下部绝缘层320；以及第二内部电路布线315，设置在第二下部绝缘层320中且电连接到第二半导体芯片300的第二焊盘335(P2a及P2b)。第二内部电路结构315及320可设置在第二半导体芯片300的第二接合结构ST2与第二半导体主体305之间。
第三半导体芯片400可包括第三半导体主体405；第三内部电路结构415及420，设置在第三半导体主体405下方；第二焊盘P2b，设置在第三内部电路结构415及420下方且构成如上所述的第二接合结构ST2；以及第二绝缘层INS2。第三内部电路结构415及420可包括：下部绝缘层420；以及第三内部电路布线415，位于下部绝缘层420中。第三内部电路结构415及420可设置在第三半导体芯片400的第二接合结构ST2与第三半导体主体405之间。
基底100与第一半导体芯片200可通过对基底100的第一接合结构ST1与第一半导体芯片200的第二接合结构ST2进行接合而耦合。举例来说，基底100的第一焊盘180a(P1a)及182(P1b)与第一半导体芯片200的第二焊盘235(P2a及P2b)可在彼此接触的同时接合并耦合，且基底100的第一绝缘层175(INS1)与第一半导体芯片200的第二绝缘层230(INS2)可在彼此接触的同时接合并耦合。
基底100及第三半导体芯片400可在基底100的第一焊盘182(P1b)与第三半导体芯片400的第二焊盘P2b彼此接触的同时接合并耦合，且可在基底100的第一绝缘层175(INS1)与第三半导体芯片400的第二绝缘层INS2彼此接触的同时接合并耦合。
第一半导体芯片200与第二半导体芯片300可在第一半导体芯片200的第一接合结构ST1与第二半导体芯片300的第二接合结构ST2接合的同时耦合。举例来说，第一半导体芯片200的第一焊盘280a(P1a)及282(P1b)与第二半导体芯片300的第二焊盘335(P2a及P2b)可在彼此接触的同时接合并耦合，且第一半导体芯片200的第一绝缘层275(INS1)与第二半导体芯片300的第二绝缘层330(INS2)可在彼此接触的同时接合并耦合。
第一半导体芯片200及第二半导体芯片300中的每一者可具有彼此相对的前侧FS与背侧BS。第一半导体芯片200的前侧FS可接触基底100并接合到基底100，且第一半导体芯片200的背侧BS可接触第二半导体芯片300的前侧FS并接合到第二半导体芯片300的前侧FS。
在一些实施例中，第一半导体芯片200的前侧FS可被称为第一表面，第一半导体芯片200的背侧BS可被称为第二表面，第二半导体芯片300的前侧FS可被称为第三表面，且第二半导体芯片300的背侧BS可被称为第四表面。
在一些实施例中，基底100a可包括第一表面及与第一表面相对的第二表面，第一半导体芯片200的前侧FS可被称为第三表面，第一半导体芯片200的背侧BS可被称为第四表面，第二半导体芯片300的前侧FS可被称为第五表面，且第二半导体芯片300的背侧BS可被称为第六表面。
在一些实施例中，第一半导体芯片200的第一接合结构ST1可被称为第三接合结构，第二半导体芯片200的第二接合结构ST2可被称为第四接合结构。
第一焊盘P1a及P1b中的每一者可小于测试焊盘TP中的每一者。
在示例性实施例中，当在平面图中观察时，第一及第二焊盘P1a、P1b、P2a及P2b中的每一者可具有多边形形状。举例来说，当在平面图中观察时，第一及第二焊盘P1a、P1b、P2a及P2b中的每一者可具有矩形形状。
在经修改的实例中，参照图2B，当在平面图中观察时，第一及第二焊盘P1a、P1b、P2a及P2b中的每一者可具有圆形形状。
接着，参照图3到图10，将阐述半导体封装1b、1c、1d、1e及1f的各种经修改的实例。图3及图4是示出根据示例性实施例的半导体封装1b的经修改的实例的视图。图5及图6是示出根据示例性实施例的半导体封装1c的另一经修改的实例的视图。图7是示出根据示例性实施例的半导体封装1d的另一经修改的实例的视图。图8及图9是示出根据示例性实施例的半导体封装1e的另一经修改的实例的视图，且图10是示出根据示例性实施例的半导体封装1f的另一经修改的实例的视图。
参照图3及图4，第二接合结构ST2还可包括虚设连接部IPb，虚设连接部IPb设置在与第一接合结构ST1的焊盘连接部IPa对应的位置处且接触第一接合结构ST1并接合到第一接合结构ST1。虚设连接部IPb可由与焊盘连接部IPa相同的材料形成。虚设连接部IPb可从第二焊盘P2a及P2b的第二焊盘P2a的一部分延伸。第一半导体芯片200可包括虚设连接部IPb，虚设连接部IPb接触基底100的焊盘连接部IPa并接合到基底100的焊盘连接部IPa，且第二半导体芯片300可包括虚设连接部IPb，虚设连接部IPb接触第一半导体芯片200的焊盘连接部IPa并接合到第一半导体芯片200的焊盘连接部IPa。因此，可提供还包括虚设连接部IPb的半导体封装1b，所述虚设连接部IPb接触焊盘连接部IPa并接合到焊盘连接部IPa。
在经修改的实例中，参照图5及图6，第一接合结构ST1的测试焊盘TP可包括：测试区域PA，直接接触图14A、图14B及图14C的用于检查缺陷的探针1010a及1010b；以及虚设区域DA，环绕测试区域PA。第二接合结构ST2可设置在与第一接合结构ST1的焊盘连接部IPa对应的位置，且还可包括：虚设连接部IPb，接触第一接合结构ST1的焊盘连接部IPa并接合到第一接合结构ST1的焊盘连接部IPa；以及虚设焊盘区域DP，接触第一接合结构ST1的测试焊盘TP的虚设区域DA并接合到第一接合结构ST1的测试焊盘TP的虚设区域DA。测试区域PA可接触第二接合结构ST2的第二绝缘层INS2。
虚设连接部IPb及虚设焊盘区域DP可由与焊盘连接部IPa及测试焊盘TP相同的材料形成。虚设连接部IPb可从第二焊盘P2a及P2b中的第二焊盘P2a的一部分延伸，且虚设焊盘区域DP可从虚设连接部IPb延伸。
第一半导体芯片200还可包括：虚设连接部IPb，接触基底100的焊盘连接部IPa并接合到基底100的焊盘连接部IPa；以及虚设焊盘区域DP，接触基底100的测试焊盘TP的一部分(即虚设区域DA)并接合到基底100的测试焊盘TP的所述一部分(即虚设区域DA)，且第二半导体芯片300还可包括：虚设连接部IPb，接触第一半导体芯片200的焊盘连接部IPa并接合到第一半导体芯片200的焊盘连接部IPa；以及虚设焊盘区域DP，接触第一半导体芯片200的测试焊盘TP的一部分(即虚设区域DA)并接合到第一半导体芯片200的测试焊盘TP的所述一部分(即虚设区域DA)。因此，可提供还包括虚设连接部IPb及虚设焊盘区域DP的半导体封装1c。
在经修改的实例中，参照图7，在同一平面中，基底100的测试焊盘TP可与基底100的第一焊盘P1a及P1b间隔开。第一焊盘P1a及P1b中的一些焊盘P1a可通过基底布线结构160的下部连接结构160a电连接到基底100的测试焊盘TP。下部连接结构160a可设置在基底100的测试焊盘TP及第一焊盘P1a及P1b下方。因此，可提供包括在同一平面中彼此间隔开的基底100的测试焊盘TP与基底100的第一焊盘P1a及P1b的半导体封装1d。
在经修改的实例中，参照图8及图9，基底100的第一焊盘P1a及P1b中的某些焊盘P1a可通过下部连接结构160a电连接到测试焊盘TP，如图7中所示。第一接合结构ST1的测试焊盘TP可包括虚设区域DA及测试区域PA，如参照图6所述。第一半导体芯片200及第二半导体芯片300中的每一者的第二接合结构ST2可包括：虚设焊盘区域DP，与第二焊盘P2a及P2b间隔开、接触第一接合结构ST1的测试焊盘TP的虚设区域DA并接合到第一接合结构ST1的测试焊盘TP的虚设区域DA。因此，可提供包括虚设焊盘区域DP的半导体封装1e。
在经修改的实例中，参照图10，半导体封装1f可包括基底100'，基底100'可为半导体芯片。举例来说，基底100'可包括：基底主体105；基底内部电路128，设置在基底主体105下方；以及基底下部焊盘135'，设置在基底内部电路128下方。基底内部电路128可设置在设置在基底主体105下方的基底下部绝缘层130'中。
如上所述的第一半导体芯片200、第二半导体芯片300及第三半导体芯片400可设置在基底100'上。基底100'与第一半导体芯片200、第二半导体芯片300及第三半导体芯片400可经由如上所述的彼此接触并接合的第一接合结构ST1与第二接合结构ST2而耦合。由于以上已阐述了第一接合结构ST1及第二接合结构ST2，因此此处将省略其详细说明。
接着，将参照图11阐述根据示例性实施例的半导体封装的另一经修改的实例。图11是示出根据示例性实施例的半导体封装1g的经修改的实例的剖视图。
参照图11，半导体芯片1g可包括：下部结构10a；基底100a，设置在下部结构10a上；以及多个半导体芯片200a、200b、200c及300，堆叠在基底100a上。半导体封装1g还可包括模制层450，模制层450形成在基底100a上且环绕所述多个半导体芯片200(200a、200b及200c)以及300。
所述多个半导体芯片200(200a、200b及200c)以及300可包括依序堆叠的下部半导体芯片200(200a、200b及200c)以及设置在下部半导体芯片200上的上部半导体芯片300。
在示例性实施例中，下部结构10a可为印刷电路板或半导体芯片。
在示例性实施例中，基底100a可为半导体芯片或中间层。下部结构10a与基底100a可经由在下部结构10a与基底100a之间延伸的连接结构20电连接到彼此。
下部半导体芯片200(200a、200b及200c)中的每一者可包括第一接合结构ST1及第二接合结构ST2，所述第一接合结构ST1及第二接合结构ST2与以上所述的第一接合结构ST1及第二接合结构ST2实质上相同。
下部半导体芯片200(200a、200b及200c)中的每一者可具有与图1A及图1B中阐述的第一半导体芯片200的结构相同的结构。因此，下部半导体芯片200中的每一者可为图1A及图1B中阐述的第一半导体芯片200。举例来说，如在图1A及图1B中阐述的第一半导体芯片200，下部半导体芯片200中的每一者可包括：第一半导体主体205；第二接合结构ST2，设置在第一半导体主体205下方；内部电路结构215及220，设置在第二接合结构ST2与第一半导体主体205之间；第一接合结构ST1，设置在第一半导体主体205上；上部绝缘层265，设置在第一接合结构ST1与第一半导体主体205之间；以及第一贯穿电极结构210，穿透过第一半导体主体205。
在示例性实施例中，上部半导体芯片300可与图1A及图1B中阐述的第二半导体芯片300相同。因此，上部半导体芯片300可包括：第二半导体主体305，例如图1A及图1B中阐述的第二半导体芯片300；内部电路结构315及320，设置在第二半导体主体305下方；以及第二接合结构ST2设置在内部电路结构315及320下方。
相似于以上在图1A及图1B中阐述的基底100，基底100a可包括：基底主体105；下部绝缘层130及基底下部焊盘135，设置在基底主体105下方；基底背侧结构160'及165，设置在基底主体105上；第一接合结构ST1，设置在基底背侧结构160'及165上；以及基底贯穿电极结构110，穿透过基底主体105。
由于已参照图1A及图1B阐述了彼此接触并接合的第一接合结构ST1与第二接合结构ST2，因此将省略第一接合结构ST1及第二接合结构ST2的说明。
接着，将参照图12阐述根据示例性实施例的半导体封装1h的经修改的实例。图12是示出根据示例性实施例的半导体封装1h的经修改的实例的剖视图。
在经修改的实例中，参照图12，半导体封装1h可包括：下部结构10a，如图11中所述；基底100a，设置在下部结构10a上；以及多个半导体芯片200(200a、200b及200c)及300，堆叠在基底100a上。半导体封装1h还可包括模制层450，模制层450形成在基底100a上且环绕所述多个半导体芯片200及300的侧表面。
半导体封装1h还可包括散热结构460，散热结构460覆盖所述多个半导体芯片200及300的上部部分。散热结构460可包括绝缘热传导层462以及位于热传导层462上的散热板464。
接着，将参照图13阐述根据示例性实施例的半导体封装1i的经修改的实例。图13是示出根据示例性实施例的半导体封装1i的经修改的实例的剖视图。
在经修改的实例中，参照图13，半导体封装1i可包括基底100a'，基底100a'包括基底内部电路结构130'及135'。相似于图10中阐述的基底100'，基底100a'可包括：基底主体105；基底内部电路128，设置在基底主体105下方；以及基底下部焊盘135'，设置在基底内部电路128下方。基底内部电路128可设置在位于基底主体105下方的基底下部绝缘层130'中。
如上所述，基底100a'可包括：基底背侧结构160'及165，设置在基底主体105上；第一接合结构ST1，设置在基底背侧结构160'及165上；以及基底贯穿电极结构110，穿透过基底主体105。因此，基底100a'可为包括基底内部电路128的半导体芯片。
半导体封装1i可被理解成与参照图11及图12的半导体封装1g及半导体封装1h相似的结构，但图11及图12中阐述的基底100a除外。
接着，将参照图14A到图14D阐述根据示例性实施例的制造半导体封装的方法的示例性实施例。
参照图14A，可将晶片100W贴合到载体衬底510a。可通过设置在载体衬底510a上的粘合层520a将晶片100W贴合到载体衬底510a。
晶片100W可包括：基底主体105；下部绝缘层130及基底下部焊盘135，设置在基底主体105下方；基底背侧结构165及160，位于基底主体105上；第一接合结构，位于基底背侧结构160及165上；以及基底贯穿电极结构110，穿透过基底主体105。基底背侧结构160及165可包括设置在基底背侧绝缘层165中的基底背侧布线结构160。基底主体105可为半导体晶片，例如硅晶片。也就是说，基底主体105可为半导体衬底，例如硅衬底。
如参照图1A及图1B所述，第一接合结构可包括第一焊盘P1a及P1b、焊盘连接部IPa、测试焊盘TP以及第一绝缘层INS1。由于已参照图1A及图1B阐述了第一焊盘P1a及P1b、焊盘连接部IPa、测试焊盘TP以及第一绝缘层INS1，因此此处将省略其详细说明。
可在晶片100W的基底下部焊盘135下方形成连接结构20。连接结构20可嵌入粘合层520a中。
可使用测试设备1000来检查晶片100W的缺陷。举例来说，通过使测试设备1000的探针1010a及1010b接触不同的测试焊盘TP，可通过测量基底布线结构160的电短路或基底布线结构160的泄漏电流来检查晶片100W。
参照图14B，如上所述，当作为晶片100W的缺陷检查的结果确定晶片100W表现为正常状态(即，没有任何缺陷)时，可将半导体芯片400耦合到晶片100W的一部分。半导体芯片400可为参照图1A及图1B阐述的第三半导体芯片400。因此，第三半导体芯片400可包括：第三半导体主体405；内部电路结构415及420，设置在第三半导体主体405下方；第二焊盘P2b，设置在内部电路结构415及420下方；以及第二绝缘层INS2。内部电路结构415及420可包括下部绝缘层420以及设置在下部绝缘层420中的内部电路布线415。
可将第三半导体芯片400放置在晶片100W上，且可在高于室温的热气氛(thermalatmosphere)(例如，约200℃到约300℃)中向第三半导体芯片400施加压力。因此，晶片100W的第一焊盘P1b与第三半导体芯片400的第二焊盘P2b可彼此接合并耦合，且晶片100W的第一绝缘层INS1与第三半导体芯片400的第二绝缘层INS2可彼此接合并耦合。此处，热气氛的温度可不限于约200℃到约300℃，而是可根据设计意图而变化。当嵌入粘合层520a中的连接结构20是焊料球时，粘合层520a可防止连接结构20因热气氛而变形。
可使用测试设备1000以与以上参照图14A所阐述的相同的方式来检查第三半导体芯片400的缺陷。举例来说，通过使测试设备1000的探针1010a及1010b接触晶片100W的不同测试焊盘TP，可测量第三半导体芯片400的内部电路布线的电短路或泄漏电流，从而可检查第三半导体芯片400。
参照图14C，当作为第三半导体芯片400的缺陷检查的结果，第三半导体芯片400在正常状态下工作时，可在此后将第一半导体芯片200(如图1A及图1B中所述)耦合到晶片100W。
第一半导体芯片200可包括第一接合结构(图1B的ST1)及第二接合结构(图1B的ST2)，例如图1A及图1B中所述的第一接合结构及第二接合结构。第一半导体芯片200的图1B所示第一接合结构ST1可在接触晶片100W的同时进行接合。第一半导体芯片200的第二接合结构(图1B的ST2)可包括第二焊盘P2a及P2b以及第二绝缘层INS2，如参照图1A、图1B、图2A及图2B所述。第一半导体芯片200的第一接合结构(图1B的ST1)可包括第一焊盘P1a及P1b、测试焊盘TP以及第一绝缘层INS1，如参照图1A、图1B、图2A及图2B所述。
可将第一半导体芯片200放置在晶片100W上，且可在温度高于室温的热气氛中向第一半导体芯片200施加压力。因此，晶片100W的第一焊盘P1a及P1b与第一半导体芯片200的第二焊盘P2a及P2b可彼此接合并耦合，且晶片100W的第一绝缘层INS1与第一半导体芯片200的第二绝缘层INS2可彼此接合并耦合。此处，热气氛的温度可不限于约200℃到约300℃，而是可不同地进行改变。当嵌入粘合层520a中的连接结构20是焊料球时，粘合层520a可防止连接结构20因热气氛而变形。
然后，可使用测试设备1000以与上述相同的方式检查第一半导体芯片200的缺陷。举例来说，通过使测试设备1000的探针1010a及1010b接触第一半导体芯片200的测试焊盘TP，可测量第一半导体芯片200的内部电路布线(图1B的215)的电短路或泄漏电流，从而可检查第一半导体芯片200。
参照图14D，当作为第一半导体芯片200的缺陷检查的结果，第一半导体芯片200在正常状态下工作时，可将第二半导体芯片300(如图1A及图1B中所述)耦合到第一半导体芯片200。第二半导体芯片300到第一半导体芯片200的耦合可与第一半导体芯片200到晶片100W的耦合实质上相同。
然后，可通过锯切工艺600来切割晶片100W，且然后可将所切割的晶片100W从粘合层520a分离。因此，可如图1A及图1B中所述形成半导体封装1a。当半导体封装1a还包括如图1A及图1B中所述的下部结构10时，所述方法还可包括在将所切割的晶片100W从粘合层520a分离之后，可将所分离的晶片100W安装在下部结构10上。
在另一实例中，为了形成图11中阐述的半导体封装1g，可执行如图14A中所示的对晶片100W进行的缺陷检查，且然后如图14C中所示可重复执行第一半导体芯片200的形成及第一半导体芯片200的缺陷检查，且然后可形成如图14D中阐述的第二半导体芯片300。然后，可形成如图11中阐述的模制层(图11的450)，且可执行对模制层(图11的450)及晶片100W进行切割的锯切工艺600。
根据示例性实施例，可提供一种半导体封装，所述半导体封装包括：彼此接触并接合的第一接合结构ST1的第一焊盘P1a及P1b与第二接合结构ST2的第二焊盘P2a及P2b；以及彼此接触并接合的第一接合结构ST1的第一绝缘层INS1与第二接合结构ST2的第二绝缘层INS2。半导体封装的厚度可微型化。这种半导体封装可通过彼此接触并耦合的第一焊盘P1a及P1b与第二焊盘P2a及P2b更高效地向外释放芯片中的热量。可提供一种具有改善的散热特性(heat dissipation characteristic)的半导体封装。
根据示例性实施例，可提供一种包括测试焊盘TP的半导体封装。由于在最终形成半导体封装之前可通过测试焊盘TP核查半导体封装中的芯片是否有缺陷，因而可提高半导体封装的生产率。
如上所述，根据示例性实施例，可提供一种半导体封装，所述半导体封装包括：焊盘，在彼此接触的同时彼此接合；以及芯片，包括在彼此接触的同时彼此耦合的绝缘层。半导体封装的厚度可减小，从而可将半导体封装微型化。这种半导体封装可通过在彼此接触的同时彼此耦合的焊盘高效地向外释放芯片中的热量。因此，可提供具有改善的散热特性(heat dissipation characteristic)的半导体封装。
根据示例性实施例，可提供一种包括测试焊盘的半导体封装。由于在最终形成半导体封装之前可通过测试焊盘TP检查半导体封装中的芯片是否有缺陷，因此可提高半导体封装的生产率。
尽管以上已示出并阐述了示例性实施例，然而对于所属领域中的技术人员而言将显而易见的是，在不背离如随附权利要求所界定的本发明概念的范围的条件下，可作出各种润饰及变化。

Claims (23)

1.一种半导体封装，包括：
基底，包括第一接合结构；以及
第一半导体芯片，包括第二接合结构，所述第二接合结构耦合到所述基底的所述第一接合结构，
其中所述第一接合结构包括：
测试焊盘；
第一焊盘，电连接到所述测试焊盘；以及
第一绝缘层，
其中所述第二接合结构包括：
第二焊盘，电连接到所述第一焊盘；以及
第二绝缘层，接触所述第一绝缘层，且
其中所述测试焊盘的至少一部分接触所述第二绝缘层。
2.根据权利要求1所述的半导体封装，其中所述第一接合结构还包括焊盘连接部，所述焊盘连接部将所述第一焊盘与所述测试焊盘电连接到彼此。
3.根据权利要求2所述的半导体封装，其中所述焊盘连接部的至少一部分接触所述第二绝缘层。
4.根据权利要求2所述的半导体封装，其中所述第二接合结构还包括虚设连接部，所述虚设连接部接触所述焊盘连接部。
5.根据权利要求2所述的半导体封装，其中所述第二接合结构还包括虚设焊盘部，
其中所述基底的所述测试焊盘包括：
测试区域；以及
虚设区域，环绕所述测试区域，且
其中所述第二接合结构的所述虚设焊盘部接触所述测试焊盘的所述虚设区域。
6.根据权利要求5所述的半导体封装，其中所述测试区域接触所述第一半导体芯片的所述第二绝缘层。
7.根据权利要求1所述的半导体封装，其中所述基底包括：
基底主体；
贯穿电极结构，穿透过所述基底主体；以及
基底背侧结构，设置在所述基底主体上，
其中所述基底的所述第一接合结构设置在所述基底背侧结构上，且
其中所述基底背侧结构包括电连接到所述测试焊盘的基底布线结构。
8.根据权利要求7所述的半导体封装，其中所述基底主体包括硅衬底。
9.根据权利要求1所述的半导体封装，其中所述基底包括中间层。
10.根据权利要求1所述的半导体封装，其中所述基底包括与所述第一半导体芯片不同的半导体芯片。
11.根据权利要求1所述的半导体封装，其中所述测试焊盘具有比所述第一焊盘的宽度大的宽度。
12.根据权利要求1所述的半导体封装，还包括：
下部结构，设置在所述基底下方；以及
连接结构，设置在所述基底与所述下部结构之间。
13.一种半导体封装，包括：
基底；以及
多个半导体芯片，设置在所述基底上，
其中所述多个半导体芯片包括：
第一半导体芯片；以及
第二半导体芯片，所述第一半导体芯片与所述第二半导体芯片依序堆叠在所述基底上且耦合到所述基底，
其中所述第一半导体芯片包括：
第一表面；以及
第二表面，与所述第一表面相对，
其中所述第二半导体芯片包括：
第三表面；以及
第四表面，与所述第三表面相对，
其中所述第一半导体芯片包括第一半导体主体及第一内部电路布线，
其中所述第二半导体芯片包括第二半导体主体及第二内部电路布线，
其中所述第一内部电路布线位于所述第一半导体主体与所述第一表面之间，
其中所述第二内部电路布线位于所述第二半导体主体与所述第三表面之间，
其中所述第一半导体芯片的所述第二表面包括：
第一焊盘；
测试焊盘；以及
第一绝缘层，且
其中所述第二半导体芯片的所述第三表面包括：
第二焊盘，接触所述第一焊盘并接合到所述第一焊盘；以及
第二绝缘层，接触所述第一绝缘层并接合到所述第一绝缘层。
14.根据权利要求13所述的半导体封装，其中所述测试焊盘的至少一部分接触所述第二绝缘层。
15.根据权利要求13所述的半导体封装，其中所述基底具有第一宽度，所述第一宽度大于所述多个半导体芯片中的每一者的第二宽度。
16.一种半导体封装，包括：
基底，具有第一表面及与所述第一表面相对的第二表面；
下部半导体芯片，设置在所述基底上且具有第三表面及与所述第三表面相对的第四表面；以及
上部半导体芯片，设置在所述下部半导体芯片上且具有第五表面及与所述第五表面相对的第六表面，
其中：
所述基底的所述第二表面及所述下部半导体芯片的所述第四表面中的每一者包括第一接合结构，
所述下部半导体芯片的所述第三表面及所述上部半导体芯片的所述第五表面中的每一者包括第二接合结构，
所述第一接合结构包括：
第一焊盘；
测试焊盘；以及
第一绝缘层，
所述第二接合结构包括：
第二焊盘；以及
第二绝缘层，
所述基底的所述第一接合结构与所述下部半导体芯片的所述第二接合结构在彼此接触的同时接合，且
所述下部半导体芯片的所述第一接合结构与所述上部半导体芯片的所述第二接合结构在彼此接触的同时接合。
17.根据权利要求16所述的半导体封装，其中所述第一焊盘及所述第二焊盘中的每一者包含导电材料。
18.根据权利要求16所述的半导体封装，其中：
所述基底的所述第一接合结构的所述第一焊盘与所述下部半导体芯片的所述第二接合结构的所述第二焊盘在彼此接触的同时接合，且
所述基底的所述第一接合结构的所述测试焊盘的至少一部分接触所述下部半导体芯片的所述第二接合结构的所述第二绝缘层。
19.根据权利要求16所述的半导体封装，其中：
所述下部半导体芯片的所述第一接合结构的所述第一焊盘与所述上部半导体芯片的所述第二接合结构的所述第二焊盘在彼此接触的同时接合，且
所述下部半导体芯片的所述第一接合结构的所述测试焊盘的至少一部分接触所述上部半导体芯片的所述第二接合结构的所述第二绝缘层。
20.根据权利要求16所述的半导体封装，其中所述下部半导体芯片还包括设置在所述第三表面与所述第四表面之间的贯穿电极结构。
21.一种形成半导体封装的方法，包括：
形成晶片，所述晶片包括第一焊盘、测试焊盘及第一绝缘层；
通过所述晶片的所述测试焊盘来检查所述晶片的缺陷；
将包括测试焊盘的第一半导体芯片耦合到所述晶片；
通过所述第一半导体芯片的所述测试焊盘来执行所述第一半导体芯片的缺陷检查；
将第二半导体芯片耦合到所述第一半导体芯片；以及
切割所述晶片。
22.根据权利要求21所述的形成半导体封装的方法，其中所述第一半导体芯片包括第二焊盘及第二绝缘层，所述第二焊盘接触所述第一焊盘并耦合到所述第一焊盘，所述第二绝缘层接触所述第一绝缘层并耦合到所述第一绝缘层。
23.根据权利要求22所述的形成半导体封装的方法，其中所述晶片的所述测试焊盘中的每一者接触所述第一半导体芯片的所述第二绝缘层。
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