CN113035800A - 半导体封装件 - Google Patents
半导体封装件 Download PDFInfo
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- CN113035800A CN113035800A CN202011032950.4A CN202011032950A CN113035800A CN 113035800 A CN113035800 A CN 113035800A CN 202011032950 A CN202011032950 A CN 202011032950A CN 113035800 A CN113035800 A CN 113035800A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 449
- 239000000758 substrate Substances 0.000 claims abstract description 235
- 238000000465 moulding Methods 0.000 claims description 57
- 230000017525 heat dissipation Effects 0.000 claims description 18
- 238000009413 insulation Methods 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 136
- 238000000034 method Methods 0.000 description 30
- 230000004888 barrier function Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 230000008054 signal transmission Effects 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000012778 molding material Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000011572 manganese Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002071 nanotube Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- Engineering & Computer Science (AREA)
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
一种半导体封装件包括:封装基板;下半导体器件,所述下半导体器件布置在所述封装基板上并包括第一贯通电极;第一下连接凸块,所述第一下连接凸块布置在所述封装基板与所述下半导体器件之间,并将所述封装基板电连接到所述第一贯通电极;连接基板,所述连接基板布置在所述封装基板上并包括第二贯通电极;第二下连接凸块,所述第二下连接凸块布置在所述封装基板与所述连接基板之间,并将所述封装基板电连接到所述第二贯通电极;以及上半导体器件,所述上半导体器件布置在所述下半导体器件上,并电连接到所述第一贯通电极和所述第二贯通电极。
Description
相关申请的交叉引用
本申请要求于2019年12月24日在韩国知识产权局提交的韩国专利申请No.10-2019-0174286的优先权,其公开内容通过引用整体合并于此。
技术领域
与本公开一致的设备、器件、方法和制造物品涉及半导体封装件,并且更具体地,涉及具有改善的散热特性的半导体封装件。
背景技术
通常,通过对半导体芯片执行封装工艺来形成半导体封装件,半导体芯片是通过对晶片执行各种半导体工艺来形成的。近来,已经将各种半导体芯片封装在一个半导体封装件中,并且半导体芯片彼此电连接,从而电连接的半导体芯片作为系统而运行。当半导体芯片运行时,可能产生过多的热,因此,半导体封装件的性能会劣化。
发明内容
一方面在于提供一种具有改善的散热特性的半导体封装件。
根据示例性实施例的一方面,提供了一种半导体封装件,所述半导体封装件包括:封装基板;下半导体器件,所述下半导体器件布置在所述封装基板上并包括多个第一贯通电极;多个第一下连接凸块,所述多个第一下连接凸块布置在所述封装基板与所述下半导体器件之间,并将所述封装基板电连接到所述多个第一贯通电极;连接基板,所述连接基板布置在所述封装基板上并包括多个第二贯通电极;多个第二下连接凸块,所述多个第二下连接凸块布置在所述封装基板与所述连接基板之间,并将所述封装基板电连接到所述多个第二贯通电极;以及上半导体器件,所述上半导体器件布置在所述下半导体器件上,并电连接到所述多个第一贯通电极和所述多个第二贯通电极。
根据示例性实施例的另一方面,提供了一种半导体封装件,所述半导体封装件包括:下半导体器件,所述下半导体器件包括多个第一贯通电极;连接基板,所述连接基板包括多个第二贯通电极;上半导体器件,所述上半导体器件堆叠在所述下半导体器件的上表面和所述连接基板的上表面上,所述上半导体器件电连接到所述多个第一贯通电极并电连接到所述多个第二贯通电极;以及再分布结构,所述再分布结构布置在所述下半导体器件的下表面和所述连接基板的下表面上,所述再分布结构电连接到所述多个第一贯通电极并电连接到所述多个第二贯通电极。
根据示例性实施例的又一方面,提供了一种半导体封装件,所述半导体封装件包括:封装基板;存储芯片,所述存储芯片布置在所述封装基板上并包括多个第一贯通电极;连接基板,所述连接基板布置在所述封装基板上并包括多个第二贯通电极,所述多个第二贯通电极中的每个第二贯通电极的第二宽度大于所述多个第一贯通电极中的每个第一贯通电极的第一宽度;逻辑芯片,所述逻辑芯片布置在所述存储芯片的上表面和所述连接基板的上表面上,所述逻辑芯片电连接到所述多个第一贯通电极和所述多个第二贯通电极;散热构件,所述散热构件位于所述逻辑芯片上;再分布结构,所述再分布结构布置在所述存储芯片的下表面和所述连接基板的下表面上,所述再分布结构包括分别电连接到所述多个第一贯通电极的多个第一下凸块焊盘,并包括分别电连接到所述多个第二贯通电极的多个第二下凸块焊盘;多个第一下连接凸块,所述多个第一下连接凸块位于所述多个第一下凸块焊盘与所述封装基板之间;以及多个第二下连接凸块,所述多个第二下连接凸块位于所述多个第二下凸块焊盘与所述封装基板之间。所述存储芯片包括:第一基板,所述第一基板包括面对所述逻辑芯片的第一表面和与所述第一表面相对的第二表面;以及第一半导体器件层,所述第一半导体器件层位于所述第一基板的所述第一表面上。所述逻辑芯片包括:第二基板,所述第二基板包括面对所述存储芯片的第三表面和与所述第三表面相对的第四表面;以及第二半导体器件层,所述第二半导体器件层位于所述第二基板的所述第三表面上,其中,所述逻辑芯片的平面面积大于所述存储芯片的平面面积与所述连接基板的平面面积之和。
附图说明
根据下面结合附图进行的详细描述,将更清楚地理解这些和其他方面,在附图中:
图1是示出了根据各种示例性实施例的半导体封装件的截面图;
图2是示出了图1中示出的半导体封装件的区域II的放大截面图;
图3是示出了图1中示出的半导体封装件的区域III的放大截面图;
图4是示出了图1中示出的半导体封装件的区域IV的放大截面图;
图5是示出了图1中示出的半导体封装件的区域V的放大截面图;
图6A至图6C是示出了根据各种示例性实施例的半导体封装件中的下半导体器件和连接基板的示例性布图的俯视图;
图7是示出了根据示例性实施例的半导体封装件的截面图;
图8是示出了根据示例性实施例的半导体封装件的截面图;
图9是示出了根据示例性实施例的半导体封装件的截面图;
图10是示出了根据示例性实施例的半导体封装件的截面图;
图11是示出了根据示例性实施例的半导体封装件的截面图;
图12是示出了根据示例性实施例的半导体封装件的截面图;
图13是示出了根据示例性实施例的半导体封装件的截面图;
图14A至图14M是示出了根据示例性实施例的制造半导体封装件的方法的截面图;以及
图15A至图15C是示出了根据示例性实施例的制造半导体封装件的方法的截面图。
具体实施方式
在下文中,将参照附图详细地描述各种示例性实施例。同样的附图标记始终指代同样的元件,并且为了简洁起见,将省略先前给出的描述。
图1是示出了根据各种示例性实施例的半导体封装件10的截面图。图2是示出了图1中的区域II的放大截面图。图3是示出了图1中的区域III的放大截面图。图4是示出了图1中的区域IV的放大截面图。图5是示出了图1中的区域V的放大截面图。
参照图1至图5,半导体封装件10可以包括下半导体器件110、上半导体器件120、连接基板130、第一模塑层163和第一再分布结构140。
上半导体器件120可以堆叠在下半导体器件110上。上半导体器件120的平面面积(或占地面积)可以大于下半导体器件110的平面面积(或占地面积)。从上方看,下半导体器件110可以布置为在竖直方向(例如,Z方向)上与上半导体器件120交叠。参见例如图6A至图6C。
另外,上半导体器件120可以堆叠在连接基板130上,连接基板130在水平方向(例如,图1中示出的示例中的X方向)上与下半导体器件110间隔开。上半导体器件120的平面面积可以大于下半导体器件110的平面面积与连接基板130的平面面积之和。从上方看,下半导体器件110和连接基板130可以布置为在竖直方向上与上半导体器件120交叠。
在一些示例性实施例中,当电力信号被供应到下半导体器件110和上半导体器件120时,上半导体器件120产生的热量可能大于由下半导体器件110产生的热量。为了在上半导体器件120上进行散热,在一些示例性实施例中,诸如散热器的散热构件(例如,参照图12的180)可以布置在上半导体器件120上,和/或在其他示例性实施例中,上半导体器件120的表面的至少一部分可以暴露于外部。
在示例性实施例中,下半导体器件110可以包括存储芯片。例如,下半导体器件110可以包括易失性存储芯片和/或非易失性存储芯片。易失性存储芯片可以为例如动态随机存取存储器(DRAM)、高带宽存储器(HBM)DRAM、静态RAM(SRAM)、晶闸管RAM(TRAM)、零电容RAM(ZRAM)或双晶体管RAM(TTRAM)。另外,非易失性存储芯片可以为例如闪存、磁性RAM(MRAM)、自旋扭矩MRAM(STT-MRAM)、铁电RAM(FRAM)、相变RAM(PRAM)、电阻RAM(RRAM)、纳米管RRAM、聚合物RAM或绝缘体相变存储器。
在示例性实施例中,上半导体器件120可以包括逻辑芯片。上半导体器件120可以包括中央处理单元(CPU)芯片、图形处理单元(GPU)芯片或应用处理器(AP)芯片。例如,上半导体器件120可以包括用于控制下半导体器件110的控制芯片。
下半导体器件110可以包括第一半导体基板111、第一半导体器件层113、第一贯通电极115、第一上凸块焊盘117和第一背面保护层119。
第一半导体基板111可以包括彼此相对的第一表面111F和第二表面111B。第一半导体基板111的第一表面111F可以是第一半导体基板111的有源表面,并且第一半导体基板111的第二表面111B可以是第一半导体基板111的无源表面。在示例性实施例中,下半导体器件110可以布置为使得第一半导体基板111的第一表面111F面对上半导体器件120。
在一些示例性实施例中,第一半导体基板111可以包括例如硅(Si)。或者,在一些示例性实施例中,第一半导体基板111可以包括例如诸如锗(Ge)的半导体元素,或者诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)或磷化铟(InP)的化合物半导体。或者,在一些示例性实施例中,第一半导体基板111可以具有绝缘体上硅(SOI)结构。例如,第一半导体基板111可以包括掩埋氧化物(BOX)层。第一半导体基板111可以包括导电区域,例如,掺杂有杂质的阱或掺杂有杂质的结构。另外,第一半导体基板111可以具有各种器件隔离结构,例如浅沟槽隔离(STI)结构。
第一半导体器件层113形成在第一半导体基板111的第一表面111F上,并可以包括前道工艺(FEOL)结构和后道工艺(BEOL)结构。
例如,第一半导体器件层113可以包括多个各种类型的单独的器件和层间绝缘层。多个各种类型的单独的器件可以包括各种微电子器件,例如,诸如互补金属绝缘体半导体(CMOS)晶体管的金属氧化物半导体场效应晶体管(MOSFET)、诸如系统大规模集成(LSI)或CMOS成像传感器(CIS)的图像传感器、微机电系统(MEMS)、有源元件和无源元件。
例如,第一半导体器件层113可以包括用于将多个单独的器件连接到形成在第一半导体基板111上的其他布线的布线结构。布线结构可以包括形成在绝缘层1135中的金属布线层1131和通路插塞1133。金属布线层1131和通路插塞1133可以包括布线势垒层和布线金属层。布线势垒层可以包括从Ti、TiN、Ta或TaN中选择的至少一种材料。布线金属层可以包括从钨(W)、铝(Al)或铜(Cu)中选择的至少一种金属。金属布线层1131和通路插塞1133可以由相同的材料形成。或者,在一些示例性实施例中,金属布线层1131和通路插塞1133的至少一部分可以包括不同的材料。
第一贯通电极115可以穿过第一半导体基板111。第一贯通电极115可以用于外部装置与下半导体器件110之间的信号传输,例如,输入/输出数据信号和电力信号的传输。第一贯通电极115可以用于外部装置与上半导体器件120之间的信号传输,例如,输入/输出数据信号和电力信号的传输。
每个第一贯通电极115可以包括第一芯导电材料1151、第一势垒层1153和第一通路介电层1155。
第一芯导电材料1511可以包括例如铝(Al)、金(Au)、铍(Be)、铋(Bi)、钴(Co)、铜(Cu)、铪(Hf)、铟(In)、镁(Mg)、锰(Mn)、钼(Mo)、镍(Ni)、铅(Pb)、钯(Pd)、铂(Pt)、铑(Rh)、铼(Re)、钌(Ru)、锡(Sn)、钽(Ta)、碲(Te)、钛(Ti)、钨(W)、锌(Zn)和锆(Zr)中的一种或更多种。
第一势垒层1153可以接触并围绕第一芯导电材料1151的侧表面。第一势垒层1153可以包括具有低布线电阻的导电层。例如,第一势垒层1153可以包括单层或多层,该单层或多层包括W、WN、WC、Ti、TiN、Ta、TaN、Ru、Co、Mn、WN、Ni或NiB中的至少一种。例如,第一势垒层1153可以包括由TaN/W、TiN/W或WN/W形成的多层。第一势垒层1153可以通过化学气相沉积(CVD)或物理气相沉积(PVD)来形成。
第一通路介电层1155可以围绕第一势垒层1153的侧表面,并可以使第一芯导电材料1151与第一半导体基板111绝缘。第一通路介电层1155可以包括氧化物层、氮化物层、碳化物层、聚合物层或以上材料的组合。第一通路介电层1155可以通过CVD来形成。
图1和图2示出了第一贯通电极115从下半导体器件110的下表面110LS延伸到第一半导体基板111的第一表面111F。然而,示例性实施例不限于此。例如,在一些示例性实施例中,一部分第一贯通电极115可以进一步延伸到第一半导体器件层113的内部或可以穿过第一半导体器件层113。
第一上凸块焊盘117可以布置在第一半导体器件层113上。第一上凸块焊盘117可以分别电连接到第一贯通电极115。例如,第一上凸块焊盘117可以通过第一半导体器件层113中的布线结构电连接到第一贯通电极115。例如,第一上凸块焊盘117可以包括Al、Cu、Ni、W、Pt、Au或以上金属的组合。
第一背面保护层119可以形成在第一半导体基板111的第二表面111B上。第一背面保护层119可以围绕从第一半导体基板111的第二表面111B突出的第一贯通电极115的侧表面。第一背面保护层119可以包括例如无机绝缘层或有机绝缘层。
上半导体器件120可以包括第二半导体基板121、第二半导体器件层123、第一凸块焊盘125和第二凸块焊盘127。
第二半导体基板121可以包括彼此相对的第一表面121F和第二表面121B。第二半导体基板121的第一表面121F可以是第二半导体基板121的有源表面,并且第二半导体基板121的第二表面121B可以是第二半导体基板121的无源表面。在示例性实施例中,上半导体器件120可以布置为使得第二半导体基板121的第一表面121F面对下半导体器件110的上表面110US。因为第二半导体基板121可以与第一半导体基板111相同或类似,所以为了简洁起见,将不给出其详细描述。
第二半导体器件层123可以形成在第二半导体基板121的第一表面121F上。第二半导体器件层123可以包括FEOL结构和BEOL结构。因为第二半导体器件层123可以与第一半导体器件层113相同或类似,所以为了简洁起见,将不给出其详细描述。
第一凸块焊盘125和第二凸块焊盘127可以布置在第二半导体器件层123上。第一凸块焊盘125和第二凸块焊盘127可以电连接到第二半导体器件层123中的布线结构。第一凸块焊盘125和第二凸块焊盘127可以包括例如Al、Cu、Ni、W、Pt或Au,或者这些金属的组合。
连接基板130均可以包括基体层131、第二贯通电极133和第二上凸块焊盘135。
基体层131可以由半导体材料或绝缘材料形成。例如,基体层131可以包括Si、Ge、SiGe、GaAs、玻璃或陶瓷中的至少一种。
第二贯通电极133可以穿过基体层131。每个第二贯通电极133可以包括第二芯导电材料1331、围绕第二芯导电材料1331的侧表面的第二势垒层1333和围绕第二势垒层1333的侧表面的第二通路介电层1335。因为第二芯导电材料1331、第二势垒层1333和第二通路介电层1335可以分别与第一芯导电材料1151、第一势垒层1153和第一通路介电层1155相同或类似,所以为了简洁起见,将不给出其详细描述。
第二上凸块焊盘135可以布置在连接基板130的面对上半导体器件120的上表面130US上。第二上凸块焊盘135可以分别电连接到第二贯通电极133。例如,第二上凸块焊盘135可以包括Al、Cu、Ni、W、Pt或Au,或者这些金属的组合。
在上半导体器件120与下半导体器件110之间,可以布置用于将上半导体器件120电连接到下半导体器件110的第一上连接凸块151。第一上连接凸块151的下部可以分别附接到下半导体器件110的第一上凸块焊盘117,并且第一上连接凸块151的上部可以分别附接到上半导体器件120的第一凸块焊盘125。第一上半导体器件120可以通过第一上连接凸块151电连接到第一贯通电极115。第一上连接凸块151可以用于上半导体器件120与下半导体器件110之间或者外部装置与上半导体器件120之间的信号传输。
在上半导体器件120与连接基板130之间,可以布置用于将上半导体器件120电连接到连接基板130的第二贯通电极133的第二上连接凸块153。第二上连接凸块153的下部可以分别附接到连接基板130的第二上凸块焊盘135,并且第二上连接凸块153的上部可以分别附接到上半导体器件120的第二凸块焊盘127。第二上连接凸块153可以用于外部装置与上半导体器件120之间的信号传输。
在上半导体器件120与下半导体器件110之间以及上半导体器件120与连接基板130之间,可以布置绝缘粘附层161。绝缘粘附层161可以围绕上半导体器件120与下半导体器件110之间的第一上连接凸块151,并可以围绕上半导体器件120与连接基板130之间的第二上连接凸块153。绝缘粘附层161可以包括例如非导电膜(NCF)。
第一模塑层163可以形成在上半导体器件120的下表面120LS上,并可以模塑下半导体器件110和连接基板130。第一模塑层163可以围绕下半导体器件110的侧表面,并可以围绕连接基板130的侧表面。第一模塑层163可以接触下半导体器件110的侧表面和连接基板130的侧表面。在一些示例性实施例中,第一模塑层163可以不覆盖下半导体器件110的面对第一再分布结构140的下表面110LS和连接基板130的面对第一再分布结构140的下表面130LS。另外,第一模塑层163可以覆盖上半导体器件120的下表面120LS的一部分。第一模塑层163可以保护下半导体器件110和连接基板130免受外部环境的影响。
例如,第一模塑层163可以包括环氧基模塑树脂或聚酰亚胺基模塑树脂。在示例性实施例中,第一模塑层163可以包括环氧模塑化合物(EMC)。
第一再分布结构140可以布置在下半导体器件110的下表面110LS、连接基板130的下表面130LS和第一模塑层163的下表面上。第一再分布结构140可以包括第一再分布图案142和第一再分布绝缘层149。
第一再分布绝缘层149可以接触下半导体器件110的下表面110LS、连接基板130的下表面130LS和第一模塑层163的下表面。第一再分布绝缘层149可以使包括在第一再分布结构140中的各种组件彼此电绝缘。第一再分布绝缘层149可以包括能够在光刻工艺中使用的可光成像电介质(PID)绝缘材料。例如,第一再分布绝缘层149可以由光敏聚酰亚胺形成。或者,在一些示例性实施例中,第一再分布绝缘层149可以包括氧化硅或氮化硅。
第一再分布图案142可以使第一下连接凸块155分别电连接到下半导体器件110的第一贯通电极115,并可以使第二下连接凸块157分别连接到连接基板130的第二贯通电极133。例如,第一再分布图案142可以包括在水平方向上延伸的导电线图案141和在竖直方向上延伸的导电通路图案143。导电通路图案143可以使导电线图案141电连接到第一贯通电极115,可以使导电线图案141电连接到第二贯通电极133,可以使导电线图案141电连接到第一下连接凸块155,或可以使导电线图案141电连接到第二下连接凸块157。另外,在图1中,导电线图案141被示出为单个层。然而,在一些示例性实施例中,形成多层的多个导电线图案141可以设置在第一再分布绝缘层149中,并且导电通路图案143可以电连接在竖直方向上彼此相邻的导电线图案141。
在示例性实施例中,第一再分布图案142可以包括第一下凸块焊盘145和第二下凸块焊盘147,第一下连接凸块155分别附接到第一下凸块焊盘145,第二下连接凸块157分别附接到第二下凸块焊盘147。第一下凸块焊盘145的至少一部分和第二下凸块焊盘147的至少一部分可以从第一再分布绝缘层149的下表面突出。
在示例性实施例中,上半导体器件120可以通过连接基板130的第二贯通电极133接收上半导体器件120的运行所需的电力。更详细地讲,由外部装置提供的电力可以通过第二下连接凸块157、第一再分布结构140的第一再分布图案142、第二贯通电极133和第二上连接凸块153供应到上半导体器件120。
如图2和图3所示,每个第二贯通电极133的宽度可以大于每个第一贯通电极115的宽度。例如,在与下半导体器件110的上表面110US平行的第一方向(例如,X或Y方向)上,每个第二贯通电极133的水平宽度133W可以大于每个第一贯通电极115的水平宽度115W。在示例性实施例中,每个第二贯通电极133的水平宽度133W可以在大约10μm至大约20μm之间。在示例性实施例中,每个第一贯通电极115的水平宽度115W可以在大约1μm至大约7μm之间。
在示例性实施例中,每个第二贯通电极133的宽度可以大于每个第一贯通电极115的宽度,因此,电力可以稳定地供应到上半导体器件120。另外,因为可以通过使用廉价的工艺形成第二贯通电极133,所以可以减少半导体封装件10的生产成本。
在示例性实施例中,每个连接到第二贯通电极133的第二上连接凸块153的宽度可以不同于每个连接到第一贯通电极115的第一上连接凸块151的宽度。例如,每个连接到第二贯通电极133的第二上连接凸块153的宽度可以大于每个连接到第一贯通电极115的第一上连接凸块151的宽度。例如,在与下半导体器件110的上表面110US平行的第一方向上,每个第二上连接凸块153的最大水平宽度153W可以大于每个第一上连接凸块151的最大水平宽度151W。
在示例性实施例中,每个连接到第二上连接凸块153的第二上凸块焊盘135的宽度可以大于每个连接到第一上连接凸块151的第一上凸块焊盘117的宽度。例如,在与下半导体器件110的上表面110US平行的第一方向上,每个第二上凸块焊盘135的水平宽度135W可以大于每个第一上凸块焊盘117的水平宽度117W。另外,上半导体器件120的每个连接到第二上连接凸块153的第二凸块焊盘127的宽度可以大于上半导体器件120的每个连接到第一上连接凸块151的第一凸块焊盘125的宽度。例如,在与下半导体器件110的上表面110US平行的第一方向上,每个第二凸块焊盘127的水平宽度127W可以大于每个第一凸块焊盘125的水平宽度125W。
在示例性实施例中,每个连接到第二贯通电极133的第二下连接凸块157的宽度可以不同于每个连接到第一贯通电极115的第一下连接凸块155的宽度。如图4和图5所示,每个连接到第二贯通电极133的第二下连接凸块157的宽度可以大于每个连接到第一贯通电极115的第一下连接凸块155的宽度。例如,在与下半导体器件110的上表面110US平行的第一方向上,每个第二下连接凸块157的最大水平宽度157W可以大于每个第一下连接凸块155的最大水平宽度155W。
在示例性实施例中,每个连接到第二下连接凸块157的第二下凸块焊盘147的宽度可以不同于每个连接到第一下连接凸块155的第一下凸块焊盘145的宽度。例如,每个连接到第二下连接凸块157的第二下凸块焊盘147的宽度可以大于每个连接到第一下连接凸块155的第一下凸块焊盘145的宽度。例如,在与下半导体器件110的上表面110US平行的第一方向上,每个第二下凸块焊盘147的水平宽度147W可以大于每个第一下凸块焊盘145的水平宽度145W。
在各种示例性实施例中,当上半导体器件120是逻辑芯片并且下半导体器件110是存储芯片时,因为逻辑芯片布置在半导体封装件10的上侧处有利于放热,所以半导体封装件10的散热特性可以改善。另外,因为可以通过使用连接基板130的具有大宽度的第二贯通电极133将电力供应到逻辑芯片,所以可以将电力稳定地供应到逻辑芯片。
图6A至图6C是示出了半导体封装件10中的下半导体器件110和连接基板130的示例性布图的俯视图。
参照图6A以及图1,下半导体器件110和两个连接基板130可以布置在上半导体器件120的下表面120LS上。下半导体器件110可以布置在上半导体器件120的下表面120LS的中央,并且两个连接基板130可以通过二者之间的下半导体器件110彼此间隔开。两个连接基板130可以分别沿着下半导体器件110的两个相对的边缘延伸。在图6A中,示出了两个连接基板130布置在半导体封装件10中。然而,示例性实施例不限于此,并且在一些示例性实施例中,三个或更多个连接基板130可以设置在半导体封装件10中。
参照图6B,在上半导体器件120的下表面120LS上,布置了下半导体器件110和两个连接基板130,并且这两个连接基板130可以分别沿着下半导体器件110的两个相邻的边缘延伸。
参照图6C,在上半导体器件120的下表面120LS上,可以布置下半导体器件110和一个连接基板130。连接基板130可以沿着下半导体器件110的两个相邻的边缘延伸并且可以弯曲。例如,如图6C所示,连接基板130可以具有L形状。
图7是示出了根据各种示例性实施例的半导体封装件10a的截面图。
除了第一模塑层163暴露连接基板130a的部分侧表面之外,图7中示出的半导体封装件10a可以与图1中示出的半导体封装件10相同或类似。在下文中,将主要描述图7中示出的半导体封装件10a与图1中示出的半导体封装件10之间的区别。
参照图7,第一模塑层163可以覆盖连接基板130a的某些部分侧表面并且可以不覆盖连接基板130a的其他部分侧表面。例如,连接基板130a的与面对下半导体器件110的第一侧表面相对的第二侧表面可以不被第一模塑层163覆盖。在一些示例性实施例中,连接基板130a的第二侧表面可以与上半导体器件120的侧表面共面。
图8是示出了根据各种示例性实施例的半导体封装件10b的截面图。
除了省略了连接基板130(图1)并且下半导体器件110a包括分别与连接基板130的第二贯通电极133(图1)对应的第三贯通电极116之外,图8中示出的半导体封装件10b可以与图1中示出的半导体封装件10相同或类似。在下文中,将主要描述图8中示出的半导体封装件10b与图1中示出的半导体封装件10之间的区别。
参照图8,下半导体器件110a的平面面积可以等于上半导体器件120的平面面积。在这种情况下,下半导体器件110a的侧表面可以与上半导体器件120的侧表面共面。
下半导体器件110a可以包括第一贯通电极115和第三贯通电极116。
第一贯通电极115可以布置在例如下半导体器件110a的中央部分中。第一贯通电极115可以分别电连接到第一下连接凸块155和第一上连接凸块151,并可以通过第一上连接凸块151电连接到上半导体器件120。在示例性实施例中,第一贯通电极115可以用于外部装置与下半导体器件110a之间的信号传输或外部装置与上半导体器件120之间的信号传输。
第三贯通电极116可以布置在例如下半导体器件110a的边缘部分中。第三贯通电极116可以分别电连接到第二下连接凸块157和第二上连接凸块153,并可以通过第二上连接凸块153电连接到上半导体器件120。在示例性实施例中,第三贯通电极116可以用于向上半导体器件120供电。
每个第三贯通电极116的宽度可以大于每个第一贯通电极115的宽度。例如,在与下半导体器件110a的上表面110US平行的第一方向上,每个第三贯通电极116的水平宽度可以大于每个第一贯通电极115的水平宽度。
另外,下半导体器件110a可以包括第一上凸块焊盘117和第三上凸块焊盘118,第一上连接凸块151分别附接到第一上凸块焊盘117,第二上连接凸块153分别附接到第三上凸块焊盘118。在示例性实施例中,每个连接到第二上连接凸块153的第三上凸块焊盘118的宽度可以大于每个连接到第一上连接凸块151的第一上凸块焊盘117的宽度。
在示例性实施例中,图8中示出的半导体封装件10b可以通过包括下半导体器件110a的下晶片与包括上半导体器件120的上晶片之间的晶片与晶片接合工艺来形成。当下晶片和上晶片通过直接晶片接合方法来接合时,可以省略绝缘粘附层161、第一上连接凸块151和第二上连接凸块153。
图9是示出了根据各种示例性实施例的半导体封装件10c的截面图。
除了半导体封装件10c还包括第二再分布结构170之外,图9中示出的半导体封装件10c可以与图1中示出的半导体封装件10相同或类似。在下文中,将主要描述图9中示出的半导体封装件10c与图1中示出的半导体封装件10之间的区别。
参照图9,上半导体器件120的平面面积可以类似于下半导体器件110的平面面积。例如,在一些示例性实施例中,上半导体器件120的平面面积可以小于下半导体器件110的平面面积。第二再分布结构170可以布置在上半导体器件120与下半导体器件110之间以及上半导体器件120与连接基板130之间。第二再分布结构170可以包括第二再分布图案172和第二再分布绝缘层179。
第二再分布绝缘层179可以接触上半导体器件120的下表面120LS和围绕上半导体器件120的侧表面的模塑层165的下表面。第二再分布绝缘层179可以使包括在第二再分布结构170中的各种组件彼此电绝缘。
第二再分布图案172可以将上半导体器件120的第一焊盘128电连接到第一上连接凸块151,并可以将上半导体器件120的第二焊盘129电连接到第二上连接凸块153。例如,第二再分布图案172可以包括在水平方向上延伸的导电线图案171和在竖直方向上延伸的导电通路图案173。
另外,第二再分布图案172可以包括第四上凸块焊盘175和第五上凸块焊盘177,第一上连接凸块151分别附接到第四上凸块焊盘175,第二上连接凸块153分别附接到第五上凸块焊盘177。第四上凸块焊盘175的至少一部分和第五上凸块焊盘177的至少一部分可以从第二再分布绝缘层179的下表面突出。在示例性实施例中,每个连接到第二上连接凸块153的第五上凸块焊盘177的宽度可以大于每个连接到第一上连接凸块151的第四上凸块焊盘175的宽度。
图10是示出了根据各种示例性实施例的半导体封装件10d的截面图。
除了下半导体器件110被翻转之外,图10中示出的半导体封装件10d可以与图1中示出的半导体封装件10相同或类似。在下文中,将主要描述图10中示出的半导体封装件10d与图1中示出的半导体封装件10之间的区别。
参照图10,下半导体器件110可以布置为使得第一半导体基板111的第一表面111F面对第一再分布结构140并且第一半导体基板111的第二表面111B面对第二上半导体器件120。位于第一半导体基板111的第一表面111F上的第一半导体器件层113可以位于下半导体器件110的与第一再分布结构140相邻的下部中,并且位于第一半导体基板111的第二表面111B上的第一背面保护层119可以位于下半导体器件110的与上半导体器件120相邻的上部中。因为第一半导体器件层113设置在下半导体器件110的下部中,所以可以减小外部装置与下半导体器件110之间的信号传输路径的长度。
图11是示出了根据各种示例性实施例的半导体封装件10e的截面图。
除了省略了第一上连接凸块151和第二上连接凸块153并且还包括第三再分布结构190之外,图11中示出的半导体封装件10e可以与图1中示出的半导体封装件10相同或类似。在下文中,将主要描述图11中示出的半导体封装件10e与图1中示出的半导体封装件10之间的区别。
参照图11,第三再分布结构190可以布置在下半导体器件110的顶表面110US、连接基板130的上表面130US和第一模塑层163上。第一模塑层163可以围绕下半导体器件110的侧表面和连接基板130的侧表面。第三再分布结构190可以包括第三再分布图案192和第三再分布绝缘层199。
第三再分布绝缘层199可以覆盖下半导体器件110的上表面110US、连接基板130的上表面130US和第一模塑层163的上表面。第三再分布绝缘层199可以使包括在第三再分布结构190中的各种组件彼此电绝缘。
第三再分布图案192可以将下半导体器件110电连接到上半导体器件120,并可以将连接基板130的第二贯通电极133电连接到上半导体器件120。例如,第三再分布图案192可以包括在水平方向上延伸的导电线图案191和在竖直方向上延伸的导电通路图案193。
在第三再分布结构190上,可以布置上半导体器件120和覆盖上半导体器件120的至少一部分的模塑层167。在上半导体器件120与暴露于第三再分布绝缘层199的上侧的第三再分布图案192之间,可以布置用于将上半导体器件120电连接到第三再分布图案192的连接凸块168。例如,上半导体器件120的第一焊盘128可以通过连接凸块168和第三再分布图案192电连接到下半导体器件110的第一贯通电极115。上半导体器件120的第二焊盘129可以通过连接凸块168和第三再分布图案192电连接到连接基板130的第二贯通电极133。
图12是示出了根据各种示例性实施例的半导体封装件10f的截面图。
除了还包括封装基板200、第二模塑层169和散热构件180之外,图12中示出的半导体封装件10f可以与图1中示出的半导体封装件10相同或类似。在下文中,将主要描述图12中示出的半导体封装件10f与图1中示出的半导体封装件10之间的区别。
参照图12,封装基板200可以为印刷电路板(PCB)。封装基板200可以包括由酚树脂、环氧树脂或聚酰亚胺或者类似材料中的至少一种形成的基板基体210。另外,封装基板200可以包括布置在基板基体210的上表面上的第一上基板焊盘221和第二上基板焊盘223以及布置在基板基体210的下表面上的下基板焊盘230。第一上基板焊盘221、第二上基板焊盘223和下基板焊盘230可以由例如Cu、Ni或Al形成。在基板基体210中,可以形成用于将第一上基板焊盘221电连接到下基板焊盘230并将第二上基板焊盘223电连接到下基板焊盘230的内部布线(未示出)。
第一下连接凸块155可以布置在封装基板200与下半导体器件110之间。更详细地讲,第一下连接凸块155可以布置在封装基板200的第一上基板焊盘221与第一下凸块焊盘145之间,并可以将第一上基板焊盘221电连接到第一下凸块焊盘145。第一下连接凸块155可以用于封装基板200与下半导体器件110之间的信号传输或封装基板200与上半导体器件120之间的信号传输。在示例性实施例中,由外部装置提供的电力可以通过封装基板200、第一下连接凸块155和第一贯通电极115供应到下半导体器件110。
第二下连接凸块157可以布置在封装基板200与连接基板130之间。更详细地讲,第二下连接凸块157可以布置在封装基板200的第二上基板焊盘223与第二下凸块焊盘147之间,并可以将第二上基板焊盘223和第二下凸块焊盘147电连接。第二下连接凸块157可以用于封装基板200与上半导体器件120之间的信号传输。在示例性实施例中,由外部装置提供的电力可以通过封装基板200、第二下连接凸块157和第二贯通电极133供应到上半导体器件120。
外部连接端子300可以附接到封装基板200的下表面上。外部连接端子300可以附接到下基板焊盘230上。外部连接端子300可以为例如焊料球或凸块。外部连接端子300可以将半导体封装件10f和外部装置电连接。
第二模塑层169可以填充第一再分布结构140与封装基板200之间的间隙。另外,第二模塑层169可以围绕第一模塑层163的侧表面和上半导体器件120的侧表面。第二模塑层169可以接触上半导体器件120的侧表面和第一模塑层163的侧表面。第二模塑层169可以包括环氧基模塑树脂或聚酰亚胺基模塑树脂。例如,在一些示例性实施例中,第二模塑层169可以包括EMC。第二模塑层169可以通过例如模塑底部填充工艺来形成。
散热构件180可以布置在上半导体器件120的上表面上。例如,散热构件180可以包括具有高导热率的材料。散热构件180可以为例如散热器、均热片或热管。尽管在图12中在散热构件180与上半导体器件120之间未详细示出,但是可以在它们之间设置热界面材料(TIM)。TIM可以增强散热构件180与上半导体器件120之间的物理结合和热结合。
图13是示出了根据各种示例性实施例的半导体封装件10g的截面图。
除了第二模塑层169a的形状之外,图13中示出的半导体封装件10g可以与图12中示出的半导体封装件10f相同或类似。在下文中,将主要描述图13中示出的半导体封装件10g与图12中示出的半导体封装件10f之间的区别。
参照图13,第二模塑层169a可以暴露上半导体器件120的侧表面的至少一部分。即,第二模塑层169a可以完全地或部分地暴露上半导体器件120的侧表面。例如,第二模塑层169a可以通过毛细管底部填充工艺来形成。因为上半导体器件120的侧表面的至少一部分被暴露,所以上半导体器件120的散热特性可以改善。
图14A至图14M是示出了根据各种示例性实施例的制造半导体封装件的方法的截面图。在下文中,参照图14A至图14M,将描述制造图12中示出的半导体封装件10f的方法。为了简洁起见,将省略或简化之前给出的描述。
参照图14A,提供第一半导体晶片W1。第一半导体晶片W1可以由通过第一划片道SL1划分的多个半导体器件来形成。每个半导体器件包括第一半导体基板111、第一半导体器件层113和第一贯通电极115。第一半导体基板111可以包括彼此相对的第一表面111F和第二表面111B'。第一半导体器件层113可以形成在第一半导体基板111的第一表面111F上。第一贯通电极115可以从第一半导体基板111的第一表面111F延伸到第一半导体基板111的内部,并且可以为柱状。
参照图14B,在第一半导体基板111的第一表面111F上,可以形成电连接到第一贯通电极115的第一上凸块焊盘117,并在第一上凸块焊盘117上形成第一上连接凸块151。
参照图14C,将其上形成有第一上连接凸块151的第一半导体晶片W1附接到载体基板510上。载体基板510可以包括支撑基板511和位于支撑基板511上的粘附材料513。第一半导体晶片W1可以附接到载体基板510,使得第一上连接凸块151面对载体基板510。粘附材料513可以围绕第一上凸块焊盘117。
参照图14D,可以通过去除第一半导体基板111的一部分使第一贯通电极115的一部分暴露。由于去除了第一半导体基板111的一部分,所以第一贯通电极115穿过第一半导体基板111。选择性地,如图14D所示,第一贯通电极115可以从第一半导体基板111的第二表面111B突出。
为了暴露第一贯通电极115,可以通过使用化学机械研磨(CMP)工艺、回蚀工艺或以上工艺的组合来去除第一半导体基板111的一部分。
参照图14E,形成覆盖第一半导体晶片W1的第二表面111B的第一背面保护层119。第一背面保护层119可以通过例如旋涂工艺或喷涂工艺来形成。第一背面保护层119可以由例如绝缘聚合物形成。为了形成第一背面保护层119,可以形成覆盖第一半导体基板111的第二表面111B和第一贯通电极115的绝缘聚合物层,并且可以通过部分地去除绝缘聚合物层来暴露第一贯通电极115。例如,可以通过回蚀工艺来去除绝缘聚合物层的一部分。
参照图14E和图14F,在形成第一背面保护层119之后,执行沿着第一划片道SL1切割第一半导体晶片W1的锯切工艺。通过锯切工艺,可以将第一半导体晶片W1划分为多个下半导体器件110。另外,可以去除支撑基板511。
参照图14G,提供第二半导体晶片W2。第二半导体晶片W2可以由通过第二划片道SL2划分的多个第二半导体器件来形成。每个第二半导体器件包括第二半导体基板121、第二半导体器件层123、第一凸块焊盘125和第二凸块焊盘127。第二半导体基板121可以包括彼此相对的第一表面121F和第二表面121B。第二半导体器件层123可以形成在第二半导体基板121的第一表面121F上。
参照图14H,可以在第二半导体晶片W2上堆叠图14F中示出的下半导体器件110以及连接基板130。可以将下半导体器件110定位在第二半导体晶片W2的第一凸块焊盘125上,并且可以将第一上连接凸块151布置在第一凸块焊盘125与下半导体器件110的第一上凸块焊盘117之间。将连接基板130定位在第二半导体晶片W2的第二凸块焊盘127上,并且可以将第二上连接凸块153布置在第二凸块焊盘127与连接基板130的第二上凸块焊盘135之间。可以在下半导体器件110的一个表面和每个连接基板130的一个表面上形成绝缘粘附层161。绝缘粘附层161可以为例如NCF。
在将下半导体器件110和连接基板130设置在第二半导体晶片W2上之后,可以执行回流工艺或热压缩工艺。通过回流工艺或热压缩工艺,第一上连接凸块151可以附接到第一上凸块焊盘117和第一凸块焊盘125,并且第二上连接凸块153可以附接到第二上凸块焊盘135和第二凸块焊盘127。
参照图14I,在第二半导体晶片W2上形成用于模塑下半导体器件110和连接基板130的第一模塑层163。为了形成第一模塑层163,可以将模塑材料供应到第二半导体晶片W2上,并且可以通过硬化工艺使模塑材料硬化。
第一模塑层163可以覆盖下半导体器件110的侧表面和连接基板130的侧表面,并且可以不覆盖下半导体器件110的面对第二半导体晶片W2的一个表面和每个连接基板130的面对第二半导体晶片W2的一个表面。例如,为了形成第一模塑层163,可以形成覆盖下半导体器件110和连接基板130的模塑材料,并且可以通过诸如CMP工艺的平坦化工艺去除模塑材料,直到下半导体器件110的所述一个表面和每个连接基板130的所述一个表面被暴露。或者,在一些示例性实施例中,为了形成第一模塑层163,可以在下半导体器件110的所述一个表面和每个连接基板130的所述一个表面上布置模塑膜,然后可以使注入在模塑膜与第二半导体晶片W2之间的模塑材料硬化。
参照图14J,可以在下半导体器件110的向上暴露的所述一个表面和每个连接基板130的向上暴露的所述一个表面上形成第一再分布结构140。在形成第一再分布结构140之后,形成位于第一下凸块焊盘145上的第一下连接凸块155和位于第二下凸块焊盘147上的第二下连接凸块157。
参照图14K,执行沿着第二半导体晶片W2的第二划片道SL2切割图14J的所得材料的锯切工艺。通过锯切工艺,可以将图14J的所得材料划分为如图1所示的个体化的半导体封装件10。
参照图14L,在封装基板200上堆叠图14K的所得材料。可以将第一下连接凸块155定位在封装基板200的第一上基板焊盘221上,并且可以将第二下连接凸块157定位在封装基板200的第二上基板焊盘223上。通过回流工艺或热压缩工艺,第一下连接凸块155可以附接到第一上基板焊盘221,并且第二下连接凸块157可以附接到第二上基板焊盘223。
参照图14M,可以在封装基板200上形成第二模塑层169。第二模塑层169可以填充第一再分布结构140与封装基板200之间的空间,并可以覆盖第一模塑层163的侧表面和第一再分布结构140的侧表面。例如,第二模塑层169可以通过模塑底部填充工艺来形成。
在形成第二模塑层169之后,可以将散热构件180附接到上半导体器件120上。例如,TIM可以位于散热构件180与上半导体器件120之间,并且散热构件180可以通过TIM物理地结合到上半导体器件120。
在示例性实施例中,当上半导体器件120为逻辑芯片并且下半导体器件110为存储芯片时,因为散热构件180附接到产生相对大量的热的逻辑芯片,所以半导体封装件10的散热特性可以改善。另外,因为由外部装置提供的电力通过连接基板130的均具有大宽度的第二贯通电极133被供应到逻辑芯片,所以可以稳定地将电力供应到逻辑芯片。
图15A至图15C是示出了根据各种示例性实施例的制造半导体封装件的方法的截面图。在下文中,将主要描述参照图14A至图14M描述的制造半导体封装件10f的方法与参照图15A至图15C描述的制造半导体封装件的方法之间的区别。
参照图15A,可以在第二半导体晶片W2上堆叠下半导体器件110和连接基板130。此时,在下半导体器件110中,与图14B中一样,第一贯通电极115不通过第一半导体基板111的第二表面111B'暴露。
参照图15B,在第二半导体晶片W2上,形成用于模塑下半导体器件110和连接基板130的第一模塑层163。第一模塑层163可以覆盖下半导体器件110和连接基板130。
参照图15C,可以对第一模塑层163、下半导体器件110和连接基板130执行研磨工艺,以暴露第一贯通电极115。例如,可以对第一模塑层163、下半导体器件110和连接基板130执行CMP工艺。通过CMP工艺,下半导体器件110的第一贯通电极115可以通过第一半导体基板111的第二表面111B暴露。另外,通过CMP工艺,可以在第一模塑层163、下半导体器件110和连接基板130上获得平坦化的表面。
在执行了研磨工艺之后,进一步执行与图14J至图14M的工艺相同或类似的工艺,从而可以制造半导体封装件。
尽管上面已经具体示出并描述了各种实施例,但是将理解的是,在不脱离如在所附权利要求中限定的本公开的精神和范围的情况下,可以对本文进行形式和细节上的各种改变。
Claims (20)
1.一种半导体封装件,所述半导体封装件包括:
封装基板;
下半导体器件,所述下半导体器件布置在所述封装基板上并包括多个第一贯通电极;
多个第一下连接凸块,所述多个第一下连接凸块布置在所述封装基板与所述下半导体器件之间,并将所述封装基板电连接到所述多个第一贯通电极;
连接基板,所述连接基板布置在所述封装基板上并包括多个第二贯通电极;
多个第二下连接凸块,所述多个第二下连接凸块布置在所述封装基板与所述连接基板之间,并将所述封装基板电连接到所述多个第二贯通电极;以及
上半导体器件,所述上半导体器件布置在所述下半导体器件上,并电连接到所述多个第一贯通电极和所述多个第二贯通电极。
2.根据权利要求1所述的半导体封装件,其中,所述上半导体器件被配置为通过所述多个第二贯通电极接收电力。
3.根据权利要求1所述的半导体封装件,其中,所述多个第二贯通电极中的每个第二贯通电极的第二水平宽度大于所述多个第一贯通电极中的每个第一贯通电极的第一水平宽度。
4.根据权利要求3所述的半导体封装件,其中,所述第一水平宽度为1μm至7μm,并且所述第二水平宽度为10μm至20μm。
5.根据权利要求1所述的半导体封装件,其中,所述多个第二下连接凸块中的每个第二下连接凸块的第二水平宽度大于所述多个第一下连接凸块中的每个第一下连接凸块的第一水平宽度。
6.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
多个第一下凸块焊盘,所述多个第一下凸块焊盘分别电连接到所述多个第一贯通电极,所述多个第一下连接凸块分别附接到所述多个第一下凸块焊盘;以及
多个第二下凸块焊盘,所述多个第二下凸块焊盘分别电连接到所述多个第二贯通电极,所述多个第二下连接凸块分别附接到所述多个第二下凸块焊盘,
其中,所述多个第二下凸块焊盘中的每个第二下凸块焊盘的第二水平宽度大于所述多个第一下凸块焊盘中的每个第一下凸块焊盘的第一水平宽度。
7.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
多个第一上连接凸块,所述多个第一上连接凸块将所述上半导体器件电连接到所述多个第一贯通电极;以及
多个第二上连接凸块,所述多个第二上连接凸块将所述上半导体器件电连接到所述多个第二贯通电极。
8.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
第一模塑层,所述第一模塑层围绕所述下半导体器件的侧表面和所述连接基板的侧表面;以及
第二模塑层,所述第二模塑层围绕所述第一模塑层的侧表面并覆盖所述上半导体器件的侧表面的至少一部分。
9.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
第一再分布绝缘层,所述第一再分布绝缘层覆盖所述下半导体器件的下表面,并覆盖所述连接基板的下表面,所述下半导体器件的所述下表面与所述下半导体器件的面对所述上半导体器件的上表面相对,所述连接基板的所述下表面与所述连接基板的面对所述上半导体器件的上表面相对;以及
第一再分布图案,所述第一再分布图案的至少一部分布置在所述第一再分布绝缘层中,所述第一再分布图案将所述多个第一下连接凸块电连接到所述多个第一贯通电极并将所述多个第二下连接凸块电连接到所述多个第二贯通电极。
10.根据权利要求1所述的半导体封装件,其中,所述下半导体器件包括:
基板,所述基板包括面对所述上半导体器件的第一表面和与所述第一表面相对的第二表面;以及
半导体器件层,所述半导体器件层布置在所述基板的所述第一表面上。
11.根据权利要求1所述的半导体封装件,其中,所述下半导体器件包括:
基板,所述基板包括面对所述上半导体器件的第一表面和与所述第一表面相对的第二表面;以及
半导体器件层,所述半导体器件层布置在所述基板的所述第二表面上。
12.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
第二再分布绝缘层,所述第二再分布绝缘层覆盖所述上半导体器件的面对所述下半导体器件的下表面;以及
第二再分布图案,所述第二再分布图案的至少一部分布置在所述第二再分布绝缘层中,所述第二再分布图案将所述上半导体器件电连接到所述多个第一贯通电极并将所述上半导体器件电连接到所述多个第二贯通电极。
13.一种半导体封装件,所述半导体封装件包括:
下半导体器件,所述下半导体器件包括多个第一贯通电极;
连接基板,所述连接基板包括多个第二贯通电极;
上半导体器件,所述上半导体器件堆叠在所述下半导体器件的上表面和所述连接基板的上表面上,所述上半导体器件电连接到所述多个第一贯通电极并电连接到所述多个第二贯通电极;以及
再分布结构,所述再分布结构布置在所述下半导体器件的下表面和所述连接基板的下表面上,所述再分布结构电连接到所述多个第一贯通电极并电连接到所述多个第二贯通电极。
14.根据权利要求13所述的半导体封装件,其中,所述上半导体器件的平面面积大于所述下半导体器件的平面面积与所述连接基板的平面面积之和。
15.根据权利要求13所述的半导体封装件,其中,所述再分布结构包括:
再分布绝缘层;
多个第一下凸块焊盘,所述多个第一下凸块焊盘分别电连接到所述多个第一贯通电极,所述多个第一下凸块焊盘至少部分地从所述再分布绝缘层突出;以及
多个第二下凸块焊盘,所述多个第二下凸块焊盘分别电连接到所述多个第二贯通电极,所述多个第二下凸块焊盘至少部分地从所述再分布绝缘层突出,并且
其中,所述多个第二下凸块焊盘中的每个第二下凸块焊盘的水平宽度不同于所述多个第一下凸块焊盘中的每个第一下凸块焊盘的水平宽度。
16.根据权利要求15所述的半导体封装件,所述半导体封装件还包括:
多个第一下连接凸块,所述多个第一下连接凸块分别位于所述多个第一下凸块焊盘上;以及
多个第二下连接凸块,所述多个第二下连接凸块分别位于所述多个第二下凸块焊盘上,
其中,所述多个第一下连接凸块中的每个第一下连接凸块的水平宽度不同于所述多个第二下连接凸块中的每个第二下连接凸块的水平宽度。
17.根据权利要求15所述的半导体封装件,所述半导体封装件还包括位于所述上半导体器件上的散热构件。
18.根据权利要求13所述的半导体封装件,其中,所述下半导体器件包括存储芯片,并且所述上半导体器件包括逻辑芯片。
19.根据权利要求13所述的半导体封装件,所述半导体封装件还包括:
多个第一上连接凸块,所述多个第一上连接凸块布置在所述上半导体器件与所述下半导体器件之间,所述多个第一上连接凸块分别电连接到所述多个第一贯通电极;以及
多个第二上连接凸块,所述多个第二上连接凸块布置在所述上半导体器件与所述连接基板之间,所述多个第二上连接凸块分别电连接到所述多个第二贯通电极,
其中,所述多个第一上连接凸块中的每个第一上连接凸块的第一水平宽度不同于所述多个第二上连接凸块中的每个第二上连接凸块的第二水平宽度。
20.一种半导体封装件,所述半导体封装件包括:
封装基板;
存储芯片,所述存储芯片布置在所述封装基板上并包括多个第一贯通电极;
连接基板,所述连接基板布置在所述封装基板上并包括多个第二贯通电极,所述多个第二贯通电极中的每个第二贯通电极的第二宽度大于所述多个第一贯通电极中的每个第一贯通电极的第一宽度;
逻辑芯片,所述逻辑芯片布置在所述存储芯片的上表面和所述连接基板的上表面上,所述逻辑芯片电连接到所述多个第一贯通电极和所述多个第二贯通电极;
散热构件,所述散热构件位于所述逻辑芯片上;
再分布结构,所述再分布结构布置在所述存储芯片的下表面和所述连接基板的下表面上,所述再分布结构包括分别电连接到所述多个第一贯通电极的多个第一下凸块焊盘,并包括分别电连接到所述多个第二贯通电极的多个第二下凸块焊盘;
多个第一下连接凸块,所述多个第一下连接凸块位于所述多个第一下凸块焊盘与所述封装基板之间;以及
多个第二下连接凸块,所述多个第二下连接凸块位于所述多个第二下凸块焊盘与所述封装基板之间,
其中,所述存储芯片包括:
第一基板,所述第一基板包括面对所述逻辑芯片的第一表面和与所述第一表面相对的第二表面;以及
第一半导体器件层,所述第一半导体器件层位于所述第一基板的所述第一表面上,
其中,所述逻辑芯片包括:
第二基板,所述第二基板包括面对所述存储芯片的第三表面和与所述第三表面相对的第四表面;以及
第二半导体器件层,所述第二半导体器件层位于所述第二基板的所述第三表面上,并且
其中,所述逻辑芯片的平面面积大于所述存储芯片的平面面积与所述连接基板的平面面积之和。
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