CN110957225B - 半导体元件及其制造方法 - Google Patents
半导体元件及其制造方法 Download PDFInfo
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- CN110957225B CN110957225B CN201910917224.1A CN201910917224A CN110957225B CN 110957225 B CN110957225 B CN 110957225B CN 201910917224 A CN201910917224 A CN 201910917224A CN 110957225 B CN110957225 B CN 110957225B
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
一种半导体元件及其制造方法。半导体元件制造方法包含:形成一栅极结构于一鳍状结构上。凹陷化一源极/漏极区于该鳍状结构。形成一第一半导体层于该凹陷化源极/漏极区。形成一第二半导体层于该第一半导体层上。该鳍状结构是由SixGe1‑x制成,其中0≤x≤0.3,该第一半导体层是由SiyGe1‑y制成,其中0.45≤y≤1.0,以及该第二半导体层是由SizGe1‑z形成,其中0≤z≤0.3。
Description
技术领域
本揭露是有关一种半导体元件及其制造方法。
背景技术
为了追求更高的装置密度、更佳的效能及更低的成本,半导体产业已进入纳米技术制程。而来自制造与设计的双重挑战已促使三维设计的开发,例如:鳍式场效晶体管(FinField-Effect Transistor,FinFET),包括鳍式FET(FinFET)和环绕式栅极(GAA)FET。在一个鳍式场效晶体管中,栅极电极层与通道区的三个侧表面相邻且栅极介电层位于其间。因为栅极结构在三个面上围绕(缠绕)鳍状结构,因此晶体管实质上具有三个栅极控制鳍状结构或通道区的电流。FinFET的电流驱动能力通常由鳍状结构的数量,位于通道区的鳍状结构的宽度及鳍状结构的高度所决定。此外,硅锗或锗取代了硅,用作FET的通道区。
发明内容
一种半导体元件制造方法,该方法包含形成栅极结构于鳍状结构之上;凹陷化该鳍状结构的源/漏极区;形成第一半导体层于凹陷化源/漏极区之上;以及形成第二半导体层于第一半导体层之上,其中鳍状结构是由SixGe1-x制成,其中0≤x≤0.3,第一半导体层是由SiyGe1-y制成,其中0.45≤y≤1.0,以及第二半导体层是由SizGe1-z制成,其中0≤z≤0.3。
一种半导体元件制造方法,方法包含形成栅极结构于鳍状结构之上;凹陷化鳍状结构的源/漏极区;形成第一阻障半导体层于源/漏极区之上;形成第二阻障半导体层于第一阻障半导体层之上;形成第三阻障半导体层于第二阻障半导体层之上;形成第二半导体层于第三阻障半导体层之上,其中第一阻障半导体层的厚度范围介于0.2nm至0.8nm,第二阻障半导体层的厚度范围介于0.2nm至0.8nm,以及第三阻障半导体层的一厚度范围介于0.2nm至0.8nm。
一种半导体元件,包含栅极结构设于通道半导体层之上;源/漏极区设于该通道半导体层的侧壁;第一磊晶半导体层设于源/漏极区之上;第二磊晶半导体层设于第一磊晶半导体层之上;导电接触孔设于第二磊晶半导体层之上;以及介电层具有开口且导电接触孔填于开口,其中第一磊晶半导体层的厚度范围介于0.2nm至0.8nm,以及第一磊晶半导体层的磷的扩散系数于450℃时小于1×10-21cm2/s。
附图说明
本揭露的观点从后续描述以及附图可以更佳理解。应注意的是,根据本产业的标准作业,许多特征结构未按照比例绘制。事实上,许多特征结构的尺寸可以任意地放大或缩小以清楚论述。
图1A,图1B以及图1C是根据本揭露的实施例展示半导体场效晶体管元件的源/漏极磊晶层的剖面图;
图2A及图2B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图3A及图3B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图4A及图4B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图5A及图5B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图6A,图6B及图6C是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图7A及图7B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图8A及图8B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图9A,图9B及图9C是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图10A及图10B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图11A及图11B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图12A及图12B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图13A,图13B及图13C是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图14A及图14B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图15A及图15B是根据本揭露的实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图16A及图16B是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图17A,图17B及图17C是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;图17D是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图18A及图18B是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图19A及图19B是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图20是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图21A及图21B是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图22A及图22B是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图23A及图23B是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图24A,图24B及图24C是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图25A及图25B是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段;
图26A及图26B是根据本揭露的另一实施例绘示半导体元件制造过程中不同阶段中的一个阶段。
【符号说明】
10 基板
22 硬遮罩图案
28 鳍衬垫层
29 第一绝缘材料层
30 第一隔离绝缘层
31 上表面
40 虚设栅极结构
41 虚设栅极介电层
42 虚设栅极电极层
45 侧壁间隔物
48 栅极开口
60 层间介电层
61 源/漏极开口
62 栅极介电层
65 栅极电极层
70 导电性接触
100 源/漏极区
103 第一扩散半导体层
105 第二扩散半导体层
107 第三扩散半导体层
110 磊晶半导体层
120 第一半导体层
125 第二半导体层
102 104 扩散阻障层
20 121 鳍状结构
50 52 阻障半导层
55 57 58 59 源/漏极磊晶层
具体实施方式
以下的揭露内容提供许多不同实施例或范例,以实施本揭露的不同结构。以下叙述构件及排列方式的特定实施例或范例,以求简化本揭露内容。当然,这些仅为范例说明并非用以限定本揭露。举例来说,构件尺寸并未限定于所揭露的范围或数值,而是根据制程条件及/或元件的期望特性。再者,若是以下的揭露内容叙述了将一第一特征部件形成于一第二特征部件之上或上方,即表示其包含了上述第一特征部件与上述第二特征部件形成直接接触的实施例,亦包含了尚可将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间,而使得上述第一特征部件与上述第二特征部件可能未直接接触的实施例。为达简化及明确目的,不同特征部件可随意绘制成不同尺寸。
再者,在空间上的相关用语,例如“之下”、“以下”、“下”、“以上”、“上”等等在此处是用以容易表达出本说明书中所绘示的附图中元件或特征部件与另外的元件或特征部件的关系。这些空间上的相关用语除了涵盖附图所绘示的方位外,还涵盖装置于使用或操作中的不同方位。此装置可具有不同方位(旋转90度或其他方位)且此处所使用的空间上的相关符号同样有相应的解释。此外,”由...所制成”一词可意味“包含”或“仅包含”。在此揭露中“A,B和C中的至少一个”一词意味“A,B及/或C”(A,B,C,A+B,A+C,B+C,A+B+C),除非另有说明,否则并不表示A中的一个,B中的一个以及C中的一个。
随着半导体元件的尺寸缩小,举例来说,鳍式场效晶体管(FinFETs)及环绕式栅极晶体管(GAA FETs),需要改善源/漏极区的结构及/或构形以降低导电接触孔(金属层)和源/漏极区(半导体)之间的接触电阻,以及提供源/漏极区的通道区一合适应力。为提供一合适应力给FinFETs或GAA FETs的源/漏极区,形成一或多层的磊晶半导体层。为降低接触电阻,采用环绕式接触孔其覆盖鳍状结构源/漏极区的顶面及侧面。
由于Ge的高载子移动率,使用高含量Ge的Ge或SiGe来制作下一世代的半导体元件的通道区。当Ge或SiGe用于FinFET的鳍状结构时,作为鳍状结构一部分的源/漏极区也由Ge或SiGe制成。因此含有Ge或SiGe的FinFET之中,n形FET的源/漏极区磊晶层包括掺杂磷(P)的Ge(Ge:P),掺杂磷(P)的SiGe(SiGe:P),及/或掺杂磷(P)的Si(Si:P),P形FET则采用包括一个或多个掺杂硼的Ge,SiGe及/或Si。然而,P在Ge中的扩散系数约为P在Si的1000倍(在450℃之下,磷在Ge中的扩散系数约为1×10-19cm2/s)。因此,P容易在Ge中扩散,以及从Ge:P到通道区的P迁移将导致器件性能下降,举例来说,高漏电流,较低的电子迁移率,较大的介质泄滞及/或低可靠性。本揭露,提供用于FinFET和GAA FET的源/漏极磊晶结构其包含扩扩散阻障层及其制造方法。
本揭露以下所述实施例中,除非另有说明,可以在另一实施例中采用一个实施例的材料,构形,尺寸及/或制造过程,并且可以省略说明。以下实施例中,半导体(例如,Si,Ge,SiGe等),半导体层和磊晶层等通常是指单晶层,除非另有说明。本揭露中,“源/漏极”一词是指源极和漏极中的一者或两者,并且“源极”和“漏极”可互换使用且其结构实质上为相同。
图1A至图1C根据本揭露的实施例绘示源/漏极磊晶结构的剖面图。第1A至图1C中,源/漏极区100是鳍状结构的一部分。在一些实施例中,源/漏极区100为凹陷化的鳍状结构其顶部低于鳍状结构的通道区。在一些实施例中,鳍状结构包含通道区和源/漏极区100其由SixGe1-x制成,其中0≤x≤0.3。在特定实施例中,鳍状结构包含通道区和源/漏极区100其由Ge(x=0)制成。在一些实施例中,鳍状结构包含通道区和源/漏极区100其非有意掺杂(不掺杂)。在一些实施例中,如果鳍状结构包含杂质其浓度小于1×1018原子/cm3。
如图1A至图1C所示,形成一磊晶半导体层110于源/漏极区100上,在一些实施例中,磊晶半导体层110由SizGe1-z制成,其中0≤z≤0.3,在特定实施例中,磊晶半导体层110由Ge(z=0)制成。在一些实施例中,磊晶半导体层110掺杂杂质,例如P,As,Sb及/或B。在特定实例中,磊晶半导体层110掺杂P。在一些实施例中,磊晶半导体层110中的磷浓度(例如Ge:P)介于5×1019atoms/cm3至1×1020atoms/cm3。
如图1A至图1C所示,设置扩散阻障层于磊晶半导体层110和源/漏极区100之间以抑制杂质(例如,P)从磊晶半导体层110经由源/漏极区100扩散至通道区。更具体地,在一些实施例中,扩散阻障层在450℃下具有一磷扩散系数其小于1×10-21cm2/s。
如图1A所示,扩散阻障层102是为含硅的材料,例如SiyGe1-y,其中0.7≤y≤1.0。在特定的实施例中,扩散阻障层102为硅(y=1)并磊晶形成于源/漏极区100上。在一些实施例中,扩散阻障层102的厚度范围介于约0.2nm至约0.8nm,而在其他实施例中,扩散阻障层102的厚度等于或小于约0.5nm。在一些实施例中,扩散阻障层102是单个Si层,由于在450℃下,磷在硅中的扩散系数约为8×10-23cm2/s,所以针对磷(P),单个Si层可作为有效的扩散阻障层。
如图1B所示,扩散阻障层104为含SiGe的材料并磊晶形成于源/漏极区100上,例如SiyGe1-y,其中0.45≤y≤0.7。在特定实施例中,0.5≤y≤0.7。在一些实施例中,扩散阻障层104的厚度范围为约0.2nm至约0.8nm。而在其他实例中,扩散阻障层104的厚度等于或小于约0.5nm。在一些实施例中,扩散阻障层104是单个SiGe层。由于磷在Si0.6Ge0.4中的扩散系数约为1×10-22cm2/s,一个SiGe层其具有Si浓度等于或大于0.5,所以针对磷(P),该SiGe层可作为有效的扩散阻障层。
如图1C所示,扩散阻障层包含三层,第一扩散半导体层103,第二扩散半导体层105和第三扩散半导体层107。在一些实施例中,第一扩散半导体层103由Siy1Ge1-y1制成,其中0.2≤y1≤0.7。第二扩散半导体层105由Siy2Ge1-y2制成,其中0.45≤y2≤1.0,以及第三扩散半导体层107由Siy3Ge1-y3制成,其中0.2≤y3≤0.7.在一些实施例中,满足y1>x,y2>y1,y2>y3,及y3>z.在特定实施例中,y2=1.0。在一些实施例中,第一扩散半导体层103,105和107的厚度范围介于约0.2nm至约0.8nm,而在其他实施例中,其厚度范围等于或小于约0.5nm。在一些实施例中,第二扩散半导体层105的厚度小于第一及第三扩散半导体层103和107的厚度。通过第一及第三阻障半导体层具有硅浓度其大于源/漏极区100和磊晶半导体层110的硅浓度以及小于第二扩散半导体层105的硅浓度,可以降低晶格不匹配导致的应力,其可降低界面能态。
在一些实施例中,省略第一及第三阻障半导体层103和107中的一个(两层结构)。在其他实施例中,形成多于三个(例如,4-8个)阻障半导体层。
图2A至图15B是根据本揭露的另一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。须知在其他的实施例中,可于图2A至图15B所绘示的制程之前,之中或之后加入额外的操作。操作/制程步骤可以调换。
图2A至图2B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图2A是为对应图2B中直线Y1-Y1的剖面图。
如图2A和图2B所示,形成一或多个鳍状结构20于基板10上,在一个实施例中,基板10至少在其表面部分上包括单晶半导体层。基板10可包含单晶半导体材料,举例来说,但不设限于此,Si,Ge,SiGe,GaAs,InSb,GaP,GaSb,InAlAs,InGaAs,GaSbP,GaAsSb及InP。在一个实施例中,基板10由Ge制成或者基板的表面具有一Ge层。在其他实施例中,基板10由SixGe1-x制成,其中0<x≤0.3或基板10的表面具有一SixGe1-x层。
基板10可包含一个或多个缓冲层(未绘示)在其表面区域。缓冲层可用于逐渐改变晶格常数,从基板的晶格常数到源/漏极区的晶格常数。缓冲层可由单晶半导体材料磊晶成长而成,例如,但不设限于此,Si,Ge,GeSn,SiGe,GaAs,InSb,GaP,GaSb,InAlAs,InGaAs,GaSbP,GaAsSb,GaN,GaP,和InP。在一个特定的实施例中,基板10包含在基板10上磊晶成长的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度从最底部缓冲层的30atomic%,可增加到最顶部缓冲层的70atomic%。基板10可包含不同的区域其已适当掺杂杂质(例如,p型或n型导电性)。
可以使用任何合适的方法图案化鳍状结构20。例如,可以使用一或多个光刻工艺来图案化鳍状结构,包括双重曝光或多重曝光图案化操作。一般而言,相较于单次直接光刻,双重曝光或多重曝光图案化结合光刻和自对准工艺,可制造具有较小节距的图案。举例来说,在其他实施例中,形成虚设层于基板上,并使用光刻工艺图案化虚设层。使用自对准工艺在图案化虚设层旁边形成间隔物。接着移除虚设层,可使用剩余的间隔物来图案化鳍状结构。
在其他实施例中,可以使用硬遮罩图案22作为蚀刻遮罩来图案化鳍状结构。在一些实施例中,硬遮罩图案22包括第一遮罩层和设置第一遮罩层上的第二遮罩层。第一遮罩层为垫氧化层其由氧化硅所制成,其可通过热氧化形成。第二遮罩层由氮化硅制成,其由化学气相沉积(CVD)形成,包括低压化学气相沉积(LPCVD)和电浆化学气相沉积(PECVD),物理气相沉积(PVD),原子层沉积(ALD),或其他合适的方法。使用图案化操作包含光刻和蚀刻工艺将沉积形成的硬遮罩层图案化为硬遮罩图案22。接着,使用硬遮罩图案将基板10图案化为鳍状结构20,两者均沿X方向延伸。如图2A和2B所示,两个鳍状结构20沿Y方向排列。但鳍状结构的数量不限于两个,可为一个或三个或更多个。在一些实施例中,在鳍状结构的两侧上形成一个或多个虚设鳍状结构,以提高图案化操作中的图案拟真度。
在一些实施例中,鳍状结构的上部部分其沿着Y方向的宽度范围介于约5nm至约40nm,在其他实施例中,其介于约10nm至约20nm的范围内。在一些实施例中,鳍状结构沿着Z方向的高度范围介于约100nm至约200nm。
图3A至图3B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图3A是为对应图3B中直线Y1-Y1的剖面图。
形成鳍状结构20之后,形成包括一层或多层绝缘材料的第一绝缘材料层29于基板10上,使得鳍状结构20完全嵌入第一绝缘材料层29中。第一绝缘材料层29所使用的绝缘材料可包括氧化硅,氮化硅,氮氧化硅(SiON),SiCN,氟掺杂硅酸盐玻璃(FSG)或低介电常数介电材料,其可以由下面方式形成,LPCVD(低压化学气相沉积),电浆化学气相沉积(PECVD)或可流动的CVD或任何其它合适的成膜方法。在一些实施例中,第一绝缘材料层29由氧化硅制成。形成第一绝缘材料层29之后,可以执行退火操作。接着平坦化操作,例如利用化学机械抛光(CMP)方法及/或回蚀方法移除硬遮罩图案22,使得鳍状结构20的上表面从第一绝缘材料层29露出如图3A所示。
在一些实施例中,在形成第一绝缘材料层29之前,在鳍状结构上方形成一个或多个鳍衬垫层28。鳍衬垫层28可以由氮化硅或氮化硅基材料制成(例如,SiON或SiCN)。
图4A至图4B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图4A是为对应图4B中直线Y1-Y1的剖面图。
接着,如图4A所示,凹陷第一绝缘材料层29以形成第一隔离绝缘层30,使得鳍状结构20的上部部分露出。利用这个操作,第一隔离绝缘层30使得数个鳍状结构20彼此电隔离,这也称为浅凹沟绝缘(STI)。在一些实施例中,凹陷蚀刻后,露出的鳍状结构的高度H1范围介于约30nm至约100nm,其他实施例中,其范围介于约40nm至约80nm。
图5A至图5B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图5A是为对应图5B中直线Y1-Y1的剖面图。
在形成隔离绝缘层30之后,形成虚设栅极结构40如图5A和图5B所示。虚设栅极结构40包含虚设栅极介电层41和虚设栅极电极层42。虚设栅极介电层41包含一或多层绝缘材料,例如含氧化硅材料。在一个实施例中,使用CVD形成氧化硅。在一些实施例中,虚设栅极介电层41的厚度范围介于约1nm至约5nm。
在暴露的鳍状结构20和第一隔离绝缘层30的上表面上,先毯式地沉积虚设栅极介电层41以形成虚设栅极结构40。接着,在虚设栅极介电层41上,毯式地沉积虚设栅极电极层42,使得鳍状结构20完全嵌入虚设栅极电极层42中。虚设栅极电极层42包含硅例如多晶硅(复晶硅)或非晶硅。在一些实施例中,虚设栅极电极层42由复晶硅制成。在一些实施例中,虚设栅极电极层42的厚度范围介于约100nm至约200nm。在一些实施例中,虚设栅极电极层42历经平坦化操作。虚设栅极介电层41和虚设栅极电极层42是由化学沉积而成,包含低压化学气相沉积和电浆化学气相沉积,物理气相沉积,原子层沉积或其它合适的方法。接着,形成一个光罩层于虚设栅极电极层上。这个光罩层可为光阻图案或硬遮罩图案。
接着,在光罩层及虚设栅极电极层42上执行图案化操作,图案化虚设栅极电极层42为虚设栅极结构40如图5A和图5B所示。利用图案化虚设栅极结构,将成为源/漏极区的鳍状结构20的上部部分,其部分暴露于虚设栅极结构40的反侧如图5B所示,图5B中分别是,形成二个虚设栅极结构40于二个鳍状结构20上,形成一个虚设栅极结构40于二个鳍状结构20之上或上方。然而布置方式并不限于图5B。
在一些实施例中,Y方向上的虚设栅极结构40的宽度范围介于约5nm至约30nm。在其他实施例中,其介于约7nm至约15nm。在一些实施例中,虚设栅极结构的节距范围介于约10nm至约50nm。在其他实施例中,其介于约15nm至约40nm。
图6A至图6C是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图6A是为对应图6B中直线Y2-Y2的剖面图以及图6C是为对应图6B中直线X1-X2的剖面图。
形成虚设栅极结构40之后,利用CVD或者其他合适的方法保角式地形成毯覆层,其为绝缘材料且用于侧壁间隔物45。因为毯覆层由保角方式沉积而成,所以在垂直表面上具有实质上相等的厚度,例如在侧壁,在水平表面及在虚设栅极结构的顶部。在一些实施例中,沉积后的毯覆层具有一厚度范围介于约2nm至约20nm。在一个实施例中,毯覆层的隔绝材料不同于第一隔离绝缘层和第二隔离绝缘层的材料,以及毯覆层的隔绝材料含有氮化硅的材料,例如氮化硅,SiON,SiOCN或SiCN及上述组合。在一些实施例中,毯覆层(侧壁间隔物45)由氮化硅制成。利用异向性蚀刻形成侧壁间隔物45于虚设栅极结构40的相对侧如图6A和图6B所示。
图7A至图7B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图7A是为对应图7B中直线X1-X2的剖面图。
接着,虚设栅极结构40并未覆盖鳍状结构20的源/漏极区,以及将侧壁间隔物45向下凹陷至第一隔离绝缘层30的上表面31之下。
图8A至图8B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图8A是为对应图8B中直线X1-X2的剖面图。
凹陷源/漏极之后,形成一或多个阻障半导层50于凹陷化源/漏极的内表面。阻障半导层50为一或多个扩散阻障层如第1A至图1C所示。可通过有机金属化学气相沉积法(MOCVD),分子束磊晶法(MBE),ALD或任何其他成膜方法磊晶形成阻障半导层50于鳍状结构20上。在一些实施例中,Si2H6作为Si的来源气体,以及Ge2H6作为Ge的来源气体。在特定实施例中,替代或除此之外,使用Ge2H6及/或Si2H6,GeH4及/或SiH4。可利用一或多种惰性气体作为稀释气体例如,H2,He,Ar及/或N2。阻障半导层50的最底部与鳍状结构20的凹陷化源/漏极接触,其鳍状结构20位于隔离绝缘层30的上表面31的下方。
图9A至图9B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图9A是为对应图9B中直线X1-X2的剖面图。
形成阻障半导层50之后,接着形成一或多个源/漏极磊晶层55于阻障半导层50上如图9A和图9B所示。在一些实施例中,用于n型FET,源/漏极磊晶层55包含掺杂磷的Ge(Ge:P)或者掺杂P的SizGe1-z(SiGe:P),其中0<z≤0.3。在其他实施例中,除了P以外,As及/或Sb被用作掺杂。在一些实施例中,Ge:P或SiGe的磷含量范围介于约1×1019atoms/cm3至1×1020atoms/cm3。在其他实施例中,磷含量范围介于约5×1019atoms/cm3至8×1019atoms/cm3。在其他实施例中,掺杂硼(B)于P型FET,硼含量范围介于约2×1019atoms/cm3至8×1019atoms/cm3。
利用有机金属化学气相沉积法(MOCVD),分子束磊晶法(MBE),ALD或任何其他膜形成方法,可磊晶形成Ge:P层于鳍状结构20的源/漏极区上。在一些实施例中,Ge2H6气体用作Ge的来源气体,在一些实施例中,Si2H6气体用作Si的来源气体,在特定的施实例中,替代或除此之外,使用Ge2H6及/或Si2H6,GeH4及/或SiH4作为来源气体。一或多个惰性气体作为稀释气体,例如H2,He,Ar及/或N2。
如图9C所示,在一些实施例中,源/漏极磊晶层55从第一隔离绝缘层30的上表面凸出,以及源/漏极磊晶层55具有菱形或六边形的横截面形状。
图10A至图11B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图10A和图11A是为对应图10B和图11B中直线X1-X2的剖面图。
接着,形成层间介电(ILD)层60。ILD层60包含化合物其包含Si,O,C及/或H,例如氧化硅,SiCOH和SiOC。有机材料例如高分子聚合物,可被用来形成ILD层60。形成ILD层60之后,执行平坦化操作例如CMP,使得虚设栅极结构40的上部部分的虚设栅极电极层露出如图11A所示。在一些实施例中,以硬遮罩层(未绘示)来图案化虚设栅极结构40,以及在一些实施例中利用平坦化操作移除硬遮罩层。
图12A至图12B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图12A是为对应图12B中直线X1-X1的剖面图。
接着,如图12A和图12B所示,移除虚设栅极结构40(虚设栅极介电层41和虚设栅极电极层42),分别地形成栅极开口48,而鳍状结构20的上部暴露在其中。在一些实施例中,并未移除侧壁间隔物45。
在移除虚设栅极结构40的过程中,阻障半导层50保护源/漏极磊晶结构。可通过电浆干蚀刻及/或湿蚀刻移除虚设栅极结构40。当虚设栅极电极层为复晶硅,以及阻障半导层50为氧化硅,可使用湿蚀刻剂例如四甲基氢氧化铵(TMAH)选择性移除虚设栅极电极层。接着使用电浆干蚀刻及/或湿蚀刻移除虚设栅极介电层。
图13A至图13C是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图13A是为对应图13B中直线X1-X1的剖面图以及图13C是为对应图13B中直线Y1-Y1的剖面图。
接着,形成栅极介电层62于栅极开口48之中,该栅极开口48位于露出的鳍状结构20上,其为通道区域及周围区域如第13A和图13B所示,在特定实施例中,栅极介电层62包含一或多层介电材料,例如氧化硅,氮化硅或高介电常数介电材料,其他合适的介电材料,及/或以上述组合。高介电常数介电材料的实例包含HfO2,HfSiO,HfSiON,HfTaO,HfTiO,HfZrO,氧化锆,氧化铝,氧化钛,二氧化铪-氧化铝(HfO2-Al2O3)合金,其他合适的高介电常数介电材料,及/或上述组合。在一些实施例中,栅极介电层62包含在沟道层和介电材料之间形成的界面层,其利用化学氧化而成。
可通过CVD,ALD或任何其他合适的方法形成栅极介电层62,在一个实施例中,通过高度保角式沉积制程例如ALD,以确保栅极介电层在每个通道层具有均一厚度。在一个实施例中,栅极介电层62的厚度范围介于约1nm至约6nm。
接着,形成栅极电极层65于栅极介电层62上。栅极电极层65包含一或多层导电材料,例如多晶硅,铝,铜,钛,钽,钨,钴,钼,氮化钽,硅化镍,硅化钴,TiN,WN,TiAl,TiAlN,TaCN,TaC,TaSiN,金属合金,其他合适的材料及/或上述组合。
可通过CVD,ALD,电镀或任何其他合适的方法形成栅极电极层65。栅极介电层62和栅极电极层65也沉积于ILD层60的上表面上。形成栅极介电层及栅极电极层于ILD层60上,接着执行平坦化操作例如CMP,直到ILD层60的上表面露出如图13A所示。
本揭露的特定实施例,在栅极介电层62和栅极电极层65之间,插入一或多层功函数调整层(未绘示)。功函数调整层由导电材料制成例如单层TiN,TaN,TaAlC,TiC,TaC,Co,Al,TiAl,HfTi,TiSi,TaSi或TiAlC,或上述材料的两种或多种的多层制成。对于n沟道FET,可通过一或多层的TaN,TaAlC,TiN,TiC,Co,TiAl,HfTi,TiSi和TaSi作为功函数调整层,以及对于p沟道FET,一或多层TiAlCAl,TiAl,TaN,TaAlC,TiN,TiC和Co作为功函数调整层。功函数调整层可通过ALD,PVD,CVD,电子束蒸镀或其他合适的工艺形成。此外,可分别对n沟道FET和p沟道FET形成功函数调整层,其可以使用不同的金属层。
图13C绘示形成栅极电极层65之后,鳍状结构20的源/漏极区。如图13C所示,源/漏极磊晶层55被ILD层60所覆盖。如图13C所示,阻障半导层50设置于第一隔离绝缘层30和ILD层60之间的界面之下。
图14A至图14B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图14A是为对应图14B中直线Y1-Y1的剖面图。
如图14A和图14B所示,进行一次或多次光刻和蚀刻操作图案化ILD层60,从而形成源/漏极开口61。在源/漏极开口61中,露出源/漏极磊晶层55其形成于鳍状结构20上。如图14A和图14B所示,形成源/漏极开口61以露出一部分的源/漏极磊晶层55。然而,其构形不限于此。在一些实施例中,形成源/漏极开口61于二个源/漏极磊晶层55上且形成源/漏极磊晶层55于二个分离的鳍状结构,在其他实施例中,形成源/漏极开口61于三个或多个源/漏极磊晶层55上且形成源/漏极磊晶层55于三个或多个鳍状结构。
图15A及图15B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图15A是为对应图15B中直线Y1-Y1的剖面图。
形成源/漏极开口61之后,形成导电性接触70如图15A及图15B所示。形成一或多层导电材料于源/漏极开口61的残留部分。形成一或多层导电材料于接触口里以及上,然后执行平坦化操作例如CMP,以形成导电性接触70如图18A及图18B所示。在一些实施例中,导电性接触70包含一个衬垫层和一个体层。一个衬垫层是一个阻障层及/或一个粘着(粘合)层。在一些实施例中,形成Ti层于源/漏极磊晶层55上以及形成一个TiN或TaN层于此Ti层上,其作为衬垫层。体层包含一或多层的Co,Ni,W,Ti,Ta,Cu及Al,或任何其他合适的材料。如第15A及图15B所示,导电性接触70缠绕源/漏极磊晶层55。
图16A及图16B是根据本揭露的另一实施例,绘示半导体元件制造过程中不同阶段中的一个阶段。
如图16A所示,多层阻障半导层52与图1C所示的第一扩散半导体层103,105及107相同,其形成于凹陷化源/漏极区的内表面。图16B绘示形成源/漏极磊晶层55之后的结构。
图17A至图19B是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。须知可以提供额外的操作于图17A至图19B所绘示的制程之前、之中、之后,以及以上所述的操作可以被置换或删除,在额外的实施例中,这些操作/制程的次序为可互换。
在此实施例中,源/漏极磊晶层57不具有菱形或六边形的形状,但也不具有平顶形状。
图17A至图17C是根据本揭露的一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图17A是为对应图17B中直线X1-X1的剖面图。图17C是为对应图17B中直线Y1-Y1的剖面图。
形成阻障半导层50之后,形成一或多个源/漏极磊晶层57于阻障半导层50上如图17A和图17B所示。在一些实施例中,源/漏极磊晶层57具有相同或类似以上所述的源/漏极磊晶层55的组成成份。
可通过有机金属化学气相沉积法(MOCVD),分子束磊晶法(MBE),ALD或任何其他成膜方法,磊晶形成源/漏极磊晶层57(例如,Ge:P或SiGe:P)于阻障半导层50上。在一些实施例中,气体Ge2H6作为Ge的来源气体。在一些实施例中,气体Si2H6作为Si的来源气体。在特定实施例中,替代或除此之外,使用Ge2H6及/或Si2H6,GeH4及/或SiH4。可利用一或多种惰性气体作为稀释气体例如,H2,He,Ar及/或N2。
磊晶形成Ge:P层或SiGe:P层时,维持基板温度于约至350℃至410℃的范围。在一些实施例中,这个基板温度为热板或晶圆夹/座的温度。在其他实施例中,基板温度范围约至380℃至约400℃。当使用气体Ge2H6及/或气体Si2H6时,可在低于约400℃的较低温度下磊晶形成Ge或SiGe层57。可从阻障半导层50选择性形成源/漏极磊晶层57,且其不形成于ILD层60的上表面。磷的掺杂气体为PH3,砷的掺杂气体为AsH3或硼的掺杂气体为B2H6。在一些实施例中,沉积后的源/漏极磊晶层57具有不平坦表面。
形成源/漏极磊晶层57之后,选择性地执行热退火操作来平整化源/漏极磊晶层57的表面如图17A和图17B所示。在一些实施例中,在介于约至410℃至约470℃的一温度下将基板加热以执行热退火操作。在其他实施例中,其温度范围约至440℃至约460℃。在一些实施例中,执行热退火操作于时间范围约至100sec至约至500sec。在其他实施例中,其时间范围约至250秒至约至350秒.在一些实施例中,执行热退火操作于相同的制造装置,特别是与形成源/漏极磊晶层57相同的处理室中。在特定实施例中,当用于磊晶成长的气体制程停止之后,然后增加基板温度至退火温度。因此,执行退火操作而未将基板(源/漏极磊晶层)暴露于大气环境,特别是暴露于含氧环境。在一些实施例中,执行退火操作时,提供惰性气体例如H2,He,Ar及/或N2。由于执行退火操作,源/漏极磊晶层57的上表面实质上变得平坦。
在特定实施例中,执行激光退火操作以平整化导电性接触70。在此状况下,激光束只选择性用于源/漏极区而避开栅极结构。在一些实施例中,加热源/漏极磊晶层至约800℃至约1000℃。在一些实施例中,执行激光退火操作时间长度约0.1nsec至1000nsec。在一些实施例中,其操作时间长度约1nsec至100nsec。
图17D绘示当形成三层阻障半导层52之后和平整化操作之后的剖面图。
图18A至图18B是根据本揭露的另一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图18A是为对应图18B中直线Y1-Y1的剖面图。
类似图18A至图18B所示,利用一或多个光刻和蚀刻操作形成图案化ILD层60,从而形成源/漏极开口61。在源/漏极开口61中,形成源/漏极磊晶层57于露出的鳍状结构20上。
图19A至图19B是根据本揭露的另一个实施例,绘示包含鳍式场效晶体管的半导体元件制造过程中不同阶段中的一个阶段,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图19A是为对应图19B中直线Y1-Y1的剖面图。
类似于图15A至图15B,形成源/漏极开口61之后,形成导电性接触70如图19A和图19B所示。
在一些实施例中,形成虚设栅极结构40之后及形成源/漏极磊晶层57之前,形成ILD层60,接着图案化ILD层60以产生开口于源/漏极区上。然后,形成源/漏极磊晶层57其具有平坦上顶部。接着,形成第二ILD层60以保护源/漏极磊晶层57,以及执行栅极置换操作。
图20是根据本揭露的另一个实施例,绘示包含鳍式场效晶体管的半导体元件的剖面图,此鳍式场效晶体管具有位于源/漏极区的阻障半导体层。图20是沿着栅极延伸的方向的剖面图。
在此实施例中,形成额外的59于源/漏极磊晶层58上,其形成于阻障半导层50或52上。源/漏极磊晶层58与源/漏极磊晶层55或57有相同的组成。在一些实施例中,额外的源/漏极磊晶层59由SiwGe1-w制成,其中0.7≤w≤1.0。在特定实施例中,额外的源/漏极磊晶层59由Si制成。在一些实施例中,额外的源/漏极磊晶层59有掺杂P。P含量介一范围约1×1019atoms/cm3至1×1020atoms/cm3,在其他实施例中,其范围约5×1019atoms/cm3至8×1019atoms/cm3。
图21A至图26B是根据本揭露的一个实施例,绘示包含GAA FETs的半导体元件的制造过程,此GAA FETs具有位于源/漏极区的阻障半导体层。须知可以提供额外的操作于图21A至图26B所绘示的制程之前、之中、之后,以及以上所述的操作可以被置换或删除,在额外的实施例中,这些操作/制程的次序为可互换。
图21A至图21B是根据本揭露的另一个实施例,绘示包含GAA FETs的半导体元件制造过程中不同阶段中的一个阶段,此GAA FETs具有位于源/漏极区的阻障半导体层。图21A是为对应图21B中直线Y1-Y1的剖面图。
如图21A所示,第一半导体层120和第二半导体层125交互堆叠于基板10上。在一个实施例中,基板10由Ge制成或基板10的表面具有一层Ge,在其他实施例中,基板10由SixGe1-x制成,其中0<x≤0.3,或基板10的表面具有一层SixGe1-x。
在一些实施例中,第一半导体层120为Ge或SixGe1-x,其中0<x≤0.3,以及第二半导体层125为Si或SivGe1-v,其中0.5<v<1.0。可通过CVD,MBE,ALD或者其他合适的方法磊晶形成第一半导体层120和第二半导体层125。在一些实施例中,形成缓冲层在基板10上。
通过类似于图2A至图4B所述操作,形成鳍状结构其从第一隔离绝缘层30突出如图22A至图22B所示。图22A是为对应图22B中直线Y1-Y1的剖面图。
如图22A所示,鳍状结构包含数层交互堆叠的第一半导体层120及第二半导体层125。即使图22A绘示二个第一半导体层120和二个第二半导体层125,第一半导体层和第二半导体层的数目可以为一,三或大于三,最多为十。
通过类似于图5A至图9C所述操作,形成虚设栅极结构40,其包含形成虚设栅极介电层41和虚设栅极电极层42,以及形成侧壁间隔物45。接着,凹陷化鳍状结构的源/漏极区,以及形成阻障半导层50于源/漏极区的内表面上如图23A和图23B所示。图23A是为对应图23B中直线X1-X1的剖面图。
接着,类似于图10A至图12B所述操作,分别地形成ILD层60和栅极开口48,其中露出鳍状结构121的上部分如图24A和图24C所示。图24A是为对应图24B中直线X1-X1的剖面图。图24C是为对应图24B中直线Y2-Y2的剖面图。
形成栅极开口48之后,移除栅极开口48中的第二半导体层125如图25A和图25B所示。图25A是为对应图25B中直线Y2-Y2的剖面图。可使用湿蚀刻剂选择性移除第二半导体层125,例如,但不设于此,氢氧化铵(NH4OH),氢氧化四甲基铵(TMAH),乙二胺邻苯二酚(EDP)或氢氧化钾(KOH)溶液。由此,半导体导线由第一半导体层120形成。
接着,通过类似于图13A至图13B所述操作,形成栅极结构其具有栅极介电层62和栅极电极层65,且形成缠绕第一半导体层120如图26A和图26B所示。图26A是为对应图26B中直线Y2-Y2的剖面图。
再来,通过类似于图14A至图15B所述操作,形成导电性接触70。
须知FinFET和GAA FET经历更进一步的CMOS工艺以形成各种特征,例如接触/通孔,互连金属层,介电层,钝化层等。
本文描述的各种实施例或示例提供优于现有技术的若干优点。举例来说,本揭露使用一个扩散阻障层。可抑制杂质(例如:P)从磊晶层扩散至鳍状结构的通道区。其扩散阻障层可为一个薄硅层或富含硅层,其硅含量高于源/漏极区(鳍状结构)及/或其上形成的磊晶层。由此在FinFET或GAAFET,可能得到较低漏电流,较高的载子流动率,降低介质泄滞及/或更高的可靠性。薄扩散阻障层可以有效的抑制其他种杂质扩散,例如As,Sb及/或B。除了FinFET和GAAFET外,具有以上所述的扩散阻障层的源/漏极结构可以应用于平面FET或其他FET。
须知并非所有优点都已在本文中讨论,所有实施例或示例不需要求特定优点,以及其他实施例或示例可能提供不同的优点。
在另一例示性态样中,一种制造半导体元件的方法,形成栅极结构于鳍状结构上。凹陷化鳍状结构的源/漏极区。形成第一半导体层在凹陷化的源/漏极区上。形成第二半导体层于第一半导体层上。鳍状结构由SixGe1-x制成,其中0≤x≤0.3,第一半导体层由SiyGe1-y制成,其中0.45≤y≤1.0,第二半导体层由SizGe1-z制成,其中0≤z≤0.3。在前述或以下一或多个实施例中,鳍状结构由Ge制成,第二半导体层由Ge制成。在前述或以下一或多个实施例中,第一半导体层由Si制成。在前述或以下一或多个实施例中,0.5≤y≤1.0。在前述或以下一或多个实施例中,第一半导体层的厚度范围介于0.2nm至0.8nm。在前述或以下一或多个实施例中,鳍状结构由未掺杂的Ge制成。在前述或以下一或多个实施例中,第二半导体层由掺杂有磷的Ge制成。在前述或以下实施方案中的一个或多个中,磷的浓度范围介于5×1019atoms/cm3至1×1020atoms/cm3。在前述或以下一或多个实施例中,第二半导体层由掺杂硼的Ge制成。在前述或以下一或多个实施例中,进一步形成第三半导体层于第二半导体层上。在前述或以下一或多个实施例中,第三半导体层由SiwGe1-w制成,其中0.7≤w≤1.0。
在另一例示性态样中,一种制造半导体元件的方法,形成栅极结构于鳍状结构上。凹陷化鳍状结构的源/漏极区。形成第二阻障半导体层于第一阻障半导体层上。形成第三阻障半导体层于第二阻障半导体层上。形成第二半导体层于第三阻障半导体层上。第一阻障半导体层的厚度范围介于0.2nm至0.8nm,第二阻障半导体层的厚度范围介于0.2nm至0.8nm,并且第三阻障半导体层的厚度范围介于0.2nm到0.8nm。在前述或以下一或多个实施例中,鳍状结构由SixGe1-x制成,其中0≤x≤0.3,第二半导体层由SizGe1-z制成,其中0≤z≤0.3,以及第一阻障半导体层以及该第三阻障半导体层是由一种不同于鳍状结构以及该第二半导体层的半导体材料制成。在前述或以下一或多个实施例中,第一阻障半导体层由Siy1Ge1-y1制成,其中0.2≤y1≤0.7,第二阻障半导体层由Siy2Ge1-y2制成,其中0.5≤y2≤1.0,第三阻障半导体层由Siy3Ge1-y3制成,其中0.2≤y3≤0.7,并且y1>x,y2>y1,y2>y3,并且y3>z。在前述或以下一或多个实施例中,鳍状结构由Ge制成,第二半导体层由Ge制成。在前述或以下一或多个实施例中,第二阻障半导体层由Si制成,并且0.4≤y1且y3≤0.6。在前述或以下一或多个实施例中,鳍状结构由未掺杂的Ge制成。在前述或以下一或多个实施例中,第二半导体层由掺杂磷的Ge制成。在前述或以下实施方案中的一个或多个中,磷的浓度范围介于5×1019atoms/cm3至1×1020atoms/cm3。
在另一例示性态样中,一种制造半导体元件的方法,形成栅极结构于鳍状结构上。凹陷化鳍状结构的源/漏极区。形成磊晶半导体层于阻障半导体层上。阻障半导体层的厚度范围介于0.2nm至0.8nm,并且阻障半导体层于450℃时,其磷的扩散系数小于1×10-21cm2/s。
在另一例示性态样中,一半导体元件包含栅极结构,其设置在通道半导体层上,一源/漏极区设置在通道半导体层一侧上,第一磊晶半导体层设置在设置在源极/漏极区上,第二磊晶半导体层设置在第一磊晶半导体层上,导电接触孔设置在第二磊晶半导体层上,以及一介电层具有一开口且该导电接触孔填于该开口。在前述或以下一或多个实施例中,半导体器件另包含隔离绝缘层,介电层设置在隔离绝缘层上。第一磊晶层设置在隔离绝缘层和介电层之间的界面下方。在前述或以下一或多个实施例中,沟道半导体层由SixGe1-x制成,其中0≤x≤0.3,第一磊晶半导体层由SiyGe1-y制成,其中0.45≤y≤1.0,并且第二磊晶半导体层由SizGe1-z制成,其中0≤z≤0.3。在前述或以下一或多个实施例中,通道半导体层和源/漏极区由Ge制成,第二磊晶半导体层由Ge制成。在前述或以下一或多个实施例中,第一磊晶半导体层由Si制成。在前述或以下实施方案中的一个或多个中,0.5≤y≤1.0。在前述或以下一或多个实施例中,第一磊晶半导体层的厚度范围介于0.2nm至0.8nm。在前述或以下实施方案中的一个或多个中,源/漏极区的杂质浓度小于1×1018atoms/cm3。在前述或以下一或多个实施例中,第二磊晶半导体层由掺杂磷的Ge制成。在前述或以下实施方案中的一个或多个中,磷的浓度范围介于5×1019atoms/cm3至1×1020atoms/cm3。在前述或以下一或多个实施例中,第二磊晶半导体层由掺杂硼的Ge制成。
在另一例示性态样中,一半导体元件包含栅极结构,其设置在通道半导体层上,一源/漏极区设置在通道半导体层一侧上,第一阻障半导体层设置在源极/漏区上,第二阻障半导体层设置在第一阻障半导体层上,第三阻障半导体层设置在第二阻障半导体层上,第二磊晶半导体层设置在第三阻障半导体层上,导电接触孔设置在第二磊晶半导体层上,以及一介电层具有一开口且该导电接触孔填于该开口。在前述或以下实施方式中的一个或多个中,第一阻障半导体层的厚度范围介于0.2nm至0.8nm,第二阻障半导体层的厚度范围介于0.2nm至0.8nm,并且第三阻障半导体层的厚度范围介于0.2nm至0.8nm。在前述或以下一或多个实施例中,沟道半导体层由SixGe1-x制成,其中0≤x≤0.3,第二磊晶半导体层由SizGe1-z制成,其中0≤z≤0.3,以及第一阻障半导体层和第三阻障半导体层由与鳍状结构和第二半导体层不同的半导体材料制成。在前述或以下一或多个实施例中,第一阻障半导体层由Siy1Ge1-y1制成,其中0.2≤y1≤0.7,第二阻障半导体层由Siy2Ge1-y2制成,其中0.45≤y2≤1.0,第三阻障半导体层由Siy3Ge1-y3制成,其中0.2≤y3≤0.7,并且y1>x,y2>y1,y2>y3,并且y3>z。在前述或以下一或多个实施例中,通道半导体层由Ge制成,第二磊晶半导体层由Ge制成。在前述或以下一或多个实施例中,第二阻障半导体层由Si制成,并且0.4≤y1且y3≤0.6。在前述或以下一或多个实施例中,通道半导体层由未掺杂的Ge制成。在前述或以下一或多个实施例中,第二磊晶半导体层由掺杂磷的Ge制成。
在另一例示性态样中,一半导体元件包含栅极结构,其设置在通道半导体层上,一源/漏极区设置在通道半导体层一侧上,第一磊晶半导体层设置在源极/漏极区上,第二磊晶半导体层设置在第一磊晶半导体层上,导电接触孔设置在第二磊晶半导体层上,以及一介电层具有一开口且该导电接触孔填于该开口。第一磊晶半导体层的厚度范围介于0.2nm至0.8nm,并且第一磊晶半导体层于450℃时磷的扩散系数小于1×10-21cm2/s。
前述内容概述了许多实施例或示例的特征,使本技术领域中具有通常知识者可以从各方面更佳了解本揭露。本技术领域中具有通常知识者应可理解,且轻易地以本揭露为基础来设计或修饰其他制程和结构,并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中具有通常知识者也应理解这些相等的结构并未背离本揭露的发明精神与范围。在不背离本揭露的发明精神和范围的情况下,可对本揭露进行各种改变,替换和变更。
Claims (16)
1.一种半导体元件制造方法,其特征在于,该方法包含:
形成一鳍状结构;
形成一绝缘材料层使得该鳍状结构的上表面从该绝缘材料层凸出;
形成一栅极结构在该鳍状结构的一通道区域上;
凹陷化该鳍状结构的一源/漏极区,以形成一凹陷露出该通道区域的一侧表面;
在凹陷化该鳍状结构的该源/漏极区之后,形成一第一阻障半导体层于该凹陷的一底部与一侧壁上,包含将第一阻障半导体层形成于该通道区域的该侧表面;以及
形成一第二半导体层于该第一阻障半导体层之上,其中:
该第二半导体层的一下部部分嵌入该绝缘材料层且与该绝缘材料层直接接触,而该第二半导体层的一上部部分从该绝缘材料层凸出,
该鳍状结构是由SixGe1-x制成,其中0≤x≤0.3,
该第一阻障半导体层是由Si制成,其中该第一阻障半导体层的厚度范围介于0.2nm至0.8nm,以及
该第二半导体层是由SizGe1-z制成,其中0≤z≤0.3。
2.根据权利要求1所述的半导体元件制造方法,其特征在于,该鳍状结构是由Ge制成,以及该第二半导体层是由Ge制成。
3.根据权利要求1所述的半导体元件制造方法,其特征在于,该鳍状结构由未掺杂的Ge制成。
4.根据权利要求1所述的半导体元件制造方法,其特征在于,该第二半导体层由掺杂有磷的Ge制成。
5.根据权利要求4所述的半导体元件制造方法,其特征在于,磷的浓度范围介于5×1019atoms/cm3至1×1020atoms/cm3。
6.根据权利要求1所述的半导体元件制造方法,其特征在于,该第二半导体层由掺杂硼的Ge制成。
7.根据权利要求1所述的半导体元件制造方法,其特征在于,进一步形成一第三半导体层于该第二半导体层上。
8.根据权利要求7所述的半导体元件制造方法,其特征在于,该第三半导体层由SiwGe1-w制成,其中0.7≤w≤1.0。
9.一种半导体元件制造方法,其特征在于,该方法包含:
形成一栅极结构于一鳍状结构之上;
凹陷化该鳍状结构的一源/漏极区;
形成一第一阻障半导体层于该源/漏极区之上;
形成一第二阻障半导体层于该第一阻障半导体层之上;
形成一第三阻障半导体层于该第二阻障半导体层之上;
形成一源/漏极磊晶半导体层于该第三阻障半导体层之上,
其中:
该第一阻障半导体层的一厚度范围介于0.2nm至0.8nm,
该第二阻障半导体层的一厚度范围介于0.2nm至0.8nm,
该第三阻障半导体层的一厚度范围介于0.2nm至0.8nm,
该鳍状结构是由SixGe1-x制成,其中0≤x≤0.3,
该源/漏极磊晶半导体层是由SizGe1-z制成,其中0≤z≤0.3,
该第一阻障半导体层是由Siy1Ge1-y1制成,其中0≤y1≤0.7,
该第二阻障半导体层是由Siy2Ge1-y2制成,其中0.45≤y2≤1.0,
该第三阻障半导体层是由Siy3Ge1-y3制成,其中0.2≤y3≤0.7,以及
y1>x,y2>y1,Y2>y3,且y3>z。
10.根据权利要求9所述的半导体元件制造方法,其特征在于,
该第一阻障半导体层以及该第三阻障半导体层是由一种不同于该鳍状结构以及该源/漏极磊晶半导体层的半导体材料制成。
11.根据权利要求9所述的半导体元件制造方法,其特征在于,该鳍状结构是由Ge制成,以及该源/漏极磊晶半导体层是由Ge制成。
12.根据权利要求11所述的半导体元件制造方法,其特征在于,该第二阻障半导体层由Si制成,并且0.4≤y1且y3≤0.6。
13.根据权利要求9所述的半导体元件制造方法,其特征在于,该鳍状结构由未掺杂的Ge制成。
14.根据权利要求9所述的半导体元件制造方法,其特征在于,该源/漏极磊晶半导体层是由掺杂磷(phosphorous)的Ge制成。
15.根据权利要求14所述的半导体元件制造方法,其特征在于,该磷(phosphorous)的一浓度范围介于5×1019atoms/cm3至1×1020atoms/cm3。
16.一种半导体元件,其特征在于,包含:
一鳍状结构,该鳍状结构的一通道半导体层的上表面从一绝缘材料层凸出,该鳍状结构包含一源/漏极区凹陷以露出该鳍状结构的该通道半导体层的一侧壁;
一栅极结构设于该鳍状结构的该通道半导体层之上;
一阻障半导体层设于该源/漏极区凹陷之上;
一磊晶半导体层设于该阻障半导体层之上,在一第一方向上的剖面,该磊晶半导体层与该鳍状结构之间被该阻障半导体层所分隔,且在一第二方向上的剖面,该磊晶半导体层直接接触该绝缘材料层;
一导电接触孔设于该磊晶半导体层之上;以及
一介电层具有一开口且该导电接触孔填于该开口,其中:
该阻障半导体层包含一第一层、一第二层以及一第三层,该第二层是由一种不同于该第一层以及该第三层的材料制成,
该第二层是由Si制成,且该第二层的一厚度范围介于0.2nm至0.8nm,以及
该阻障半导体层的磷的一扩散系数于450℃时小于1×10-21cm2/s。
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