CN108122763A - 半导体元件的制造方法 - Google Patents

半导体元件的制造方法 Download PDF

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CN108122763A
CN108122763A CN201710248955.2A CN201710248955A CN108122763A CN 108122763 A CN108122763 A CN 108122763A CN 201710248955 A CN201710248955 A CN 201710248955A CN 108122763 A CN108122763 A CN 108122763A
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fin structure
layer
fin
ditches
irrigation canals
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林佑明
后藤贤
后藤贤一
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体元件的制造方法，半导体元件包括鳍状场效晶体管元件，含有突出于基材层的鳍状结构，且鳍状结构沿第一方向延伸若干长度。通道层是形成于鳍状结构上。栅极堆叠包含栅极电极层和栅极介电层，形成于通道区上并沿垂直于第一方向的第二方向延伸，且覆盖鳍状结构的部分长度。源极和漏极是形成于沟渠上，且沟渠延伸入鳍状结构至其至少30％的高度。

Description

半导体元件的制造方法
技术领域
本揭露是有关于一种半导体集成电路，且特别是有关于一种接触结构以及二维鳍状场效晶体管的制造方法。
背景技术
随着半导体工业进展至奈米科技制程节点，为追求更高的元件密度、更高的效能以及更低的成本，来自制程以及设计的挑战成就三维设计的发展，例如鳍状场效晶体管(Fin FETs)。在鳍状场效晶体管中，晶体管通道提升于平面基材上，而形成鳍状结构，栅极电极是与通道区的两侧表面和上表面相邻，且栅极介电层是设于栅极电极与通道区二者之间。
在一些场效晶体管中，至少一部分的通道区是由二维半导体围绕鳍状结构而形成。目前已知接触寄生阻抗(contact parasitic resistance)为限制以二维材料为主的元件达到高效能的主要因素，特别是当元件尺寸变小时。接触阻抗是反比于接触面积，其中接触面积在元件持续缩小的情况下会减少。对二维材料而言，接触阻抗与接触长度相关，接触长度相当于接触金属与二维材料之间周长。此外，在鳍状场效晶体管设计中，接触金属需要被填入窄沟渠中，一般而言在高幅形比时，上述制程的挑战性更高。这是因为在更先进的技术节点中，目前有增加幅形比以及缩小沟渠开口的趋势。
二维鳍状场效晶体管元件具有由三维鳍状结构所支撑的二维薄膜通道，目前已知可改善驱动电流。然而，二维鳍状场效晶体管面临类似于上述关于接触阻抗的问题。目前亟需解决方法来有效地减少接触阻抗、改善整体效能，但同时降低当元件尺寸缩小时制造接触的制程挑战，如在高幅形比的沟渠中填入金属的困难性。
发明内容
根据本揭露的一个态样，一种半导体元件的制造方法包含形成鳍状结构。虚拟栅极形成于鳍状结构的第一部分上，而间隙壁层是形成于虚拟栅极以及鳍状结构的第二部分上。介电层是形成于间隙壁层上。将形成于虚拟栅极上方的介电层和间隙壁层以及虚拟栅极本身予以移除，以暴露出鳍状结构的第一部分。栅极堆叠是形成于暴露出的鳍状结构的第一部分。移除形成于剩余部分的间隙壁层上的介电层以及介电层下方鳍状结构的一部分高度，以形成多个沟渠。接着，于所述沟渠中填入金属以形成多个源极和漏极接触。
附图说明
通过以下详细说明并配合附图阅读，可更容易理解本揭露。在此强调的是，按照产业界的标准做法，各种特征并未按比例绘制，仅为说明之用。事实上，为了清楚的讨论，各种特征的尺寸可任意放大或缩小。
图1为根据本揭露的一或多个实施例所绘示的制造二维鳍状场效晶体管元件的示意流程图；
图2A至图2O为根据本揭露的一或多个实施例所述的制造二维鳍状场效晶体管的制程所绘示的二维示意图；
图3A至图3F为根据本揭露的一或多个实施例所绘示的二维鳍状场效晶体管的详细结构；
图4A至图4C为根据本揭露的一或多个实施例所绘示的制造二维鳍状场效晶体管元件的方法的有利特征。
具体实施方式
下面的揭露提供了许多不同的实施例或例示，用于实现本揭露的不同特征。部件和安排的具体实例描述如下，以简化本揭露的揭露。当然，这些是仅仅是例示并且不意在进行限制。例如，在接着的说明中叙述在第二特征上方或上形成第一特征可以包括在第一和第二特征形成直接接触的实施例，并且还可以包括以一附加特征形成于第一和第二特征之间的实施例，从而使得第一和第二特征可以不直接接触。此外，本公开可以在各种例示重复元件符号和/或字母。这种重复是为了简化和清楚的目的，并不在本身决定所讨论的各种实施例和/或配置之间的关系。
此外，空间相对术语，如“之下”、“下方”、“低于”、“上方”、“高于”等，在本文中可以用于简单说明如图中所示元件或特征对另一元件(多个)或特征(多个特征)的关系。除了在附图中描述的位向，空间相对术语意欲包含元件使用或步骤时的不同位向。元件可以其他方式定位(旋转90度或者在其它方位)，并且本文中所使用的相对的空间描述，同样可以相应地进行解释。
图1为根据本揭露的一或多个实施例所绘示的制造二维鳍状场效晶体管元件的示意流程图100。流程图100仅绘示整体制程的相关部分。可以了解的是，在图1所示的操作前、中以及后可加入额外的操作，且在其他实施例的方法中，下述所提的一些操作可被取代或删除。操作或制程的顺序也可相互交换。
在图1的操作S101中，鳍状结构205是形成于基材202上，如图2A所示的Y剖面200A。在一些实施例中，基材可例如为p型硅基材，上述p型硅基材可具有约1×1015cm-3至约3×1015cm-3的杂质浓度。在其他实施例中，基材为n型硅基材，上述n型硅基材可具有约1×1015cm-3至约3×1015cm-3的杂质浓度。在一些实施例中，硅基材具有晶向为(100)的上表面。
基材亦可包含如锗的其他元素半导体、如碳化硅(SiC)和硅锗(SiGe)的第四族化合物半导体，以及砷化镓(GaAs)、磷化镓(GaP)、氮化镓(GaN)、磷化铟(InP)、砷化铟(InAs)、锑化铟(InSb)、砷磷化镓(GaAsP)、氮化铝镓(AlGaN)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GalnP)及/或磷砷化铟镓(GaInAsP)，或上述的组合的第III族-第V族化合物半导体等的化合物半导体。在一或多个实施例中，基材为绝缘层上覆硅(silicon-on-insulator；SOI)基材的硅层。如非晶硅或非晶碳化硅的非晶基材，或如二氧化硅的绝缘材料也可被用以做为基材。基材可包括各种区域，其可经杂质(例如p型或n型导电性)适当地掺杂。
鳍状结构205是以公知方法形成鳍片204，且鳍片204的材料与基材202相似。在一些实施例中，鳍片204可使用硅、二氧化硅或覆有介电材料于其上的硅。在一些态样中，介电材料可为氮化硼(BN)、氧化铝和二氧化铪的一者或其他介电材料。在一些实施例中，如图2B的剖面200B(例如沿图2A的剖线AA’)所示，鳍片204可具有例如为约10nm至100nm的高度H。在一些实施例中，如图2A的Y剖面200A所示，鳍片204的宽度t为约1nm至约20nm。
鳍状结构205包括鳍片204以及通道层206，其中通道层206是形成于鳍片204上。在一些实施例中，如Y剖面200A和X剖面200B所示，通道层206为以二维材料形成的二维通道(2D channel)。二维材料的例子包含石墨烯、黑磷、硼烯(borophene)、硅烯(silicone)、锗烯(germanene)以及其类似物，如碳、磷、硼、硅、锗等基础元素的二维同素异形体。其他二维材料包括一种以上的元素，如过渡金属二硫族化合物，其中过渡金属原子(例如钼、钨、铪、锆)是夹在硫族元素的原子(例如硫、硒、鍗)之间，以形成二维晶体，其中所述二维晶体是由三层原子共价地键结而组成。二维材料也可包括多层前述二维晶体的堆叠，其层间具有凡德瓦作用力。上述堆叠可包含相同的二维晶体层或各层不同的二维晶体层的组合。
在未来的元件中，二维材料如过渡金属二硫族化合物、石墨烯以及黑磷被视为具有前瞻性的晶体管通道材料。在一些态样中，所揭露的二维通道可为二维半导体，且二维半导体包括如二硫化钼(MoS2)的过渡金属二硫族化合物(TMD)。在一些实施例中，二维半导体可包括一或多层，且可具有约0.5nm至100nm的厚度。二维半导体的优点之一是高电子移动率(μe)或高空穴移动率(μh)，其是约1-10,000cm2/V-sec。可以了解的是，相较于具有典型厚度的二维材料膜，当大块硅晶圆裁切至低厚度(例如约2nm)时，大块硅晶圆的电子移动率或空穴移动率大幅下降。
在一些实施例中，通道层206是选择性地沉积于鳍片204上但不沉积于基材202上。如化学气相沉积(CVD)法或原子层沉积(ALD)法的各种沉积方法可用以形成通道层206。若鳍片204是以不同于基材的材料所制得，则沉积制程可为选择性的，因此通道层206的材料可选择为不附着于基材者。在鳍片204以与基材相同的材料所形成的情况中，则可形成例如薄氧化膜于鳍片204上，以适用通道层206的选择性沉积。
在图1的操作S102中，形成虚拟栅极208以覆盖鳍状结构205的第一部分，如图2C的Y剖面200C和图2D的X剖面200D(例如沿图2C的剖线AA’)所示。虚拟栅极208可包括，例如，非晶硅或其他硅化合物，且可使用公知的沉积方法沉积虚拟栅极208，公知沉积方法包括如等离子加强式化学气相沉积(PECVD)的化学气相沉积。如X剖面200D所示，虚拟栅极208覆盖鳍状结构205的第一部分，并使鳍状结构205的第二部分212暴露出来。
在图1的操作S103中，间隙壁层214是形成于虚拟栅极208和鳍状结构205的第二部分212上，如图2E的Y剖面200E和图2F的X剖面200F(例如沿图2E的剖线AA’)所示。在一些态样中，间隙壁层214为如氮化硅或碳氮化硅的适合的氮化层，但也可使用其他适合的材料。可使用公知的沉积方法来沉积间隙壁层214，例如化学气相沉积、原子层沉积或物理气相沉积。在一些实施例中，在形成间隙壁层214前，暴露出的通道层(例如二维通道层)是先进行如氯离子的掺杂。在一些实施例中，氯离子是以溶液(例如氯化铁溶液)、喷洒或浸涂的形式，导入至暴露出的通道层。上述的操作使氯离子得以附着于通道层的二维材料上，使得通道层206被掺杂或变成金属性。
在图1的操作S104中，介电层216是形成于间隙壁214上，如图2G的X剖面200G所示。在一些实施例中，介电层216为第一层间介电沉积层(ILD0)，并包含例如二氧化硅。在一些态样中，可使用如化学气相沉积、物理气相沉积或原子层沉积的公知沉积方法来沉积介电层216。
在图1的操作105中，虚拟栅极208上一部分的介电层216和间隙壁层214，以及虚拟栅极208是被移除，以暴露出被虚拟栅极208所覆盖的鳍状结构的第一部分，如图2H的X剖面200H和图2I的Y剖面200I(例如沿图2H的剖线BB’)所示。介电层216和间隙壁层214的移除是由平坦化操作来施行。
平坦化操作例如平坦化制程，包括化学机械研磨(CMP)法及/或回蚀制程，以移除形成于虚拟栅极208上一部分的介电层216与间隙壁层214，至例如图2G的线XX’所示处。在平坦化制程后，使用例如干式蚀刻法及/或湿式蚀刻法进行沟渠蚀刻，以移除虚拟栅极208。平坦化制程后的制程中元件悉如X剖面200H和Y剖面200I所示。鳍状结构205所暴露出的部分是已准备进行栅极堆叠的沉积。
在图1的操作S106中，栅极堆叠是形成于暴露出的鳍状结构205的第一部分上，如图2J的X剖面200J以及图2K的Y剖面200K(例如沿图2J的剖线CC’)所示。栅极堆叠包含形成于鳍状结构205暴露出的第一部分上的栅极电极层220以及栅极介电层218。在一些实施例中，栅极电极层220可为金属或多晶硅。栅极介电层可包括氧化硅，其是通过化学气相沉积、物理气相沉积、原子层沉积、电子束蒸镀或其他适合的制程所形成。
在一或多个实施例中，应用后栅极技术(gate-last technology)(栅极替换技术)。在后栅极技术中，形成于前述操作的栅极电极层220和栅极介电层218以取代如图2F或图2G所示的虚拟栅极，上述虚拟栅极是在图1的操作S105被移除，如图2H所示。
在一些实施例中，栅极介电层218包含一或多层的氧化硅、氮化硅、氮氧化硅或高介电常数的介电材料。上述高介电常数的介电材料包括金属氧化物。作为高介电常数的介电材料的金属氧化物的例子包括锂、铍、镁、钙、锶、钪、钇、锆、铪、铝、镧、铈、镨、钕、钐、铕、钆、铽、镝、钬、铒、铥、镱、镏的氧化物及/或上述金属氧化物的组合。在一些实施例中，栅极介电层218的厚度是约1nm至约5nm。在一些实施例中，栅极介电层218可包括由二氧化硅所形成的界面层。在其他实施例中，栅极电极层220包括单层或多层。
再者，栅极电极层220可为均匀掺杂或非均匀掺杂的掺杂的多晶硅。在一些选择性的实施例中，栅极电极层220包括如铝(Al)、铜(Cu)、钨(W)、钛(Ti)、钽(Ta)、钯(Pd)、钴(Co)、氮化钛(TiN)、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钽(TaN)、硅化镍(NiSi)、硅化钴(CoSi)的金属、其他具有与基材材料相容的功函数的导电材料，或上述的组合。可使用如原子层沉积、化学气相沉积、物理气相沉积、电镀或上述的组合等适合的制程，以形成栅极电极层220。在一些实施例中，栅极电极层220(沿X方向)的宽度可为约5奈米至约60奈米。
形成栅极堆叠后，如X剖面200J所示的制程中的元件是使用适合的罩幕层被图案化，以移除介电层216和部分的鳍状结构205，以下将详细叙述。
在图1的操作S107中，移除形成于剩余部分的间隙壁层214上的介电层216，以及介电层216下一部分的鳍状结构205，以形成沟渠240，其中所述鳍状结构205所移除的部分高度为H1，如图2L的X剖面200L以及图2M的Y剖面200M(例如沿图2L的剖线DD’)所示。上述移除的操作可通过使用干式蚀刻极/或湿式蚀刻来蚀刻沟渠而达成。沟渠240的开口是用以形成源极和漏极接触金属，以下将详细叙述。移除高度H1的鳍状结构205为主要技术，上述技术允许金属与二维通道的侧边接触。在一些实施例中，鳍状结构被移除的高度H1是鳍状结构205的高度的至少约30％，上述高度是约10nm至约100nm。因此，从鳍状结构205上被移除的高度H1至少有15nm。
在图1的操作108中，于图2L的沟渠240中填入金属，以形成源极和漏极接触222，如图2N的X剖面200N和图2O的Y剖面200P(例如沿图2N的剖线FF’)所示。特别说明的是，X剖面200N本身为图2O的剖线EE’。在一或多个实施例中，前述可被用作源极和漏极接触的金属的例子包括铝、铜、钨、钛、钽、钯、钪、镍、钴、钌、氮化钛、钛铝、氮化钛铝、氮化钽、硅化镍、硅化钴以及其他的导电材料或上述的组合。在一些实施例中，可使用例如原子层沉积、化学气相沉积、物理气相沉积或其他适合的沉积制程，以沉积源极和漏极接触222。在一些实施例中，在例如约150℃至650℃的温度下进行选择性的退火制程，可改善金属至通道的接触阻抗。前述的制程概念可被整合于目前的鳍状场效晶体管制程，且可于许多技术节点中施行，包括但不限于10nm、7nm以及5nm的技术节点。
图3A至图3F是根据本揭露的一或多个实施例绘示二维鳍状场效晶体管300A的详细结构。二维鳍状场效晶体管300A包括突出于基材层202上的鳍状结构205，且上述鳍状结构205沿第一方向(例如X)延伸一长度。通道层206是形成于鳍状结构205上，且栅极堆叠310包括栅极电极层220和栅极介电层218，其中栅极堆叠310是沿垂直于第一方向的第二方向(例如Y)延伸，且栅极堆叠310形成于通道层上。栅极堆叠310覆盖鳍状结构205的部分长度。通道层206为二维半导体(例如二硫化钼)的一薄层(例如具有0.5nm至10nm的厚度)。鳍状结构205的高度为约10nm至约100nm，且源极和漏极接触是形成于沟渠(例如图2L的沟渠240)上，且沟渠延伸入鳍状结构205至其至少约30％的高度。
所揭露的二维鳍状场效晶体管的优点之一在于：源极和漏极接触金属222与鳍状结构的通道层206之间的侧边接触。例如，通道层206与金属222在侧壁325上相接触，与传统的二维鳍状场效晶体管元件相比，传统者不包括使金属222延伸入鳍状结构205中(例如图2L)的沟渠(如图2L的沟渠240)。
图3A的区域320的放大视图300B悉如图3B所示。放大视图300B描绘源极和漏极接触金属222和二维材料324(例如二硫化钼)之间的侧边接触。如图所示，接触金属222与二硫化钼材料的分子键结。相较于传统的上接触式的二维鳍状场效晶体管，传统者不包括使金属222延伸入鳍状结构205(例如图2L)的沟渠(如图2L的沟渠240)中，侧边接触使得接触阻抗得以改善。二维材料324可具有约1至10,000cm2/Vsec的电荷载体(例如电子)移动率(μe)，且可在低厚度时维持高移动率。应可了解的是，大块硅晶圆的厚度小于约5nm时，其电荷载体移动率大幅下降(约50％)。
立体图(三维图)300C是绘示于图3C，其包含鳍状结构的剖面图，以表示金属接触形成前的鳍状结构。立体图300C绘示栅极电极层220、栅极介电层218、间隙壁层214、通道层206和鳍片204。鳍状结构的剖面图显示源极和漏极接触金属222不仅接触通道层206的底表面(例如XY平面)315，亦与通道层206的侧表面325形成接触。
在一些建构中，本揭露的主要技术可将二维通道的源极和漏极金属的接触阻抗从一般范围的1-10KΩ-μm减少至小于约100Ω-μm。要于先进技术节点中，例如小于50nm，要达成源极和漏极金属与二维通道间的低阻抗是特别困难的。然而，本揭露的解决方法并不限于特定技术节点，其可解决低特征尺寸的接触阻抗的问题。
图3D绘示X剖面300D，其是相似于鳍状场效晶体管元件300A的X剖面，显示分别如放大视图300D和300E所示的接触金属222和通道层206之间接合的二点(点330和点340)。放大视图300E为Y剖面，其绘示鳍状结构205中的沟渠侧壁上的接触，且其可见鳍状结构205的完整高度。放大视图300F为Y剖面，其绘示鳍状结构205中的沟渠的底部的接触，且其可见鳍状结构205的减少的高度342(例如减少至少约30％)。虚线335绘示鳍状结构205原本的高度。
图4A至图4C是根据本揭露的一或多个实施例绘示制造二维鳍状场效晶体管元件的方法的有利特征。Y剖面400A绘示使用传统方法建构窄间距鳍状场效晶体管元件的示范情况。由于沟渠的高幅形比(例如高/宽)，例如鳍状结构与开口侧壁之间的窄间距，在金属块件中会产生空洞410，其阻挡金属222完全地接触鳍状结构205的侧壁，因此造成接触金属和二维通道之间的有效接触长度减少。减少的接触长度导致非预定的效果，如源极和漏极接触的阻抗增加以及鳍状场效晶体管元件的不可靠度增加。
Y剖面400B是绘示使用传统方法建构窄间距鳍状场效晶体管元件的另一示范情况，其中二相邻的金属222的距离短且金属仅能接触鳍状结构的一侧。上述情况造成金属222与鳍状结构的二通道间的接触长度更加减短。
Y剖面400绘示如图2O所示的用以形成源极和漏极金属接触的相对应开口420的主要技术。开口420允许源极和漏极金属与二维通道之间的完全接触，且因为鳍状结构的高度减少(例如减少至少30％)，故于减少高度的鳍状结构430的侧边上形成具有较低的幅形比的开口，从而允许填入金属222时不产生如空洞的缺陷。再者，所述主要技术可增加金属222和二维通道(例如通道层206)之间的接触长度，如上图3A所绘示与说明。
需要了解的是，此处并未提及所有的优点，并非所的有实施例或例子皆具有特定优点，且其他实施例或例子可能提供不同的优点。
根据本揭露的一个态样，一种半导体元件的制造方法包含形成鳍状结构。虚拟栅极是形成于鳍状结构的第一部分上，而间隙壁层是形成于虚拟栅极以及鳍状结构的第二部分上中。形成于虚拟栅极上方的介电层和间隙壁层以及虚拟栅极本身是被移除，以暴露出鳍状结构的第一部分。栅极堆叠是形成于暴露出的鳍状结构的第一部分。移除形成于剩余部分的间隙壁层上的介电层，以及介电层下方鳍状结构的一部分高度，以形成沟渠。接着，于沟渠中填入金属以形成源极和漏极接触。
在一些实施例中，鳍状结构以及虚拟栅极是形成于间隙壁层形成前，且形成鳍状结构的操作包含于基材的鳍片上形成二维通道，且二维通道包含二维材料。二维材料包含二维半导体，二维半导体包含黑磷、石墨烯或如硫化钼(MoS2)的过渡金属二硫族化合物(transition metal dichalcogenide；TMD)。
在一些实施例中，上述形成二维通道的操作包含使用化学气相沉积(chemical-vapor deposition；CVD)法或原子层沉积(atomic-layer deposition；ALD)法中的一者的一选择性沉积，且其中所述二维通道的厚度实质为0.5nm至10nm。
在一些实施例中，鳍片与基材包含相似的材料，其中基材包含硅、二氧化硅或覆有介电材料的硅中的一者，以及介电材料包含氮化硼(BN)、氧化铝或二氧化铪中的一者。
在一些实施例中，间隙壁层包含氮化硅(SiN)或碳氮化硅(SiCN)，且间隙壁层是使用化学气相沉积、原子层沉积或物理气相沉积中的一者所形成。
在一些实施例中，于形成间隙壁层前，二维通道是被掺杂氯离子。
在一些实施例中，前述介电层包含第一层间沉积层，且第一层间沉积层包含二氧化硅。
在一些实施例中，前述形成多个沟渠的操作包含移除介电层下方鳍状结构至其所述高度的实质至少30％。
在一些实施例中，所述鳍状结构的高度实质为10nm至100nm，且每一沟渠的宽度是实质为1nm至100nm。
根据本揭露的另一态样，一种半导体元件的制造方法包含形成包括二维通道的鳍状结构。虚拟栅极是形成于鳍状结构上。虚拟栅极覆盖所述鳍状结构的一部分。间隙壁层是被形成，以覆盖虚拟栅极以及鳍状结构的暴露出的部分。形成于虚拟栅极上方的间隙壁层以及虚拟栅极是被移除，以暴露出虚拟栅极下的鳍状结构。栅极堆叠是形成于暴露出的鳍状结构上。源极和漏极的结构是通过移除鳍状结构的部分高度，以形成沟渠，从而将金属填入沟渠中以形成源极和漏极接触电极。
在一些实施例中，形成鳍状结构包含于基材上形成鳍片并选择性地形成二维通道于鳍片上。鳍片和基材包含硅、二氧化硅以及覆有介电材料的硅中的一者，且介电材料包含氮化硼(BN)、氧化铝和二氧化铪中的一者。
在一些实施例中，所述二维通道包含具有实质为0.5nm至10nm的厚度的薄层，且上述薄层是使用化学气相沉积(chemical-vapor deposition；CVD)法或原子层沉积(atomic-layer deposition；ALD)法的一者所形成的过渡金属二硫族化合物薄层。
在一些实施例中，本揭露的制造方法还包含形成介电层于所述间隙壁层上，其中前述暴露出虚拟栅极下的鳍状结构的操作还包含移除形成于间隙壁层上的介电层，且间隙壁层是形成于虚拟栅极上。
在一些实施例中，形成多个沟渠用以形成多个源极和漏极接触的操作包含：移除介电层以及介电层下的具有高度的鳍状结构的该第一部分，其中所述第一部分包含具有实质至少30％的高度的鳍状结构。
在一些实施例中，鳍状结构的高度是实质为10nm至100nm，且其中形成多个沟渠用以形成多个源极和漏极接触的操作包含形成具有实质为1nm至100nm的宽度的每一沟渠。
根据本揭露的又一态样，半导体元件包括鳍状场效晶体管元件，含有突出于基材层上的鳍状结构，且鳍状结构沿第一方向延伸若干长度。通道层是形成于鳍状结构上。栅极堆叠包含栅极电极层和栅极介电层，形成于通道区上并沿垂直于第一方向的第二方向延伸，从而覆盖鳍状结构的部分长度。源极和漏极是形成于沟渠上，且沟渠延伸入鳍状结构至其至少30％的高度。
在一些实施例中，源极和漏极接触为金属填充物，上述金属填充物是与通道层形成侧边接触。通道层包括二维半导体的薄层，且通道层的厚度约2nm。鳍状结构的高度为约50nm，且源极和漏极接触是形成于沟渠上，上述沟渠延伸入具有实质至少30％的所述高度的鳍状结构。
前述内容概述多个实施例的特征，以使在本技术领域具有通常知识者可进一步了解本揭露的态样。本技术领域具通常知识者应可轻易利用本揭露作为基础，设计或润饰其他制程及结构，借以执行此处所描述的实施例的相同的目的及/或达到相同的优点。本技术领域具有通常知识者亦应可了解，上述相等的结构并未脱离本揭露的精神和范围，且在不脱离本揭露的精神及范围下，其可经润饰、取代或替换。

Claims (1)

1.一种半导体元件的制造方法，其特征在于，包含：
在形成于一鳍状结构的一第一部分上的一虚拟栅极以及该鳍状结构的一第二部分上，形成一间隙壁层；
形成一介电层于该间隙壁层上；
移除形成于该虚拟栅极上方的该介电层和该间隙壁层以及该虚拟栅极，以暴露出该鳍状结构的该第一部分；
形成一栅极堆叠于暴露出的该鳍状结构的该第一部分上；
移除形成于该间隙壁层上的该介电层的一剩余部分以及该介电层下方的具有一高度的该鳍状结构的一部分，以形成多个沟渠；以及
将一金属填入所述多个沟渠，以形成多个源极/漏极接触。
CN201710248955.2A 2016-11-29 2017-04-17 半导体元件的制造方法 Pending CN108122763A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110957225A (zh) * 2018-09-26 2020-04-03 台湾积体电路制造股份有限公司 半导体元件及其制造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10084066B2 (en) * 2016-11-29 2018-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
KR20210094332A (ko) 2020-01-21 2021-07-29 삼성전자주식회사 2d 채널을 포함하는 트랜지스터
KR20210094330A (ko) 2020-01-21 2021-07-29 삼성전자주식회사 2차원 반도체 물질을 포함하는 반도체 소자
KR20210121948A (ko) 2020-03-31 2021-10-08 삼성전자주식회사 2차원 물질기반 배선 도전층 콘택구조, 이를 포함하는 전자소자 및 그 제조방법
KR20210154602A (ko) 2020-06-12 2021-12-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11728391B2 (en) * 2020-08-07 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. 2d-channel transistor structure with source-drain engineering

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100054448A (ko) * 2008-11-14 2010-05-25 삼성전자주식회사 반도체 소자 및 그 형성 방법
US8278703B2 (en) * 2010-02-08 2012-10-02 Micron Technology, Inc. Cross-hair cell based floating body device
US9368388B2 (en) * 2012-04-13 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for FinFETs
US9012287B2 (en) * 2012-11-14 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Cell layout for SRAM FinFET transistors
US8877592B2 (en) * 2013-03-14 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial growth of doped film for source and drain regions
US9412667B2 (en) * 2014-11-25 2016-08-09 International Business Machines Corporation Asymmetric high-k dielectric for reducing gate induced drain leakage
US9647091B2 (en) * 2015-05-01 2017-05-09 International Business Machines Corporation Annealed metal source drain overlapping the gate
US9673293B1 (en) * 2016-02-18 2017-06-06 International Business Machines Corporation Airgap spacers
US9805982B1 (en) * 2016-05-17 2017-10-31 Globalfoundries Inc. Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs
US9653464B1 (en) * 2016-09-14 2017-05-16 International Business Machines Corporation Asymmetric band gap junctions in narrow band gap MOSFET
US10084066B2 (en) * 2016-11-29 2018-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110957225A (zh) * 2018-09-26 2020-04-03 台湾积体电路制造股份有限公司 半导体元件及其制造方法
CN110957225B (zh) * 2018-09-26 2023-02-28 台湾积体电路制造股份有限公司 半导体元件及其制造方法
US11626507B2 (en) 2018-09-26 2023-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing FinFETs having barrier layers with specified SiGe doping concentration

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