CN110911291A - 一种树脂型晶圆级扇出集成封装方法及结构 - Google Patents
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Abstract
本发明公开一种树脂型晶圆级扇出集成封装方法及结构,属于集成电路封装技术领域。提供硅基,在其背面制作截止层、凸点和第一凹槽;将玻璃载板通过键合胶键合在所述硅基背面;减薄硅基正面并刻蚀第二凹槽、TSV通孔和切割槽;在TSV通孔中制作铜柱,在第二凹槽中埋入第一芯片;用干膜填充所述硅基正面的缝隙并在第一芯片的焊盘面和铜柱开口;在开口处制作第一n层再布线,将第二芯片倒装焊接在第一n层再布线上并填充第二芯片和第一n层再布线之间的空隙;用塑封料塑封硅基正面,塑封料包覆第二芯片;拆除玻璃载板并清洗键合胶,用塑封料塑封硅基背面,塑封料包覆凸点;研磨至露出凸点,制作第二n层再布线、阻焊层和焊球,最后切割完成最终封装。
Description
技术领域
本发明涉及集成电路封装技术领域,特别涉及一种树脂型晶圆级扇出集成封装方法及结构。
背景技术
在树脂型晶圆级扇出集成封装中,翘曲一直以来都是阻碍其发展的重要问题之一。重构圆片塑封后,由于芯片硅基与树脂材料CTE(coefficient of thermal expansion,热膨胀系数)相差较大,必然会产生一定翘曲。重构圆片翘曲的主要影响有两方面:一是对套刻精度的影响,圆片翘曲后,各I/O位置发生了事实上的偏移,这导致无法同时对准;二是圆片的翘曲导致圆片无法进行全自动机台的自动传片、上下料作业,因为翘曲的圆片非常容易被机械手臂叉碎,无法自动作业对于产业化来说是很致命的。
申请号为201910870925.4的专利将硅基扇出与塑封技术结合在一起实现了多芯片的三维晶圆级扇出,但是当再布线层数或塑封厚度较大时会产生较大的翘曲,增加流片难度。因此,如何解决树脂型圆片的翘曲问题是树脂型晶圆级扇出集成封装技术进一步向前发展的关键。
发明内容
本发明的目的在于提供一种树脂型晶圆级扇出集成封装方法及结构,以解决目前树脂型圆片存在翘曲缺陷的问题。
为解决上述技术问题,本发明提供一种树脂型晶圆级扇出集成封装方法,包括:
提供硅基,在其背面制作截止层、凸点和第一凹槽;
将玻璃载板通过键合胶键合在所述硅基背面;
减薄硅基正面并刻蚀第二凹槽、TSV通孔和切割槽;在TSV通孔中制作铜柱,在第二凹槽中埋入第一芯片;
用干膜填充所述硅基正面的缝隙并在第一芯片的焊盘面和铜柱开口;
在开口处制作第一n层再布线,将第二芯片倒装焊接在第一n层再布线上并填充第二芯片和第一n层再布线之间的空隙;
用塑封料塑封硅基正面,塑封料包覆第二芯片;
拆除玻璃载板并清洗键合胶,用塑封料塑封硅基背面,塑封料包覆凸点;
研磨至露出凸点,制作第二n层再布线、阻焊层和焊球,最后切割完成最终封装。
可选的,所述截止层的材料为SiO2、SiC和SiN中的一种或几种,厚度在0.1μm以上;
所述凸点为铜柱或锡球,其高度在5μm以上。
可选的,所述第一凹槽通过机械切割或干法刻蚀制作,所述第一凹槽的深度和宽度均在5μm以上。
可选的,所述第二凹槽和所述TSV通孔刻蚀至所述截止层,所述切割槽刻蚀至所述键合胶。
可选的,通过光刻、电镀工艺在TSV通孔中制作铜柱,铜柱与凸点间的截止层用激光或干法刻蚀方法打开,使所述铜柱与所述凸点相连。
可选的,所述第一芯片通过粘结胶粘结在所述第二凹槽中,所述第一芯片的焊盘面朝外;其中,所述粘结胶和所述干膜均为高分子材料。
可选的,通过底填料填充所述第二芯片和所述第一n层再布线之间的空隙;所述底填料和所述塑封料均为高分子材料。
本发明还提供了一种树脂型晶圆级扇出集成封装结构,包括硅基,
所述硅基背面依次制作有截止层、凸点和第一凹槽;正面刻蚀有第二凹槽、TSV通孔和切割槽,所述第二凹槽中制作有铜柱,所述TSV通孔中埋有第一芯片;
所述第一芯片的正面填充有干膜,并制作有第一n层再布线;所述第一芯片通过所述第一n层再布线与第二芯片连接;
所述硅基背面通过塑封料塑封,并依次制作第二n层再布线、阻焊层和焊球,所述第二n层再布线与所述凸点相连。
可选的,所述树脂型晶圆级扇出集成封装结构正面塑封有塑封料,所述塑封料包覆所述第二芯片。
可选的,所述第二芯片和所述第一n层再布线之间填充有底填料。
在本发明中提供了一种树脂型晶圆级扇出集成封装方法及结构,提供硅基,在其背面制作截止层、凸点和第一凹槽;将玻璃载板通过键合胶键合在所述硅基背面;减薄硅基正面并刻蚀第二凹槽、TSV通孔和切割槽;在TSV通孔中制作铜柱,在第二凹槽中埋入第一芯片;用干膜填充所述硅基正面的缝隙并在第一芯片的焊盘面和铜柱开口;在开口处制作第一n层再布线,将第二芯片倒装焊接在第一n层再布线上并填充第二芯片和第一n层再布线之间的空隙;用塑封料塑封硅基正面,塑封料包覆第二芯片;拆除玻璃载板并清洗键合胶,用塑封料塑封硅基背面,塑封料包覆凸点;研磨至露出凸点,制作第二n层再布线、阻焊层和焊球,最后切割完成最终封装。本发明通过在硅基正反面进行预切割,同时运用临时键合技术,完成硅基正面和背面的塑封工艺,形成三明治结构,大大降低了圆片翘曲。本发明提供的方法可以被大规模应用在量产中,提高生产效率,提高封装成品率。
附图说明
图1是本发明提供的树脂型晶圆级扇出集成封装方法流程示意图;
图2是在硅基背面制作截止层、凸点的示意图;
图3是在硅基背面刻蚀第一凹槽的示意图;
图4是在硅基背面键合玻璃载板的示意图;
图5是在硅基正面刻蚀第二凹槽、TSV通孔和切割槽的示意图;
图6是在TSV通孔中制作铜柱的示意图;
图7是在第二凹槽中埋入第一芯片的示意图;
图8是用干膜填充硅基正面缝隙的示意图;
图9是将第二芯片通过第一n层再布线与第一芯片连接的示意图;
图10是用塑封料包覆硅基正面的示意图;
图11是拆除玻璃载板、清洗干净键合胶的示意图;
图12是用塑封料塑封硅基背面的示意图;
图13是研磨硅基背面的塑封料至露出凸点的示意图;
图14是在硅基背面形成第二n层再布线、阻焊层和焊球的示意图;
图15是切割形成最后封装的示意图。
具体实施方式
以下结合附图和具体实施例对本发明提出的一种树脂型晶圆级扇出集成封装方法及结构作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
实施例一
本发明提供了一种树脂型晶圆级扇出集成封装方法,其流程如图1所示,包括如下步骤:
提供硅基,在其背面依次制作截止层、凸点和第一凹槽;
将玻璃载板通过键合胶键合在所述硅基背面;
减薄硅基正面并刻蚀第二凹槽、TSV通孔和切割槽;在TSV通孔中制作铜柱,在第二凹槽中埋入第一芯片;
用干膜填充所述硅基正面的缝隙并在第一芯片的焊盘面和铜柱开口;
在开口处制作第一n层再布线,将第二芯片倒装焊接在第一n层再布线上并填充第二芯片和第一n层再布线之间的空隙;
用塑封料塑封硅基正面,塑封料包覆第二芯片;
拆除玻璃载板并清洗键合胶,用塑封料塑封硅基背面,塑封料包覆凸点;
研磨至露出凸点,制作第二n层再布线、阻焊层和焊球,最后切割完成最终封装。
首先提供硅基101,在其背面依次制作截止层102、凸点103,如图2所示;其中,所述截止层102的材料为SiO2、SiC和SiN中的一种或几种,厚度在0.1μm以上,所述凸点103为铜柱或锡球,其高度在5μm以上;
通过机械切割或干法刻蚀制作第一凹槽104,如图3所示;所述第一凹槽104的深度和宽度都在5μm以上;
之后进行临时键合工艺,将玻璃载板106通过键合胶105键合在所述硅基101背面,如图4;
如图5所示,通过研磨或刻蚀工艺减薄所述硅基101正面至目标厚度,然后刻蚀第二凹槽107a、TSV通孔107b和切割槽107c;其中,所述第二凹槽107a和所述TSV通孔107b刻蚀至所述截止层102,所述切割槽107c刻蚀至所述键合胶105;至此,如图5中虚线框内所示,硅基的封装单元被划分开成为一颗颗的封装体;
通过光刻、电镀等工艺在所述TSV通孔107b中制作铜柱108,铜柱108与凸点103之间的截止层用激光或干法刻蚀方法打开,使所述铜柱108和所述凸点103相连,如图6所示;
接着在第二凹槽107a中埋入第一芯片109,所述第一芯片109通过粘结胶110与所述截止层102相连,其焊盘面111朝外,如图7所示;所述粘结胶110为高分子材料;
通过真空压干膜技术用干膜112填充所述硅基101正面的缝隙,并利用光刻技术在所述第一芯片109的焊盘面111和铜柱108的地方开口,如图8;所述干膜112为高分子材料;
通过光刻、电镀和化镀等技术在开口处制作第一n层再布线113,将第二芯片114倒装焊接在第一n层再布线113上,并用底填料115填充所述第二芯片114和所述第一n层再布线113之间的空隙;所述第二芯片114的焊盘面116朝内,如图9;所述底填料115为高分子材料;
用塑封料117塑封硅基101正面,塑封厚度大于所述第二芯片114的厚度,所述塑封料117包覆所述第二芯片114,如图10;所述塑封料117为高分子材料;
拆除所述玻璃载板106并清洗干净所述键合胶105,露出所述凸点103和所述第一凹槽104,如图11;
另外再用塑封料117塑封硅基101背面,塑封厚度大于所述凸点103,完全包覆所述凸点103,如图12;
研磨所述硅基101背面的塑封料至露出所述凸点103,如图13中虚线所示,截至此时基于硅基的封装体被完全分割开,这样可以释放由于硅基与塑封料CTE不匹配而产生的内应力,同时由于硅基正面和背面都通过塑封料塑封起来,形成三明治结构,减小了圆片的翘曲;
如图14所示,在所述硅基101背面依次制作第二n层再布线118、阻焊层119和焊球120,最后切割完成如图15所示的最终封装。
在硅基正、反面分别形成切割槽107c和第一凹槽104进行预切割,将整个硅基圆片划成一颗颗的单个封装体释放整体的内应力来降低圆片翘曲。同时通过在硅基正反面塑封和临时键合形成三明治结构,平衡硅基正面和背面的翘曲,再进一步降低圆片翘曲,完成硅基加树脂塑封的三维扇出型封装。
实施例二
本发明提供了一种树脂型晶圆级扇出集成封装结构,其结构如图14所示,包括硅基101,所述硅基101背面依次制作有截止层102、凸点103和第一凹槽;正面刻蚀有第二凹槽、TSV通孔和切割槽,所述TSV通孔中制作有铜柱108,所述第二凹槽中埋有第一芯片109,所述第一芯片109通过粘结胶110与所述截止层102相连;所述第一芯片109的正面填充有干膜112,并制作有第一n层再布线113;所述第一芯片109的焊盘面111通过所述第一n层再布线113与第二芯片114的焊盘面116连接;所述硅基101背面通过塑封料117塑封,并依次制作第二n层再布线118、阻焊层119和焊球120,所述第二n层再布线118与所述凸点103相连。
其中,所述树脂型晶圆级扇出集成封装结构正面塑封有塑封料117,所述塑封料117包覆所述第二芯片114,所述第二芯片114和所述第一n层再布线113之间填充有底填料115。通过对图14所示的封装结构进行切割形成如图15所示的最终封装。
上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。
Claims (10)
1.一种树脂型晶圆级扇出集成封装方法,其特征在于,包括:
提供硅基,在其背面制作截止层、凸点和第一凹槽;
将玻璃载板通过键合胶键合在所述硅基背面;
减薄硅基正面并刻蚀第二凹槽、TSV通孔和切割槽;在TSV通孔中制作铜柱,在第二凹槽中埋入第一芯片;
用干膜填充所述硅基正面的缝隙并在第一芯片的焊盘面和铜柱开口;
在开口处制作第一n层再布线,将第二芯片倒装焊接在第一n层再布线上并填充第二芯片和第一n层再布线之间的空隙;
用塑封料塑封硅基正面,塑封料包覆第二芯片;
拆除玻璃载板并清洗键合胶,用塑封料塑封硅基背面,塑封料包覆凸点;
研磨至露出凸点,制作第二n层再布线、阻焊层和焊球,最后切割完成最终封装。
2.如权利要求1所述的树脂型晶圆级扇出集成封装方法,其特征在于,所述截止层的材料为SiO2、SiC和SiN中的一种或几种,厚度在0.1μm以上;
所述凸点为铜柱或锡球,其高度在5μm以上。
3.如权利要求1所述的树脂型晶圆级扇出集成封装方法,其特征在于,所述第一凹槽通过机械切割或干法刻蚀制作,所述第一凹槽的深度和宽度均在5μm以上。
4.如权利要求1所述的树脂型晶圆级扇出集成封装方法,其特征在于,所述第二凹槽和所述TSV通孔刻蚀至所述截止层,所述切割槽刻蚀至所述键合胶。
5.如权利要求1所述的树脂型晶圆级扇出集成封装方法,其特征在于,通过光刻、电镀工艺在TSV通孔中制作铜柱,铜柱与凸点间的截止层用激光或干法刻蚀方法打开,使所述铜柱与所述凸点相连。
6.如权利要求1所述的树脂型晶圆级扇出集成封装方法,其特征在于,所述第一芯片通过粘结胶粘结在所述第二凹槽中,所述第一芯片的焊盘面朝外;其中,所述粘结胶和所述干膜均为高分子材料。
7.如权利要求1所述的树脂型晶圆级扇出集成封装方法,其特征在于,通过底填料填充所述第二芯片和所述第一n层再布线之间的空隙;所述底填料和所述塑封料均为高分子材料。
8.一种树脂型晶圆级扇出集成封装结构,包括硅基(101),其特征在于,
所述硅基(101)背面依次制作有截止层(102)、凸点(103)和第一凹槽;正面刻蚀有第二凹槽、TSV通孔和切割槽,所述第二凹槽中制作有铜柱(108),所述TSV通孔中埋有第一芯片(109);
所述第一芯片(109)的正面填充有干膜(112),并制作有第一n层再布线(113);所述第一芯片(109)通过所述第一n层再布线(113)与第二芯片(114)连接;
所述硅基(101)背面通过塑封料(117)塑封,并依次制作第二n层再布线(118)、阻焊层(119)和焊球(120),所述第二n层再布线(118)与所述凸点(103)相连。
9.如权利要求8所述的树脂型晶圆级扇出集成封装结构,其特征在于,所述树脂型晶圆级扇出集成封装结构正面塑封有塑封料(117),所述塑封料(117)包覆所述第二芯片(114)。
10.如权利要求8所述的树脂型晶圆级扇出集成封装结构,其特征在于,所述第二芯片(114)和所述第一n层再布线(113)之间填充有底填料(115)。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111463137A (zh) * | 2020-05-22 | 2020-07-28 | 中国电子科技集团公司第五十八研究所 | 一种硅基三维扇出集成封装方法及其结构 |
CN111696879A (zh) * | 2020-06-15 | 2020-09-22 | 西安微电子技术研究所 | 一种基于转接基板的裸芯片kgd筛选方法 |
CN114914196A (zh) * | 2022-07-19 | 2022-08-16 | 武汉大学 | 基于芯粒概念的局部中介层2.5d扇出封装结构及工艺 |
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CN115665983A (zh) * | 2022-11-14 | 2023-01-31 | 惠州市金百泽电路科技有限公司 | 一种埋置器件pcb板及其制作方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180158798A1 (en) * | 2015-11-03 | 2018-06-07 | Sj Semiconductor (Jiangyin) Corporation | Fan-Out Package Structure, And Manufacturing Method Thereof |
CN110299294A (zh) * | 2019-07-31 | 2019-10-01 | 中国电子科技集团公司第五十八研究所 | 一种三维系统级集成硅基扇出型封装方法及结构 |
CN110310895A (zh) * | 2019-07-31 | 2019-10-08 | 中国电子科技集团公司第五十八研究所 | 一种埋入tsv转接芯片硅基扇出型三维集成封装方法及结构 |
CN110379780A (zh) * | 2019-07-31 | 2019-10-25 | 中国电子科技集团公司第五十八研究所 | 一种硅基扇出型晶圆级封装方法及结构 |
CN110416091A (zh) * | 2019-07-31 | 2019-11-05 | 中国电子科技集团公司第五十八研究所 | 一种硅基扇出型封装方法及结构 |
CN110491792A (zh) * | 2019-09-16 | 2019-11-22 | 中国电子科技集团公司第五十八研究所 | 一种树脂型三维扇出集成封装方法及结构 |
CN110491853A (zh) * | 2019-09-16 | 2019-11-22 | 中国电子科技集团公司第五十八研究所 | 一种硅基三维扇出集成封装方法及结构 |
CN210805739U (zh) * | 2019-12-17 | 2020-06-19 | 中国电子科技集团公司第五十八研究所 | 一种树脂型晶圆级扇出集成封装结构 |
-
2019
- 2019-12-17 CN CN201911297394.0A patent/CN110911291A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180158798A1 (en) * | 2015-11-03 | 2018-06-07 | Sj Semiconductor (Jiangyin) Corporation | Fan-Out Package Structure, And Manufacturing Method Thereof |
CN110299294A (zh) * | 2019-07-31 | 2019-10-01 | 中国电子科技集团公司第五十八研究所 | 一种三维系统级集成硅基扇出型封装方法及结构 |
CN110310895A (zh) * | 2019-07-31 | 2019-10-08 | 中国电子科技集团公司第五十八研究所 | 一种埋入tsv转接芯片硅基扇出型三维集成封装方法及结构 |
CN110379780A (zh) * | 2019-07-31 | 2019-10-25 | 中国电子科技集团公司第五十八研究所 | 一种硅基扇出型晶圆级封装方法及结构 |
CN110416091A (zh) * | 2019-07-31 | 2019-11-05 | 中国电子科技集团公司第五十八研究所 | 一种硅基扇出型封装方法及结构 |
CN110491792A (zh) * | 2019-09-16 | 2019-11-22 | 中国电子科技集团公司第五十八研究所 | 一种树脂型三维扇出集成封装方法及结构 |
CN110491853A (zh) * | 2019-09-16 | 2019-11-22 | 中国电子科技集团公司第五十八研究所 | 一种硅基三维扇出集成封装方法及结构 |
CN210805739U (zh) * | 2019-12-17 | 2020-06-19 | 中国电子科技集团公司第五十八研究所 | 一种树脂型晶圆级扇出集成封装结构 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111463137A (zh) * | 2020-05-22 | 2020-07-28 | 中国电子科技集团公司第五十八研究所 | 一种硅基三维扇出集成封装方法及其结构 |
CN111463137B (zh) * | 2020-05-22 | 2024-05-28 | 中国电子科技集团公司第五十八研究所 | 一种硅基三维扇出集成封装方法及其结构 |
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