CN110752189B - 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品 - Google Patents

一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品 Download PDF

Info

Publication number
CN110752189B
CN110752189B CN201911014276.4A CN201911014276A CN110752189B CN 110752189 B CN110752189 B CN 110752189B CN 201911014276 A CN201911014276 A CN 201911014276A CN 110752189 B CN110752189 B CN 110752189B
Authority
CN
China
Prior art keywords
shielding
shielding material
module
emi shielding
metal particles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911014276.4A
Other languages
English (en)
Other versions
CN110752189A (zh
Inventor
李林萍
盛荆浩
江舟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huzhou Jianwenlu Technology Co Ltd
Original Assignee
Hangzhou Jianwenlu Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Jianwenlu Technology Co Ltd filed Critical Hangzhou Jianwenlu Technology Co Ltd
Priority to CN201911014276.4A priority Critical patent/CN110752189B/zh
Publication of CN110752189A publication Critical patent/CN110752189A/zh
Application granted granted Critical
Publication of CN110752189B publication Critical patent/CN110752189B/zh
Priority to EP20879295.2A priority patent/EP4036962A4/en
Priority to JP2022523920A priority patent/JP2022552897A/ja
Priority to US17/771,014 priority patent/US11770920B2/en
Priority to PCT/CN2020/114836 priority patent/WO2021077937A1/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00Screening of apparatus or components against electric or magnetic fields
    • H05K9/0073Shielding materials
    • H05K9/0081Electromagnetic shielding materials, e.g. EMI, RFI shielding
    • H05K9/0088Electromagnetic shielding materials, e.g. EMI, RFI shielding comprising a plurality of shielding layers; combining different shielding material structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007Casings
    • H05K9/006Casings specially adapted for signal processing applications, e.g. CATV, tuner, antennas amplifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Signal Processing (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Transceivers (AREA)

Abstract

本申请公开了一种EMI屏蔽材料。该EMI屏蔽材料包括相互混合的树脂材料和金属颗粒,其中所述金属颗粒的表面具有绝缘保护层。本申请还公开了一种通信模块产品,包括设置在基板上的模块元件,其中需要EMI屏蔽的所述模块元件的周边被填充有上述的屏蔽材料。本申请还公开了一种EMI屏蔽工艺,包括以下步骤:a、制备其上设置有模块元件的通信模块;和b、在所述通信模块上需要做EMI屏蔽的模块元件区域施加上述的屏蔽材料。该屏蔽材料可以实现对需要屏蔽的芯片区域的包裹性屏蔽,即对芯片的6个表面或6个方向都进行包裹性屏蔽,并且可以对芯片与芯片之间进行屏蔽,结合现有的屏蔽工艺可以实现从低频到高频的良好屏蔽,同时具有很低的工艺成本。

Description

一种EMI屏蔽材料、EMI屏蔽工艺以及通信模块产品
技术领域
本申请实施例涉及电磁领域,具体涉及一种EMI屏蔽材料、通信模块产品以及EMI屏蔽工艺。
背景技术
现有的EMI屏蔽技术主要是用于手机等蜂窝终端,随着频段的复杂、载波聚合需要邻近频段的同时使用,终端内部空间更小、集成度越来越高,模块之间的干扰成为一个难题,要保证通信效果和整机功耗,对模块之间的EMI屏蔽的要求越来越高,尤其是低频频段的屏蔽。随着通信技术的不断扩展,各类终端也必须广泛的应用高标准的EMI屏蔽工艺来保证通信模块的性能,包括各类智能终端,无人机,无人驾驶,汽车通信模块,IOT等等。
现有的EMI屏蔽技术主要包括共形EMI屏蔽结构和分段式EMI屏蔽结构。共形EMI屏蔽结构通过溅射或喷涂的方式施加金属屏蔽层,但是这种方式无法做到分段式屏蔽。而分段式EMI屏蔽结构往往针对每个芯片器件做出独立的屏蔽区域,具体需要通过挖槽以及填充或涂胶等方式来在器件之间形成分段式屏蔽结构。但是这种分段式工艺的制造成本高,工艺管控困难。另外,现有技术的屏蔽结构均未对芯片底部形成EMI屏蔽,并且具有较高的成本,不利于大批量生产。
发明内容
针对现有技术中的以上问题,本申请提出了一种改进的EMI屏蔽材料和EMI屏蔽工艺,以及施加了如上屏蔽材料和工艺的通信模块产品。
根据本发明的一方面,提出了一种EMI屏蔽材料,包括相互混合的树脂材料和金属颗粒,所述金属颗粒的表面具有绝缘保护层。该EMI屏蔽材料由于同时具有非常好的屏蔽性和绝缘性,从而可以被直接施加于射频模块上,并且具有非常低的制造成本和施工成本,非常利于量产。
在优选实施例中,所述屏蔽材料还混合有一定比例的二氧化硅颗粒。二氧化硅颗粒的添加可以降低所述屏蔽材料的膨胀系数。
在优选实施例中,所述屏蔽材料还混合有一定比例的氧化铝颗粒。氧化铝颗粒的添加可以降低屏蔽材料的散热系数。
在优选实施例中,所述金属颗粒在所述屏蔽材料中的重量占比是1-95%,所述金属颗粒的直径在0.1-30um之间。该占比可以根据所需的EMI屏蔽效果进行选择,越高的占比具有越好的屏蔽效果,而由于金属颗粒本身带有绝缘保护层,所以高占比的金属颗粒并不影响屏蔽材料的绝缘性。
在优选实施例中,所述二氧化硅颗粒在所述屏蔽材料中的重量占比为1-40%,所述二氧化硅颗粒的大小在0.1um-30um之间。其占比和大小根据实际需求来确定。
在优选实施例中,所述氧化铝在所述屏蔽材料中的重量占比为1-40%,所述氧化铝颗粒的大小在0.1um-30um之间。其占比和大小根据实际需求来确定。
在优选实施例中,所述屏蔽材料还包括重量占比0.1-0.2%的固化剂。固化剂的加入可便于屏蔽材料的凝固。
在优选实施例中,所述树脂材料在所述屏蔽材料中的重量占比为1%-30%。在优选实施例中,所述金属颗粒的材质包括银、金、铜、铬、镍、镍铁、由以上两种以上金属组成的合金或由以上金属或合金组成的复合梯度材料。对于不同的屏蔽需要(例如针对低频干扰或高频干扰)可以选择不同材质的金属颗粒。
在优选实施例中,所述金属颗粒包括混杂的不同材质的金属颗粒。当然也可以根据全频率的屏蔽需要同时选择不同材质的金属颗粒。
在优选实施例中,所述金属颗粒上的所述绝缘保护层为树脂、铁氟龙、氮化硅或氧化硅涂层,厚度在1nm-5000nm之间。绝缘保护层的存在保证了金属颗粒的绝缘性,从而实现了屏蔽材料整体上的绝缘性。
根据本发明的另一方面,提出了一种通信模块产品,包括设置在基板上的模块元件,其中需要EMI屏蔽的所述模块元件的周边被填充有如上文所述的屏蔽材料。通过简单地在模块元件周边填充本申请所要求保护的屏蔽材料可以实现很好的屏蔽效果,同时不需要施加针对模块元件另外的绝缘保护材料。该模块元件可以是电阻、电容或合路器等任何器件。
在优选实施例中,所述模块元件与所述基板之间以及所述模块元件的顶部被填充有所述屏蔽材料。通过模块元件的顶部和底部均填充屏蔽材料,可以对模块元件本体的六个方向进行屏蔽,包括两个模块元件之间的屏蔽,同时起到现有技术中的分段式屏蔽和共体屏蔽的效果。
在优选实施例中,所述模块元件的顶部处的所述屏蔽材料具有大于30um的厚度。申请人发现,该厚度要求可以很好实现所需的屏蔽效果。
在优选实施例中,所述通信模块产品的外部由金属屏蔽层包覆。额外的金属屏蔽层的施加达到双层屏蔽的效果,可以实现对通信模块产品更好的屏蔽。
根据本发明的另一方面,提出了一种EMI屏蔽工艺,包括以下步骤:a、制备其上设置有模块元件的通信模块;和b、在所述通信模块上需要做EMI屏蔽的模块元件区域施加上文所述的屏蔽材料。该屏蔽工艺施工简单,成本低廉,非常利于量产,但是同时达到相对于现有工艺更好的屏蔽效果。
在优选实施例中,所述施加步骤利用印刷和/或点胶工艺。
在优选实施例中,所述印刷工艺具体包括在所述通信模块上需要覆盖的区域使用定制的网版,然后印刷所述屏蔽材料。
在优选实施例中,所述印刷工艺优选是真空印刷。经过发明人的实验证明,真空印刷可以实现更好的施加效果。
在优选实施例中,点胶工艺具体包括通过点胶的方式实现在模块元件的底部和顶部填充或覆盖屏蔽材料。
在优选实施例中,所述方法还包括以下步骤:c、在施加了所述屏蔽材料后的通信模块上进行注塑。通过注塑可以在通信模块外部形成均匀的表面,便于后续工艺的施加。
在优选实施例中,所述方法还包括以下步骤:d、在注塑后的通信模块外层进行溅射或喷涂以形成金属屏蔽层。这实现了双层屏蔽层的形成。
附图说明
包括附图以提供对实施例的进一步理解并且附图被并入本说明书中并且构成本说明书的一部分。附图图示了实施例并且与描述一起用于解释本发明的原理。将容易认识到其它实施例和实施例的很多预期优点,因为通过引用以下详细描述,它们变得被更好地理解。附图的元件不一定是相互按照比例的。同样的附图标记指代对应的类似部件。
图1示出了现有技术中的共形EMI屏蔽结构的示意图;
图2示出了现有技术中的分段式EMI屏蔽结构的示意图;
图3示出了根据本发明的实施例的屏蔽材料中的金属颗粒的结构示意图;
图4示出了根据本发明的实施例的EMI屏蔽结构的示意图;
图5示出了根据本发明的另一实施例的EMI屏蔽结构的示意图;
图6a-d示出了根据本发明的实施例的EMI屏蔽工艺的流程图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释相关发明,而非对该发明的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与有关发明相关的部分。
需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
图1示出了现有技术中的共形EMI屏蔽结构的示意图。其中可以看出,射频通信模块产品101上设置有滤波器、低噪声放大器(LNA)、低通滤波器(LPF)、合路器、开关、运算放大器(PA)等芯片102。在需要做EMI屏蔽的射频通信模块产品101上设置有金属屏蔽层103。该金属屏蔽层103一般是通过在产品上溅射铜靶材或者喷涂银浆材料来施加的。该金属屏蔽层103的施加工艺简单,但是对高频屏蔽效果差,并且无法做到分段式屏蔽。
图2示出了现有技术中的分段式EMI屏蔽结构的示意图。其中可看出,射频通信模块产品201上设置有芯片202。在芯片202之间设置了分段式屏蔽结构203,该分段式屏蔽结构203使得每个芯片期间都能够有独立的屏蔽区域,大幅度地提高了屏蔽效果。该分段式屏蔽结构一般通过在需要分段屏蔽的芯片周围挖槽再溅射、喷涂或填充导电材料(或者通过wire bonding的方法在芯片之间形成屏蔽),最后完成模块外表面的金属屏蔽层204,为需要的任何区域形成隔离式的屏蔽效果。但是,现有技术中的分段式屏蔽的工艺复杂、成本高,尤其是对低频干扰的屏蔽效果不是很好。该低频主要是指500-800MHz的通信频段。
本申请公开的屏蔽技术的核心在于采用了特殊的屏蔽材料。该屏蔽材料包括相互混合的树脂材料和金属颗粒,并且该金属颗粒的表面具有绝缘保护层。该金属颗粒可以是如图3所示的金属球301。金属颗粒的形状不限于球形或圆形,也可以是扁形或椭圆形等其他形状,或者是由不同尺寸或形状的颗粒进行混合配制。
该金属球的表面设置有纳米级树脂涂层以形成绝缘保护层302,另外该金属球可以是单一金属球(如图3中的左图所示)或复合金属球(如图3中的右图所示)。当然,金属颗粒也可以具有除了球之外的形状。另外,金属颗粒的材质可以根据不同的屏蔽效果来确定,例如可以是金、银、铜、铬、镍或镍铁,或者是两种以上金属组成的合金,或者是由以上金属或合金组成的复合梯度材料,例如由多层金属或合金组成的多层金属复合而成的金属颗粒。其中银的屏蔽效果最好,镍铁对低频信号的屏蔽效果更好。在实际操作中,可以根据需要选择不同种类的金属颗粒混合在最终的屏蔽材料中,例如以实现更全面的屏蔽效果。而树脂材料可以采用环氧树脂或有机硅胶等,其可以根据不同需求来选择。金属颗粒的尺寸可以是0.1um-30um,在屏蔽材料中的重量占比可以是1-95%。该尺寸和占比是根据屏蔽的需要来灵活选择的。可以根据不同金属成分比例对应的EMI屏蔽效果来确定。
在优选方案中,绝缘保护层的厚度可以在1nm-5000nm之间。绝缘保护层的设置可以确保该屏蔽材料是绝缘的,因此可以直接被施加在芯片模块上以实现干扰屏蔽效果,而不需在芯片模块上提前包覆绝缘材料。而具体厚度的选择可以根据可靠性和导热性的要求来确定。绝缘保护层优选是纳米级的,具体可以选用树脂、铁氟龙、氮化硅或氧化硅这些材料。
在优选方案中,可以在屏蔽材料中加入二氧化硅颗粒以降低屏蔽材料的膨胀系数,并且可以加入氧化铝颗粒以提高散热系数。其中二氧化硅颗粒的尺寸可以在0.1um-30um之间,氧化铝颗粒的尺寸可以在0.1um-30um之间。而二氧化硅和氧化铝颗粒两者在所述屏蔽材料中的重量占比可以是1-40%。二氧化硅颗粒或氧化铝颗粒的形状不限于球形或圆形,也可以是扁形或椭圆形等其他形状,或者是不同尺寸或形状的二氧化硅颗粒或氧化铝颗粒进行混合配制。
图4示出了根据本发明的实施例的屏蔽材料中的金属颗粒的结构示意图。其中示出了施加了如本申请所述的EMI屏蔽材料后,即封装完成后的通信模块产品。从图4可看出,该通信模块产品包括设置在基板401上的模块元件402,其中需要EMI屏蔽的所述模块元件402的周边被填充有如上文所述的屏蔽材料403。由此在模块元件402之间形成了分段式屏蔽,该屏蔽并没有区域限制和对模块元件402的限制,甚至可以在电容、电阻、电感等任何其他元件之间或局部可以形成这样的屏蔽结构。尤其是,在模块元件402的顶部和底部(即模块元件402与基板401之间)均填充有屏蔽材料,因此可以实现对模块元件402的独特的包裹性屏蔽。模块元件底部EMI屏蔽区域的形成大大提升了模块元件402底部的屏蔽效果,解决了行业的痛点问题。而由于本申请所公开的屏蔽材料本身在含有金属颗粒的同时是非导电的,其并不影响模块元件402的工作。而模块元件402顶部的屏蔽材料的厚度优选大于30um,以在模块元件402上方区域获得更好的屏蔽效果,因此最后可以在模块元件402的六个方向上进行屏蔽,也可以在多个模块元件402之间进行屏蔽。
该通信模块产品可以是在无线蜂窝终端中使用过的射频模块产品,该无线蜂窝终端可以是2G/3G/4G/5G的手机、WiFi设备、Pad、智能手表、IOT设备和车载终端等。而通信模块产品上的模块元件402例如可以是滤波器、开关、低噪声放大器、运算放大器、调谐器或前者的组合。
图5示出了根据本发明的实施例的EMI屏蔽结构的示意图。图5所示的实施例与图4的区别在于,在通信模块产品的外部设置有外层金属屏蔽层504,从而实现了双层屏蔽,可以达到更好的低频屏蔽效果。
图6a-d示出了根据本发明的实施例的EMI屏蔽工艺的流程图。首先如图6a所示,将模块元件402SMT贴装到基板上,完成焊接和清洗。该模块元件402可以包括滤波器芯片、低噪声放大器(LNA)、开关和运算放大器(PA)等芯片,也可以是电阻、电容、电感或者合路器,LPF等任何元件。当然,SMT仅仅是示例的一种方式,也通过其他工艺安装模块元件。
图6b所示,使用本申请公开的屏蔽材料,通过印刷或点胶工艺施加到基板401上以覆盖并且填充需要做屏蔽的芯片区域。点胶工艺具体包括通过点胶的方式实现在模块元件的底部和顶部填充或覆盖屏蔽材料。由于该屏蔽材料的独特性质,可以通过印刷工艺实现EMI屏蔽材料的施加,具体包括在需要覆盖的区域使用定制的网版601,然后通过印刷屏蔽材料的方式完成覆盖。该网版601可以是金属或塑胶材质。在印刷后,可以通过刮刀602将多余的屏蔽材料603去除。在优选的方案中,可以通过真空印刷的方式施加屏蔽材料,该方式可以使得屏蔽材料更好地进入模块元件402的底部和之间的区域,从而实现更充分的填充。当然,也可以通过在模块元件402底部填充胶的方式完成对模块元件402区域底部和上方的覆盖,从而很好地降低了模块元件402之间(包括模块元件402内部)的射频信号干扰。可以看到的是,该屏蔽材料的施加不需要额外的开槽和框架制作,因此具有很低的工艺难度和成本。
如图6c所示,在施加了屏蔽材料后的通信模块产品上进行注塑,以在产品外包覆注塑材料604。然后在如图6d所示的步骤中,通过溅射或喷涂的方式在产品最外层形成金属屏蔽层605。应当认识到,该步骤是可选的。最终使得封装后的产品同时具备分段式屏蔽和双层屏蔽的效果。通过发明人的实际测试,这样的屏蔽工艺可以使得在500MHz-6GHz的范围内达到40dB的屏蔽效果。
以上描述了本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。
在本申请的描述中,需要理解的是,术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。措词‘包括’并不排除在权利要求未列出的元件或步骤的存在。元件前面的措词‘一’或‘一个’并不排除多个这样的元件的存在。在相互不同从属权利要求中记载某些措施的简单事实不表明这些措施的组合不能被用于改进。在权利要求中的任何参考符号不应当被解释为限制范围。

Claims (23)

1.一种通信模块产品,包括设置在基板上的模块元件,其特征在于,需要EMI屏蔽的所述模块元件本体的周边被填充有EMI屏蔽材料以在所述模块元件之间形成分段式屏蔽,所述EMI屏蔽材料包括相互混合的树脂材料和金属颗粒,所述金属颗粒的表面具有绝缘保护层,所述金属颗粒上的所述绝缘保护层为树脂、铁氟龙、氮化硅或氧化硅涂层。
2.根据权利要求1所述的通信模块产品,其特征在于,所述模块元件与所述基板之间以及所述模块元件的顶部被填充有所述屏蔽材料。
3.根据权利要求1所述的通信模块产品,其特征在于,所述模块元件的顶部处的所述屏蔽材料具有大于30um的厚度。
4.根据权利要求1所述的通信模块产品,其特征在于,所述通信模块产品的外部由金属屏蔽层包覆。
5.根据权利要求1所述的通信模块产品,其特征在于,所述屏蔽材料还混合有一定比例的二氧化硅颗粒。
6.根据权利要求1或5所述的通信模块产品,其特征在于,所述屏蔽材料还混合有一定比例的氧化铝颗粒。
7.根据权利要求1所述的通信模块产品,其特征在于,所述金属颗粒在所述屏蔽材料中的重量占比是1-95%。
8.根据权利要求5所述的通信模块产品,其特征在于,所述二氧化硅颗粒在所述屏蔽材料中的重量占比为1-40%。
9.根据权利要求6所述的通信模块产品,其特征在于,所述氧化铝在所述屏蔽材料中的重量占比为1-40%。
10.根据权利要求1所述的通信模块产品,其特征在于,所述屏蔽材料还包括重量占比0.1-0.2%的固化剂。
11.根据权利要求1所述的通信模块产品,其特征在于,所述树脂材料在所述屏蔽材料中的重量占比为1%-30%。
12.根据权利要求1所述的通信模块产品,其特征在于,所述金属颗粒的尺寸大小在0.1um-30um之间。
13.根据权利要求5所述的通信模块产品,其特征在于,所述二氧化硅颗粒的尺寸大小在0.1um-30um之间。
14.根据权利要求6所述的通信模块产品,其特征在于,所述氧化铝颗粒的尺寸大小在0.1um-30um之间。
15.根据权利要求1所述的通信模块产品,其特征在于,所述金属颗粒的材质包括银、金、铜、铬、镍、镍铁、由以上两种以上金属组成的合金或由以上金属或合金组成的复合梯度材料。
16.根据权利要求15所述的通信模块产品,其特征在于,所述金属颗粒包括混杂的不同材质的金属颗粒。
17.根据权利要求1所述的通信模块产品,其特征在于,所述金属颗粒上的所述绝缘保护层为树脂、铁氟龙、氮化硅或氧化硅涂层,厚度在1nm-5000nm之间。
18.一种EMI屏蔽工艺,包括以下步骤:
a、制备其上设置有模块元件的通信模块;和
b、在所述通信模块上需要做EMI屏蔽的模块元件区域利用印刷和/或点胶工艺施加有EMI屏蔽材料以在所述模块元件之间形成分段式屏蔽,所述EMI屏蔽材料包括相互混合的树脂材料和金属颗粒,所述金属颗粒的表面具有绝缘保护层,所述金属颗粒上的所述绝缘保护层为树脂、铁氟龙、氮化硅或氧化硅涂层。
19.根据权利要求18所述的EMI屏蔽工艺,其特征在于,所述印刷工艺具体包括在所述通信模块上需要覆盖的区域使用定制的网版,然后印刷所述EMI屏蔽材料。
20.根据权利要求19所述的EMI屏蔽工艺,其特征在于,所述印刷工艺包括真空印刷。
21.根据权利要求18所述的EMI屏蔽工艺,其特征在于,所述点胶工艺具体包括通过点胶的方式实现在所述模块元件的底部和顶部填充或覆盖所述EMI屏蔽材料。
22.根据权利要求18-21中任一项所述的EMI屏蔽工艺,其特征在于,还包括以下步骤:
c、在施加了所述EMI屏蔽材料后的通信模块上进行注塑。
23.根据权利要求22所述的EMI屏蔽工艺,其特征在于,还包括以下步骤:
d、在注塑后的通信模块外层进行溅射或喷涂以形成金属屏蔽层。
CN201911014276.4A 2019-10-23 2019-10-23 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品 Active CN110752189B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201911014276.4A CN110752189B (zh) 2019-10-23 2019-10-23 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品
EP20879295.2A EP4036962A4 (en) 2019-10-23 2020-09-11 ELECTROMAGNETIC INTERFERENCE SHIELDING MATERIAL, ELECTROMAGNETIC INTERFERENCE SHIELDING METHOD AND COMMUNICATION MODULE PRODUCT
JP2022523920A JP2022552897A (ja) 2019-10-23 2020-09-11 Emiシールド工程及び通信モジュール製品
US17/771,014 US11770920B2 (en) 2019-10-23 2020-09-11 EMI shielding material, EMI shielding process, and communication module product
PCT/CN2020/114836 WO2021077937A1 (zh) 2019-10-23 2020-09-11 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911014276.4A CN110752189B (zh) 2019-10-23 2019-10-23 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品

Publications (2)

Publication Number Publication Date
CN110752189A CN110752189A (zh) 2020-02-04
CN110752189B true CN110752189B (zh) 2020-08-21

Family

ID=69279601

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911014276.4A Active CN110752189B (zh) 2019-10-23 2019-10-23 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品

Country Status (5)

Country Link
US (1) US11770920B2 (zh)
EP (1) EP4036962A4 (zh)
JP (1) JP2022552897A (zh)
CN (1) CN110752189B (zh)
WO (1) WO2021077937A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110752189B (zh) 2019-10-23 2020-08-21 杭州见闻录科技有限公司 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品
CN115868019A (zh) * 2020-09-30 2023-03-28 株式会社村田制作所 高频模块以及通信装置
CN112616305A (zh) * 2020-12-30 2021-04-06 湘潭市神钜机电科技有限公司 电子设备的抗核屏蔽结构及制作方法、电子设备
CN114188312B (zh) * 2022-02-17 2022-07-08 甬矽电子(宁波)股份有限公司 封装屏蔽结构和屏蔽结构制作方法
CN118471832A (zh) * 2024-07-12 2024-08-09 威海嘉瑞光电科技股份有限公司 一种集成电路装置及其制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019167778A1 (ja) * 2018-02-27 2019-09-06 Dic株式会社 電子部品パッケージ及びその製造方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372886A (en) * 1989-03-28 1994-12-13 Sumitomo Electric Industries, Ltd. Insulated wire with an intermediate adhesion layer and an insulating layer
KR100533097B1 (ko) * 2000-04-27 2005-12-02 티디케이가부시기가이샤 복합자성재료와 이것을 이용한 자성성형재료, 압분 자성분말성형재료, 자성도료, 복합 유전체재료와 이것을이용한 성형재료, 압분성형 분말재료, 도료, 프리프레그및 기판, 전자부품
WO2006076603A2 (en) * 2005-01-14 2006-07-20 Cabot Corporation Printable electrical conductors
DE112008000327T5 (de) 2007-02-06 2009-12-31 World Properties, Inc., Lincolnwood Leitfähige Polymerschäume, Herstellungsverfahren und Anwendungen derselben
CN101191007B (zh) * 2007-11-23 2010-09-08 武汉理工大学 一种含金属颗粒的树脂基复合材料的制备方法
US8059425B2 (en) * 2008-05-28 2011-11-15 Azurewave Technologies, Inc. Integrated circuit module with temperature compensation crystal oscillator
JP5316051B2 (ja) * 2009-02-12 2013-10-16 住友電装株式会社 電気接続箱
US9167736B2 (en) * 2010-01-15 2015-10-20 Applied Nanostructured Solutions, Llc CNT-infused fiber as a self shielding wire for enhanced power transmission line
JP2012151326A (ja) * 2011-01-20 2012-08-09 Toshiba Corp 半導体装置の製造方法、半導体装置及び電子部品のシールド方法
KR20130035620A (ko) * 2011-09-30 2013-04-09 삼성전자주식회사 Emi 쉴드된 반도체 패키지 및 emi 쉴드된 기판 모듈
CN103571215A (zh) * 2012-07-18 2014-02-12 天瑞企业股份有限公司 高导热及emi遮蔽的高分子复合材
JP5466785B1 (ja) * 2013-08-12 2014-04-09 太陽誘電株式会社 回路モジュール及びその製造方法
KR102161173B1 (ko) * 2013-08-29 2020-09-29 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
CN103496228B (zh) * 2013-08-29 2016-07-13 北京工业大学 一种电磁屏蔽用结构型导电硅橡胶及制备
KR20160050012A (ko) * 2013-09-03 2016-05-10 산요오도꾸슈세이꼬 가부시키가이샤 자성부재용 절연피복분말
TW201513275A (zh) * 2013-09-17 2015-04-01 Chipmos Technologies Inc 晶片封裝結構及其製作方法
CN203690294U (zh) * 2013-11-07 2014-07-02 新科实业有限公司 电子元件组件
WO2016117575A1 (ja) * 2015-01-22 2016-07-28 住友電気工業株式会社 プリント配線板用基材、プリント配線板及びプリント配線板の製造方法
JP6477124B2 (ja) * 2015-03-26 2019-03-06 Tdk株式会社 軟磁性金属圧粉コア、及び、リアクトルまたはインダクタ
US10242954B2 (en) * 2016-12-01 2019-03-26 Tdk Corporation Electronic circuit package having high composite shielding effect
US9818518B2 (en) * 2016-03-31 2017-11-14 Tdk Corporation Composite magnetic sealing material
US9881877B2 (en) * 2016-03-31 2018-01-30 Tdk Corporation Electronic circuit package using composite magnetic sealing material
JP6536539B2 (ja) 2016-03-31 2019-07-03 Tdk株式会社 複合磁性封止材料を用いた電子回路パッケージ
US9685413B1 (en) * 2016-04-01 2017-06-20 Intel Corporation Semiconductor package having an EMI shielding layer
CN107507823B (zh) 2016-06-14 2022-12-20 三星电子株式会社 半导体封装和用于制造半导体封装的方法
KR102620863B1 (ko) * 2016-08-19 2024-01-05 에스케이하이닉스 주식회사 전자기간섭 차폐층을 갖는 반도체 패키지 및 그 제조방법
CN106961826A (zh) * 2017-03-27 2017-07-18 保定乐凯新材料股份有限公司 一种可重复贴装使用的电磁波防护膜
CN107452696B (zh) * 2017-08-10 2019-11-01 华进半导体封装先导技术研发中心有限公司 电磁屏蔽封装体以及制造方法
CN207489847U (zh) * 2017-10-13 2018-06-12 中芯长电半导体(江阴)有限公司 Emi防护的芯片封装结构
JP6770050B2 (ja) * 2017-12-29 2020-10-14 エヌトリウム インコーポレイテッド 電磁波保護層を有する電子装置及びその製造方法
US11804420B2 (en) * 2018-06-27 2023-10-31 Intel Corporation Core-shell particles for magnetic packaging
CN110752189B (zh) * 2019-10-23 2020-08-21 杭州见闻录科技有限公司 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019167778A1 (ja) * 2018-02-27 2019-09-06 Dic株式会社 電子部品パッケージ及びその製造方法

Also Published As

Publication number Publication date
US11770920B2 (en) 2023-09-26
EP4036962A4 (en) 2022-11-23
JP2022552897A (ja) 2022-12-20
CN110752189A (zh) 2020-02-04
EP4036962A1 (en) 2022-08-03
WO2021077937A1 (zh) 2021-04-29
US20220418174A1 (en) 2022-12-29

Similar Documents

Publication Publication Date Title
CN110752189B (zh) 一种emi屏蔽材料、emi屏蔽工艺以及通信模块产品
JP6469572B2 (ja) アンテナ一体型無線モジュールおよびこのモジュールの製造方法
US8350368B2 (en) Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
US8791862B1 (en) Semiconductor package having integrated antenna pad
JP2003273571A (ja) 素子間干渉電波シールド型高周波モジュール
CN110277356A (zh) 天线馈电线的封装结构及封装方法
CN103258817B (zh) 半导体封装结构及其制造方法
US10978779B2 (en) Sputtered SIP antenna
TWI744572B (zh) 具有封裝內隔室屏蔽的半導體封裝及其製作方法
CN110752163A (zh) 一种用于通信模块产品的emi屏蔽工艺和通信模块产品
CN109545503A (zh) 电子组件
CN108807360A (zh) 半导体封装设备和制造半导体封装设备的方法
CN111585002B (zh) 双向喇叭封装天线结构、其制作方法和电子设备
WO2019102726A1 (ja) チップインダクタ
CN210129510U (zh) 天线外置在封装体表面的射频封装结构
JP2010258137A (ja) 高周波モジュールおよびその製造方法
CN100418223C (zh) 可整合微型天线的系统芯片
CN209434180U (zh) 天线封装结构
JP6839037B2 (ja) インダクタンス素子およびその製造方法ならびに電子・電気機器
JP2003298004A (ja) 素子間干渉電波シールド型高周波モジュール及び電子装置
CN109979922A (zh) 天线封装结构及封装方法
CN217306496U (zh) 一种含射频芯片的集成电路封装结构
US11211340B2 (en) Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding
KR102378155B1 (ko) 패키지 내 구획 차폐물 및 능동 전자기 적합성 차폐물을 갖는 반도체 패키지
CN110190045A (zh) 天线外置在封装体表面的射频封装结构及封装方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: 1219-23, building 3, No. 1366, Hongfeng Road, Kangshan street, Huzhou City, Zhejiang Province, 313000

Patentee after: Jianwenlu (Zhejiang) Semiconductor Co.,Ltd.

Address before: 310019 room 1004, 10th floor, building 4, No. 9, Jiuhuan Road, Jianggan District, Hangzhou City, Zhejiang Province

Patentee before: Hangzhou Wenwenlu Technology Co.,Ltd.

TR01 Transfer of patent right

Effective date of registration: 20210222

Address after: 313001 1219-11, building 3, No. 1366, Hongfeng Road, Kangshan street, Huzhou Economic and Technological Development Zone, Huzhou City, Zhejiang Province

Patentee after: Huzhou jianwenlu Technology Co.,Ltd.

Address before: 1219-23, building 3, No. 1366, Hongfeng Road, Kangshan street, Huzhou City, Zhejiang Province, 313000

Patentee before: Jianwenlu (Zhejiang) Semiconductor Co.,Ltd.

TR01 Transfer of patent right
PE01 Entry into force of the registration of the contract for pledge of patent right
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: The invention relates to an EMI shielding material, an EMI shielding process and a communication module product

Effective date of registration: 20210528

Granted publication date: 20200821

Pledgee: Huzhou Jinsheng equity investment partnership (L.P.)

Pledgor: Huzhou jianwenlu Technology Co.,Ltd.

Registration number: Y2021330000478

PC01 Cancellation of the registration of the contract for pledge of patent right
PC01 Cancellation of the registration of the contract for pledge of patent right

Granted publication date: 20200821

Pledgee: Huzhou Jinsheng equity investment partnership (L.P.)

Pledgor: Huzhou jianwenlu Technology Co.,Ltd.

Registration number: Y2021330000478

PE01 Entry into force of the registration of the contract for pledge of patent right
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: An EMI shielding material, EMI shielding process, and communication module product

Granted publication date: 20200821

Pledgee: Huzhou Jinsheng equity investment partnership (L.P.)

Pledgor: Huzhou jianwenlu Technology Co.,Ltd.

Registration number: Y2024330001218